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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5declare i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %a)6declare i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %a)7declare i16 @llvm.vector.reduce.umax.v1i16(<1 x i16> %a)8declare i24 @llvm.vector.reduce.umax.v1i24(<1 x i24> %a)9declare i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %a)10declare i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> %a)11declare i128 @llvm.vector.reduce.umax.v1i128(<1 x i128> %a)12 13declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %a)14declare i8 @llvm.vector.reduce.umax.v3i8(<3 x i8> %a)15declare i8 @llvm.vector.reduce.umax.v9i8(<9 x i8> %a)16declare i32 @llvm.vector.reduce.umax.v3i32(<3 x i32> %a)17declare i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> %a)18declare i24 @llvm.vector.reduce.umax.v4i24(<4 x i24> %a)19declare i128 @llvm.vector.reduce.umax.v2i128(<2 x i128> %a)20declare i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %a)21 22define i1 @test_v1i1(<1 x i1> %a) nounwind {23; CHECK-LABEL: test_v1i1:24; CHECK: // %bb.0:25; CHECK-NEXT: and w0, w0, #0x126; CHECK-NEXT: ret27 %b = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %a)28 ret i1 %b29}30 31define i8 @test_v1i8(<1 x i8> %a) nounwind {32; CHECK-LABEL: test_v1i8:33; CHECK: // %bb.0:34; CHECK-NEXT: // kill: def $d0 killed $d0 def $q035; CHECK-NEXT: umov w0, v0.b[0]36; CHECK-NEXT: ret37 %b = call i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %a)38 ret i8 %b39}40 41define i16 @test_v1i16(<1 x i16> %a) nounwind {42; CHECK-LABEL: test_v1i16:43; CHECK: // %bb.0:44; CHECK-NEXT: // kill: def $d0 killed $d0 def $q045; CHECK-NEXT: umov w0, v0.h[0]46; CHECK-NEXT: ret47 %b = call i16 @llvm.vector.reduce.umax.v1i16(<1 x i16> %a)48 ret i16 %b49}50 51define i24 @test_v1i24(<1 x i24> %a) nounwind {52; CHECK-LABEL: test_v1i24:53; CHECK: // %bb.0:54; CHECK-NEXT: ret55 %b = call i24 @llvm.vector.reduce.umax.v1i24(<1 x i24> %a)56 ret i24 %b57}58 59define i32 @test_v1i32(<1 x i32> %a) nounwind {60; CHECK-SD-LABEL: test_v1i32:61; CHECK-SD: // %bb.0:62; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q063; CHECK-SD-NEXT: fmov w0, s064; CHECK-SD-NEXT: ret65;66; CHECK-GI-LABEL: test_v1i32:67; CHECK-GI: // %bb.0:68; CHECK-GI-NEXT: fmov w0, s069; CHECK-GI-NEXT: ret70 %b = call i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %a)71 ret i32 %b72}73 74define i64 @test_v1i64(<1 x i64> %a) nounwind {75; CHECK-SD-LABEL: test_v1i64:76; CHECK-SD: // %bb.0:77; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q078; CHECK-SD-NEXT: fmov x0, d079; CHECK-SD-NEXT: ret80;81; CHECK-GI-LABEL: test_v1i64:82; CHECK-GI: // %bb.0:83; CHECK-GI-NEXT: fmov x0, d084; CHECK-GI-NEXT: ret85 %b = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> %a)86 ret i64 %b87}88 89define i128 @test_v1i128(<1 x i128> %a) nounwind {90; CHECK-LABEL: test_v1i128:91; CHECK: // %bb.0:92; CHECK-NEXT: ret93 %b = call i128 @llvm.vector.reduce.umax.v1i128(<1 x i128> %a)94 ret i128 %b95}96 97; No i64 vector support for UMAX.98define i64 @test_v2i64(<2 x i64> %a) nounwind {99; CHECK-SD-LABEL: test_v2i64:100; CHECK-SD: // %bb.0:101; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8102; CHECK-SD-NEXT: cmhi d2, d0, d1103; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b104; CHECK-SD-NEXT: fmov x0, d0105; CHECK-SD-NEXT: ret106;107; CHECK-GI-LABEL: test_v2i64:108; CHECK-GI: // %bb.0:109; CHECK-GI-NEXT: mov d1, v0.d[1]110; CHECK-GI-NEXT: fmov x8, d0111; CHECK-GI-NEXT: fmov x9, d1112; CHECK-GI-NEXT: cmp x8, x9113; CHECK-GI-NEXT: fcsel d0, d0, d1, hi114; CHECK-GI-NEXT: fmov x0, d0115; CHECK-GI-NEXT: ret116 %b = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %a)117 ret i64 %b118}119 120define i8 @test_v3i8(<3 x i8> %a) nounwind {121; CHECK-SD-LABEL: test_v3i8:122; CHECK-SD: // %bb.0:123; CHECK-SD-NEXT: movi v0.2d, #0000000000000000124; CHECK-SD-NEXT: mov v0.h[0], w0125; CHECK-SD-NEXT: mov v0.h[1], w1126; CHECK-SD-NEXT: mov v0.h[2], w2127; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8128; CHECK-SD-NEXT: umaxv h0, v0.4h129; CHECK-SD-NEXT: fmov w0, s0130; CHECK-SD-NEXT: ret131;132; CHECK-GI-LABEL: test_v3i8:133; CHECK-GI: // %bb.0:134; CHECK-GI-NEXT: and w8, w0, #0xff135; CHECK-GI-NEXT: cmp w8, w1, uxtb136; CHECK-GI-NEXT: csel w8, w0, w1, hi137; CHECK-GI-NEXT: and w9, w8, #0xff138; CHECK-GI-NEXT: cmp w9, w2, uxtb139; CHECK-GI-NEXT: csel w0, w8, w2, hi140; CHECK-GI-NEXT: ret141 %b = call i8 @llvm.vector.reduce.umax.v3i8(<3 x i8> %a)142 ret i8 %b143}144 145define i8 @test_v9i8(<9 x i8> %a) nounwind {146; CHECK-SD-LABEL: test_v9i8:147; CHECK-SD: // %bb.0:148; CHECK-SD-NEXT: adrp x8, .LCPI9_0149; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI9_0]150; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b151; CHECK-SD-NEXT: umaxv b0, v0.16b152; CHECK-SD-NEXT: fmov w0, s0153; CHECK-SD-NEXT: ret154;155; CHECK-GI-LABEL: test_v9i8:156; CHECK-GI: // %bb.0:157; CHECK-GI-NEXT: mov b1, v0.b[1]158; CHECK-GI-NEXT: umov w8, v0.b[0]159; CHECK-GI-NEXT: umov w9, v0.b[1]160; CHECK-GI-NEXT: umov w10, v0.b[2]161; CHECK-GI-NEXT: fmov w11, s1162; CHECK-GI-NEXT: cmp w8, w11, uxtb163; CHECK-GI-NEXT: umov w11, v0.b[3]164; CHECK-GI-NEXT: csel w8, w8, w9, hi165; CHECK-GI-NEXT: umov w9, v0.b[4]166; CHECK-GI-NEXT: cmp w10, w8, uxtb167; CHECK-GI-NEXT: csel w8, w8, w10, lo168; CHECK-GI-NEXT: umov w10, v0.b[5]169; CHECK-GI-NEXT: cmp w11, w8, uxtb170; CHECK-GI-NEXT: csel w8, w8, w11, lo171; CHECK-GI-NEXT: umov w11, v0.b[6]172; CHECK-GI-NEXT: cmp w9, w8, uxtb173; CHECK-GI-NEXT: csel w8, w8, w9, lo174; CHECK-GI-NEXT: umov w9, v0.b[7]175; CHECK-GI-NEXT: cmp w10, w8, uxtb176; CHECK-GI-NEXT: csel w8, w8, w10, lo177; CHECK-GI-NEXT: umov w10, v0.b[8]178; CHECK-GI-NEXT: cmp w11, w8, uxtb179; CHECK-GI-NEXT: csel w8, w8, w11, lo180; CHECK-GI-NEXT: cmp w9, w8, uxtb181; CHECK-GI-NEXT: csel w8, w8, w9, lo182; CHECK-GI-NEXT: cmp w10, w8, uxtb183; CHECK-GI-NEXT: csel w0, w8, w10, lo184; CHECK-GI-NEXT: ret185 %b = call i8 @llvm.vector.reduce.umax.v9i8(<9 x i8> %a)186 ret i8 %b187}188 189define i32 @test_v3i32(<3 x i32> %a) nounwind {190; CHECK-LABEL: test_v3i32:191; CHECK: // %bb.0:192; CHECK-NEXT: mov v0.s[3], wzr193; CHECK-NEXT: umaxv s0, v0.4s194; CHECK-NEXT: fmov w0, s0195; CHECK-NEXT: ret196 %b = call i32 @llvm.vector.reduce.umax.v3i32(<3 x i32> %a)197 ret i32 %b198}199 200define i1 @test_v4i1(<4 x i1> %a) nounwind {201; CHECK-SD-LABEL: test_v4i1:202; CHECK-SD: // %bb.0:203; CHECK-SD-NEXT: shl v0.4h, v0.4h, #15204; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0205; CHECK-SD-NEXT: umaxv h0, v0.4h206; CHECK-SD-NEXT: fmov w8, s0207; CHECK-SD-NEXT: and w0, w8, #0x1208; CHECK-SD-NEXT: ret209;210; CHECK-GI-LABEL: test_v4i1:211; CHECK-GI: // %bb.0:212; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0213; CHECK-GI-NEXT: umov w8, v0.h[0]214; CHECK-GI-NEXT: umov w9, v0.h[1]215; CHECK-GI-NEXT: umov w10, v0.h[2]216; CHECK-GI-NEXT: umov w11, v0.h[3]217; CHECK-GI-NEXT: and w12, w8, #0x1218; CHECK-GI-NEXT: and w13, w9, #0x1219; CHECK-GI-NEXT: cmp w12, w13220; CHECK-GI-NEXT: and w12, w10, #0x1221; CHECK-GI-NEXT: and w13, w11, #0x1222; CHECK-GI-NEXT: csel w8, w8, w9, hi223; CHECK-GI-NEXT: cmp w12, w13224; CHECK-GI-NEXT: csel w9, w10, w11, hi225; CHECK-GI-NEXT: and w10, w8, #0x1226; CHECK-GI-NEXT: and w11, w9, #0x1227; CHECK-GI-NEXT: cmp w10, w11228; CHECK-GI-NEXT: csel w8, w8, w9, hi229; CHECK-GI-NEXT: and w0, w8, #0x1230; CHECK-GI-NEXT: ret231 %b = call i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> %a)232 ret i1 %b233}234 235define i24 @test_v4i24(<4 x i24> %a) nounwind {236; CHECK-SD-LABEL: test_v4i24:237; CHECK-SD: // %bb.0:238; CHECK-SD-NEXT: bic v0.4s, #255, lsl #24239; CHECK-SD-NEXT: umaxv s0, v0.4s240; CHECK-SD-NEXT: fmov w0, s0241; CHECK-SD-NEXT: ret242;243; CHECK-GI-LABEL: test_v4i24:244; CHECK-GI: // %bb.0:245; CHECK-GI-NEXT: mov s1, v0.s[1]246; CHECK-GI-NEXT: mov s2, v0.s[2]247; CHECK-GI-NEXT: mov s3, v0.s[3]248; CHECK-GI-NEXT: fmov w8, s0249; CHECK-GI-NEXT: fmov w9, s1250; CHECK-GI-NEXT: fmov w10, s2251; CHECK-GI-NEXT: fmov w11, s3252; CHECK-GI-NEXT: and w8, w8, #0xffffff253; CHECK-GI-NEXT: and w9, w9, #0xffffff254; CHECK-GI-NEXT: cmp w8, w9255; CHECK-GI-NEXT: and w8, w10, #0xffffff256; CHECK-GI-NEXT: and w9, w11, #0xffffff257; CHECK-GI-NEXT: fcsel s0, s0, s1, hi258; CHECK-GI-NEXT: cmp w8, w9259; CHECK-GI-NEXT: fcsel s1, s2, s3, hi260; CHECK-GI-NEXT: fmov w8, s0261; CHECK-GI-NEXT: fmov w9, s1262; CHECK-GI-NEXT: and w8, w8, #0xffffff263; CHECK-GI-NEXT: and w9, w9, #0xffffff264; CHECK-GI-NEXT: cmp w8, w9265; CHECK-GI-NEXT: fcsel s0, s0, s1, hi266; CHECK-GI-NEXT: fmov w0, s0267; CHECK-GI-NEXT: ret268 %b = call i24 @llvm.vector.reduce.umax.v4i24(<4 x i24> %a)269 ret i24 %b270}271 272define i128 @test_v2i128(<2 x i128> %a) nounwind {273; CHECK-SD-LABEL: test_v2i128:274; CHECK-SD: // %bb.0:275; CHECK-SD-NEXT: cmp x2, x0276; CHECK-SD-NEXT: sbcs xzr, x3, x1277; CHECK-SD-NEXT: csel x0, x0, x2, lo278; CHECK-SD-NEXT: csel x1, x1, x3, lo279; CHECK-SD-NEXT: ret280;281; CHECK-GI-LABEL: test_v2i128:282; CHECK-GI: // %bb.0:283; CHECK-GI-NEXT: cmp x0, x2284; CHECK-GI-NEXT: cset w8, hi285; CHECK-GI-NEXT: cmp x1, x3286; CHECK-GI-NEXT: cset w9, hi287; CHECK-GI-NEXT: csel w8, w8, w9, eq288; CHECK-GI-NEXT: tst w8, #0x1289; CHECK-GI-NEXT: csel x0, x0, x2, ne290; CHECK-GI-NEXT: csel x1, x1, x3, ne291; CHECK-GI-NEXT: ret292 %b = call i128 @llvm.vector.reduce.umax.v2i128(<2 x i128> %a)293 ret i128 %b294}295 296define i32 @test_v16i32(<16 x i32> %a) nounwind {297; CHECK-SD-LABEL: test_v16i32:298; CHECK-SD: // %bb.0:299; CHECK-SD-NEXT: umax v1.4s, v1.4s, v3.4s300; CHECK-SD-NEXT: umax v0.4s, v0.4s, v2.4s301; CHECK-SD-NEXT: umax v0.4s, v0.4s, v1.4s302; CHECK-SD-NEXT: umaxv s0, v0.4s303; CHECK-SD-NEXT: fmov w0, s0304; CHECK-SD-NEXT: ret305;306; CHECK-GI-LABEL: test_v16i32:307; CHECK-GI: // %bb.0:308; CHECK-GI-NEXT: umax v0.4s, v0.4s, v1.4s309; CHECK-GI-NEXT: umax v1.4s, v2.4s, v3.4s310; CHECK-GI-NEXT: umax v0.4s, v0.4s, v1.4s311; CHECK-GI-NEXT: umaxv s0, v0.4s312; CHECK-GI-NEXT: fmov w0, s0313; CHECK-GI-NEXT: ret314 %b = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %a)315 ret i32 %b316}317