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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s3 4define <4 x i32> @test_compress_v4i32(<4 x i32> %vec, <4 x i1> %mask) {5; CHECK-LABEL: test_compress_v4i32:6; CHECK: ; %bb.0:7; CHECK-NEXT: sub sp, sp, #168; CHECK-NEXT: .cfi_def_cfa_offset 169; CHECK-NEXT: ushll.4s v1, v1, #010; CHECK-NEXT: mov x8, sp11; CHECK-NEXT: str s0, [sp]12; CHECK-NEXT: shl.4s v1, v1, #3113; CHECK-NEXT: cmlt.4s v1, v1, #014; CHECK-NEXT: mov.s w9, v1[1]15; CHECK-NEXT: fmov w11, s116; CHECK-NEXT: mov.s w10, v1[2]17; CHECK-NEXT: and x12, x11, #0x118; CHECK-NEXT: bfi x8, x11, #2, #119; CHECK-NEXT: mov x11, sp20; CHECK-NEXT: and x9, x9, #0x121; CHECK-NEXT: add x9, x12, x922; CHECK-NEXT: st1.s { v0 }[1], [x8]23; CHECK-NEXT: sub w10, w9, w1024; CHECK-NEXT: orr x9, x11, x9, lsl #225; CHECK-NEXT: bfi x11, x10, #2, #226; CHECK-NEXT: st1.s { v0 }[2], [x9]27; CHECK-NEXT: st1.s { v0 }[3], [x11]28; CHECK-NEXT: ldr q0, [sp], #1629; CHECK-NEXT: ret30 %out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> %mask, <4 x i32> undef)31 ret <4 x i32> %out32}33 34 35define <4 x i32> @test_compress_v4i32_with_passthru(<4 x i32> %vec, <4 x i1> %mask, <4 x i32> %passthru) {36; CHECK-LABEL: test_compress_v4i32_with_passthru:37; CHECK: ; %bb.0:38; CHECK-NEXT: str q2, [sp, #-16]!39; CHECK-NEXT: .cfi_def_cfa_offset 1640; CHECK-NEXT: ushll.4s v1, v1, #041; CHECK-NEXT: movi.4s v3, #142; CHECK-NEXT: mov x12, sp43; CHECK-NEXT: mov x10, sp44; CHECK-NEXT: mov x9, sp45; CHECK-NEXT: mov x14, sp46; CHECK-NEXT: mov w15, #3 ; =0x347; CHECK-NEXT: shl.4s v1, v1, #3148; CHECK-NEXT: cmlt.4s v1, v1, #049; CHECK-NEXT: and.16b v3, v1, v350; CHECK-NEXT: mov.s w8, v1[1]51; CHECK-NEXT: fmov w16, s152; CHECK-NEXT: mov.s w11, v1[2]53; CHECK-NEXT: mov.s w13, v1[3]54; CHECK-NEXT: addv.4s s2, v355; CHECK-NEXT: bfi x12, x16, #2, #156; CHECK-NEXT: and x16, x16, #0x157; CHECK-NEXT: and x8, x8, #0x158; CHECK-NEXT: add x8, x16, x859; CHECK-NEXT: and x11, x11, #0x160; CHECK-NEXT: and x13, x13, #0x161; CHECK-NEXT: fmov w16, s262; CHECK-NEXT: add x11, x8, x1163; CHECK-NEXT: orr x8, x9, x8, lsl #264; CHECK-NEXT: add x13, x11, x1365; CHECK-NEXT: bfi x14, x11, #2, #266; CHECK-NEXT: cmp x13, #367; CHECK-NEXT: bfi x10, x16, #2, #268; CHECK-NEXT: mov.s w16, v0[3]69; CHECK-NEXT: csel x11, x13, x15, lo70; CHECK-NEXT: ldr w10, [x10]71; CHECK-NEXT: str s0, [sp]72; CHECK-NEXT: st1.s { v0 }[1], [x12]73; CHECK-NEXT: st1.s { v0 }[2], [x8]74; CHECK-NEXT: orr x8, x9, x11, lsl #275; CHECK-NEXT: csel w9, w16, w10, hi76; CHECK-NEXT: st1.s { v0 }[3], [x14]77; CHECK-NEXT: str w9, [x8]78; CHECK-NEXT: ldr q0, [sp], #1679; CHECK-NEXT: ret80 %out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> %mask, <4 x i32> %passthru)81 ret <4 x i32> %out82}83 84define <2 x double> @test_compress_v2f64(<2 x double> %vec, <2 x i1> %mask) {85; CHECK-LABEL: test_compress_v2f64:86; CHECK: ; %bb.0:87; CHECK-NEXT: sub sp, sp, #1688; CHECK-NEXT: .cfi_def_cfa_offset 1689; CHECK-NEXT: ushll.2d v1, v1, #090; CHECK-NEXT: mov x8, sp91; CHECK-NEXT: str d0, [sp]92; CHECK-NEXT: shl.2d v1, v1, #6393; CHECK-NEXT: cmlt.2d v1, v1, #094; CHECK-NEXT: fmov x9, d195; CHECK-NEXT: and x9, x9, #0x896; CHECK-NEXT: orr x8, x8, x997; CHECK-NEXT: st1.d { v0 }[1], [x8]98; CHECK-NEXT: ldr q0, [sp], #1699; CHECK-NEXT: ret100 %out = call <2 x double> @llvm.experimental.vector.compress.v2f64(<2 x double> %vec, <2 x i1> %mask, <2 x double> undef)101 ret <2 x double> %out102}103 104define <16 x i8> @test_compress_v16i8(<16 x i8> %vec, <16 x i1> %mask) {105; CHECK-LABEL: test_compress_v16i8:106; CHECK: ; %bb.0:107; CHECK-NEXT: sub sp, sp, #16108; CHECK-NEXT: .cfi_def_cfa_offset 16109; CHECK-NEXT: shl.16b v1, v1, #7110; CHECK-NEXT: mov x12, sp111; CHECK-NEXT: mov x8, sp112; CHECK-NEXT: str b0, [sp]113; CHECK-NEXT: mov x13, sp114; CHECK-NEXT: cmlt.16b v1, v1, #0115; CHECK-NEXT: umov.b w9, v1[0]116; CHECK-NEXT: umov.b w10, v1[1]117; CHECK-NEXT: umov.b w11, v1[2]118; CHECK-NEXT: umov.b w14, v1[3]119; CHECK-NEXT: bfxil x12, x9, #0, #1120; CHECK-NEXT: and x10, x10, #0x1121; CHECK-NEXT: and x9, x9, #0x1122; CHECK-NEXT: add x9, x9, x10123; CHECK-NEXT: umov.b w10, v1[4]124; CHECK-NEXT: and x11, x11, #0x1125; CHECK-NEXT: st1.b { v0 }[1], [x12]126; CHECK-NEXT: orr x12, x8, x9127; CHECK-NEXT: add x9, x9, x11128; CHECK-NEXT: umov.b w11, v1[5]129; CHECK-NEXT: and x14, x14, #0x1130; CHECK-NEXT: st1.b { v0 }[2], [x12]131; CHECK-NEXT: add x14, x9, x14132; CHECK-NEXT: umov.b w12, v1[6]133; CHECK-NEXT: orr x9, x8, x9134; CHECK-NEXT: and x10, x10, #0x1135; CHECK-NEXT: st1.b { v0 }[3], [x9]136; CHECK-NEXT: orr x9, x8, x14137; CHECK-NEXT: add x10, x14, x10138; CHECK-NEXT: umov.b w14, v1[7]139; CHECK-NEXT: st1.b { v0 }[4], [x9]140; CHECK-NEXT: and x11, x11, #0x1141; CHECK-NEXT: bfxil x13, x10, #0, #4142; CHECK-NEXT: mov x9, sp143; CHECK-NEXT: add x10, x10, x11144; CHECK-NEXT: umov.b w11, v1[8]145; CHECK-NEXT: and x12, x12, #0x1146; CHECK-NEXT: bfxil x9, x10, #0, #4147; CHECK-NEXT: st1.b { v0 }[5], [x13]148; CHECK-NEXT: umov.b w13, v1[9]149; CHECK-NEXT: add x10, x10, x12150; CHECK-NEXT: mov x12, sp151; CHECK-NEXT: and x14, x14, #0x1152; CHECK-NEXT: st1.b { v0 }[6], [x9]153; CHECK-NEXT: umov.b w9, v1[10]154; CHECK-NEXT: bfxil x12, x10, #0, #4155; CHECK-NEXT: add x10, x10, x14156; CHECK-NEXT: mov x14, sp157; CHECK-NEXT: and x11, x11, #0x1158; CHECK-NEXT: bfxil x14, x10, #0, #4159; CHECK-NEXT: add x10, x10, x11160; CHECK-NEXT: mov x11, sp161; CHECK-NEXT: and x13, x13, #0x1162; CHECK-NEXT: st1.b { v0 }[7], [x12]163; CHECK-NEXT: mov x12, sp164; CHECK-NEXT: bfxil x11, x10, #0, #4165; CHECK-NEXT: add x10, x10, x13166; CHECK-NEXT: umov.b w13, v1[11]167; CHECK-NEXT: st1.b { v0 }[8], [x14]168; CHECK-NEXT: umov.b w14, v1[12]169; CHECK-NEXT: and x9, x9, #0x1170; CHECK-NEXT: bfxil x12, x10, #0, #4171; CHECK-NEXT: add x9, x10, x9172; CHECK-NEXT: mov x10, sp173; CHECK-NEXT: st1.b { v0 }[9], [x11]174; CHECK-NEXT: umov.b w11, v1[13]175; CHECK-NEXT: bfxil x10, x9, #0, #4176; CHECK-NEXT: st1.b { v0 }[10], [x12]177; CHECK-NEXT: umov.b w12, v1[14]178; CHECK-NEXT: and x13, x13, #0x1179; CHECK-NEXT: and x14, x14, #0x1180; CHECK-NEXT: add x9, x9, x13181; CHECK-NEXT: st1.b { v0 }[11], [x10]182; CHECK-NEXT: mov x10, sp183; CHECK-NEXT: add x13, x9, x14184; CHECK-NEXT: mov x14, sp185; CHECK-NEXT: bfxil x10, x9, #0, #4186; CHECK-NEXT: and x9, x11, #0x1187; CHECK-NEXT: mov x11, sp188; CHECK-NEXT: add x9, x13, x9189; CHECK-NEXT: and w12, w12, #0x1190; CHECK-NEXT: bfxil x14, x13, #0, #4191; CHECK-NEXT: bfxil x11, x9, #0, #4192; CHECK-NEXT: add w9, w9, w12193; CHECK-NEXT: st1.b { v0 }[12], [x10]194; CHECK-NEXT: bfxil x8, x9, #0, #4195; CHECK-NEXT: st1.b { v0 }[13], [x14]196; CHECK-NEXT: st1.b { v0 }[14], [x11]197; CHECK-NEXT: st1.b { v0 }[15], [x8]198; CHECK-NEXT: ldr q0, [sp], #16199; CHECK-NEXT: ret200 %out = call <16 x i8> @llvm.experimental.vector.compress(<16 x i8> %vec, <16 x i1> %mask, <16 x i8> undef)201 ret <16 x i8> %out202}203 204define <8 x i32> @test_compress_large(<8 x i32> %vec, <8 x i1> %mask) {205; CHECK-LABEL: test_compress_large:206; CHECK: ; %bb.0:207; CHECK-NEXT: sub sp, sp, #32208; CHECK-NEXT: .cfi_def_cfa_offset 32209; CHECK-NEXT: ; kill: def $d2 killed $d2 def $q2210; CHECK-NEXT: umov.b w9, v2[0]211; CHECK-NEXT: umov.b w10, v2[1]212; CHECK-NEXT: mov x11, sp213; CHECK-NEXT: umov.b w12, v2[2]214; CHECK-NEXT: umov.b w13, v2[3]215; CHECK-NEXT: mov x8, sp216; CHECK-NEXT: umov.b w15, v2[4]217; CHECK-NEXT: str s0, [sp]218; CHECK-NEXT: mov s3, v0[3]219; CHECK-NEXT: and x10, x10, #0x1220; CHECK-NEXT: and x14, x9, #0x1221; CHECK-NEXT: bfi x11, x9, #2, #1222; CHECK-NEXT: add x9, x14, x10223; CHECK-NEXT: umov.b w10, v2[5]224; CHECK-NEXT: st1.s { v0 }[1], [x11]225; CHECK-NEXT: and x11, x12, #0x1226; CHECK-NEXT: orr x14, x8, x9, lsl #2227; CHECK-NEXT: and x12, x13, #0x1228; CHECK-NEXT: add x9, x9, x11229; CHECK-NEXT: umov.b w11, v2[6]230; CHECK-NEXT: and x13, x15, #0x1231; CHECK-NEXT: add x12, x9, x12232; CHECK-NEXT: st1.s { v0 }[2], [x14]233; CHECK-NEXT: str s3, [x8, x9, lsl #2]234; CHECK-NEXT: and x9, x10, #0x1235; CHECK-NEXT: add x10, x12, x13236; CHECK-NEXT: and x12, x12, #0x7237; CHECK-NEXT: add x9, x10, x9238; CHECK-NEXT: and x10, x10, #0x7239; CHECK-NEXT: str s1, [x8, x12, lsl #2]240; CHECK-NEXT: and x12, x9, #0x7241; CHECK-NEXT: mov s0, v1[3]242; CHECK-NEXT: and w11, w11, #0x1243; CHECK-NEXT: add x10, x8, x10, lsl #2244; CHECK-NEXT: add x12, x8, x12, lsl #2245; CHECK-NEXT: add w9, w9, w11246; CHECK-NEXT: and x9, x9, #0x7247; CHECK-NEXT: st1.s { v1 }[1], [x10]248; CHECK-NEXT: st1.s { v1 }[2], [x12]249; CHECK-NEXT: str s0, [x8, x9, lsl #2]250; CHECK-NEXT: ldp q0, q1, [sp], #32251; CHECK-NEXT: ret252 %out = call <8 x i32> @llvm.experimental.vector.compress(<8 x i32> %vec, <8 x i1> %mask, <8 x i32> undef)253 ret <8 x i32> %out254}255 256define <4 x i32> @test_compress_all_const() {257; CHECK-LABEL: test_compress_all_const:258; CHECK: ; %bb.0:259; CHECK-NEXT: Lloh0:260; CHECK-NEXT: adrp x8, lCPI5_0@PAGE261; CHECK-NEXT: Lloh1:262; CHECK-NEXT: ldr q0, [x8, lCPI5_0@PAGEOFF]263; CHECK-NEXT: ret264; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1265 %out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> <i32 3, i32 5, i32 7, i32 9>,266 <4 x i1> <i1 0, i1 1, i1 0, i1 1>,267 <4 x i32> undef)268 ret <4 x i32> %out269}270 271define <4 x i32> @test_compress_const_mask(<4 x i32> %vec) {272; CHECK-LABEL: test_compress_const_mask:273; CHECK: ; %bb.0:274; CHECK-NEXT: mov.s v0[1], v0[3]275; CHECK-NEXT: ret276 %out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> <i1 1, i1 undef, i1 0, i1 1>, <4 x i32> undef)277 ret <4 x i32> %out278}279 280define <4 x i32> @test_compress_const_mask_passthrough(<4 x i32> %vec, <4 x i32> %passthru) {281; CHECK-LABEL: test_compress_const_mask_passthrough:282; CHECK: ; %bb.0:283; CHECK-NEXT: mov.d v1[0], v0[1]284; CHECK-NEXT: mov.s v1[0], v0[0]285; CHECK-NEXT: mov.16b v0, v1286; CHECK-NEXT: ret287 %out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> <i1 1, i1 undef, i1 0, i1 1>, <4 x i32> %passthru)288 ret <4 x i32> %out289}290 291define <4 x i32> @test_compress_const_mask_const_passthrough(<4 x i32> %vec) {292; CHECK-LABEL: test_compress_const_mask_const_passthrough:293; CHECK: ; %bb.0:294; CHECK-NEXT: mov.s v0[1], v0[3]295; CHECK-NEXT: mov w8, #7 ; =0x7296; CHECK-NEXT: mov.s v0[2], w8297; CHECK-NEXT: mov w8, #8 ; =0x8298; CHECK-NEXT: mov.s v0[3], w8299; CHECK-NEXT: ret300 %out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>)301 ret <4 x i32> %out302}303 304; We pass a placeholder value for the const_mask* tests to check that they are converted to a no-op by simply copying305; the second vector input register to the return register or doing nothing.306define <4 x i32> @test_compress_const_splat1_mask(<4 x i32> %ignore, <4 x i32> %vec) {307; CHECK-LABEL: test_compress_const_splat1_mask:308; CHECK: ; %bb.0:309; CHECK-NEXT: mov.16b v0, v1310; CHECK-NEXT: ret311 %out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> splat (i1 -1), <4 x i32> undef)312 ret <4 x i32> %out313}314define <4 x i32> @test_compress_const_splat0_mask(<4 x i32> %ignore, <4 x i32> %vec) {315; CHECK-LABEL: test_compress_const_splat0_mask:316; CHECK: ; %bb.0:317; CHECK-NEXT: ret318 %out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> splat (i1 0), <4 x i32> undef)319 ret <4 x i32> %out320}321define <4 x i32> @test_compress_undef_mask(<4 x i32> %ignore, <4 x i32> %vec) {322; CHECK-LABEL: test_compress_undef_mask:323; CHECK: ; %bb.0:324; CHECK-NEXT: ret325 %out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> undef, <4 x i32> undef)326 ret <4 x i32> %out327}328define <4 x i32> @test_compress_const_splat0_mask_with_passthru(<4 x i32> %ignore, <4 x i32> %vec, <4 x i32> %passthru) {329; CHECK-LABEL: test_compress_const_splat0_mask_with_passthru:330; CHECK: ; %bb.0:331; CHECK-NEXT: mov.16b v0, v2332; CHECK-NEXT: ret333 %out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> splat (i1 0), <4 x i32> %passthru)334 ret <4 x i32> %out335}336define <4 x i32> @test_compress_const_splat0_mask_without_passthru(<4 x i32> %ignore, <4 x i32> %vec) {337; CHECK-LABEL: test_compress_const_splat0_mask_without_passthru:338; CHECK: ; %bb.0:339; CHECK-NEXT: ret340 %out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %vec, <4 x i1> splat (i1 0), <4 x i32> undef)341 ret <4 x i32> %out342}343 344define <4 x i8> @test_compress_small(<4 x i8> %vec, <4 x i1> %mask) {345; CHECK-LABEL: test_compress_small:346; CHECK: ; %bb.0:347; CHECK-NEXT: sub sp, sp, #16348; CHECK-NEXT: .cfi_def_cfa_offset 16349; CHECK-NEXT: shl.4h v1, v1, #15350; CHECK-NEXT: add x8, sp, #8351; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0352; CHECK-NEXT: str h0, [sp, #8]353; CHECK-NEXT: cmlt.4h v1, v1, #0354; CHECK-NEXT: umov.h w9, v1[0]355; CHECK-NEXT: umov.h w10, v1[1]356; CHECK-NEXT: umov.h w11, v1[2]357; CHECK-NEXT: bfi x8, x9, #1, #1358; CHECK-NEXT: and x10, x10, #0x1359; CHECK-NEXT: and x9, x9, #0x1360; CHECK-NEXT: add x9, x9, x10361; CHECK-NEXT: and w11, w11, #0x1362; CHECK-NEXT: add x10, sp, #8363; CHECK-NEXT: add w11, w9, w11364; CHECK-NEXT: orr x9, x10, x9, lsl #1365; CHECK-NEXT: st1.h { v0 }[1], [x8]366; CHECK-NEXT: bfi x10, x11, #1, #2367; CHECK-NEXT: st1.h { v0 }[2], [x9]368; CHECK-NEXT: st1.h { v0 }[3], [x10]369; CHECK-NEXT: ldr d0, [sp, #8]370; CHECK-NEXT: add sp, sp, #16371; CHECK-NEXT: ret372 %out = call <4 x i8> @llvm.experimental.vector.compress(<4 x i8> %vec, <4 x i1> %mask, <4 x i8> undef)373 ret <4 x i8> %out374}375 376define <4 x i4> @test_compress_illegal_element_type(<4 x i4> %vec, <4 x i1> %mask) {377; CHECK-LABEL: test_compress_illegal_element_type:378; CHECK: ; %bb.0:379; CHECK-NEXT: sub sp, sp, #16380; CHECK-NEXT: .cfi_def_cfa_offset 16381; CHECK-NEXT: shl.4h v1, v1, #15382; CHECK-NEXT: add x8, sp, #8383; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0384; CHECK-NEXT: str h0, [sp, #8]385; CHECK-NEXT: cmlt.4h v1, v1, #0386; CHECK-NEXT: umov.h w9, v1[0]387; CHECK-NEXT: umov.h w10, v1[1]388; CHECK-NEXT: umov.h w11, v1[2]389; CHECK-NEXT: bfi x8, x9, #1, #1390; CHECK-NEXT: and x10, x10, #0x1391; CHECK-NEXT: and x9, x9, #0x1392; CHECK-NEXT: add x9, x9, x10393; CHECK-NEXT: and w11, w11, #0x1394; CHECK-NEXT: add x10, sp, #8395; CHECK-NEXT: add w11, w9, w11396; CHECK-NEXT: orr x9, x10, x9, lsl #1397; CHECK-NEXT: st1.h { v0 }[1], [x8]398; CHECK-NEXT: bfi x10, x11, #1, #2399; CHECK-NEXT: st1.h { v0 }[2], [x9]400; CHECK-NEXT: st1.h { v0 }[3], [x10]401; CHECK-NEXT: ldr d0, [sp, #8]402; CHECK-NEXT: add sp, sp, #16403; CHECK-NEXT: ret404 %out = call <4 x i4> @llvm.experimental.vector.compress(<4 x i4> %vec, <4 x i1> %mask, <4 x i4> undef)405 ret <4 x i4> %out406}407 408define <3 x i32> @test_compress_narrow(<3 x i32> %vec, <3 x i1> %mask) {409; CHECK-LABEL: test_compress_narrow:410; CHECK: ; %bb.0:411; CHECK-NEXT: sub sp, sp, #16412; CHECK-NEXT: .cfi_def_cfa_offset 16413; CHECK-NEXT: movi.2d v1, #0000000000000000414; CHECK-NEXT: mov x11, sp415; CHECK-NEXT: str s0, [sp]416; CHECK-NEXT: mov.h v1[0], w0417; CHECK-NEXT: mov.h v1[1], w1418; CHECK-NEXT: mov.h v1[2], w2419; CHECK-NEXT: ushll.4s v1, v1, #0420; CHECK-NEXT: shl.4s v1, v1, #31421; CHECK-NEXT: cmlt.4s v1, v1, #0422; CHECK-NEXT: mov.s w8, v1[1]423; CHECK-NEXT: fmov w10, s1424; CHECK-NEXT: mov.s w9, v1[2]425; CHECK-NEXT: and x12, x10, #0x1426; CHECK-NEXT: bfi x11, x10, #2, #1427; CHECK-NEXT: mov x10, sp428; CHECK-NEXT: and x8, x8, #0x1429; CHECK-NEXT: add x8, x12, x8430; CHECK-NEXT: st1.s { v0 }[1], [x11]431; CHECK-NEXT: sub w9, w8, w9432; CHECK-NEXT: orr x8, x10, x8, lsl #2433; CHECK-NEXT: bfi x10, x9, #2, #2434; CHECK-NEXT: st1.s { v0 }[2], [x8]435; CHECK-NEXT: st1.s { v0 }[3], [x10]436; CHECK-NEXT: ldr q0, [sp], #16437; CHECK-NEXT: ret438 %out = call <3 x i32> @llvm.experimental.vector.compress(<3 x i32> %vec, <3 x i1> %mask, <3 x i32> undef)439 ret <3 x i32> %out440}441 442define <3 x i3> @test_compress_narrow_illegal_element_type(<3 x i3> %vec, <3 x i1> %mask) {443; CHECK-LABEL: test_compress_narrow_illegal_element_type:444; CHECK: ; %bb.0:445; CHECK-NEXT: sub sp, sp, #16446; CHECK-NEXT: .cfi_def_cfa_offset 16447; CHECK-NEXT: movi.2d v0, #0000000000000000448; CHECK-NEXT: add x10, sp, #8449; CHECK-NEXT: strh w0, [sp, #8]450; CHECK-NEXT: mov.h v0[0], w3451; CHECK-NEXT: mov.h v0[1], w4452; CHECK-NEXT: mov.h v0[2], w5453; CHECK-NEXT: shl.4h v0, v0, #15454; CHECK-NEXT: cmlt.4h v0, v0, #0455; CHECK-NEXT: umov.h w8, v0[0]456; CHECK-NEXT: umov.h w9, v0[1]457; CHECK-NEXT: and x9, x9, #0x1458; CHECK-NEXT: and x11, x8, #0x1459; CHECK-NEXT: bfi x10, x8, #1, #1460; CHECK-NEXT: add x8, x11, x9461; CHECK-NEXT: add x9, sp, #8462; CHECK-NEXT: orr x8, x9, x8, lsl #1463; CHECK-NEXT: strh w1, [x10]464; CHECK-NEXT: strh w2, [x8]465; CHECK-NEXT: ldrh w0, [sp, #8]466; CHECK-NEXT: ldrh w1, [sp, #10]467; CHECK-NEXT: ldrh w2, [sp, #12]468; CHECK-NEXT: add sp, sp, #16469; CHECK-NEXT: ret470 %out = call <3 x i3> @llvm.experimental.vector.compress(<3 x i3> %vec, <3 x i1> %mask, <3 x i3> undef)471 ret <3 x i3> %out472}473 474define <4 x i32> @test_compress_knownbits_zext_v4i16_4i32(<4 x i16> %vec, <4 x i1> %mask, <4 x i32> %passthru) nounwind {475; CHECK-LABEL: test_compress_knownbits_zext_v4i16_4i32:476; CHECK: ; %bb.0: ; %entry477; CHECK-NEXT: sub sp, sp, #16478; CHECK-NEXT: ushll.4s v1, v1, #0479; CHECK-NEXT: movi.4s v3, #1480; CHECK-NEXT: mov x14, sp481; CHECK-NEXT: movi.4s v4, #3482; CHECK-NEXT: ushll.4s v0, v0, #0483; CHECK-NEXT: mov x13, sp484; CHECK-NEXT: mov x12, sp485; CHECK-NEXT: mov x15, sp486; CHECK-NEXT: shl.4s v1, v1, #31487; CHECK-NEXT: and.16b v2, v2, v4488; CHECK-NEXT: cmlt.4s v1, v1, #0489; CHECK-NEXT: str q2, [sp]490; CHECK-NEXT: and.16b v3, v1, v3491; CHECK-NEXT: mov.s w8, v1[1]492; CHECK-NEXT: mov.s w9, v1[2]493; CHECK-NEXT: mov.s w10, v1[3]494; CHECK-NEXT: fmov w11, s1495; CHECK-NEXT: addv.4s s1, v3496; CHECK-NEXT: and x16, x11, #0x1497; CHECK-NEXT: and x8, x8, #0x1498; CHECK-NEXT: bfi x14, x11, #2, #1499; CHECK-NEXT: add x8, x16, x8500; CHECK-NEXT: and x9, x9, #0x1501; CHECK-NEXT: and x10, x10, #0x1502; CHECK-NEXT: fmov w11, s1503; CHECK-NEXT: add x9, x8, x9504; CHECK-NEXT: mov w16, #3 ; =0x3505; CHECK-NEXT: add x10, x9, x10506; CHECK-NEXT: orr x8, x12, x8, lsl #2507; CHECK-NEXT: bfi x15, x9, #2, #2508; CHECK-NEXT: cmp x10, #3509; CHECK-NEXT: bfi x13, x11, #2, #2510; CHECK-NEXT: mov.s w11, v0[3]511; CHECK-NEXT: csel x9, x10, x16, lo512; CHECK-NEXT: ldr w13, [x13]513; CHECK-NEXT: str s0, [sp]514; CHECK-NEXT: st1.s { v0 }[1], [x14]515; CHECK-NEXT: st1.s { v0 }[2], [x8]516; CHECK-NEXT: orr x8, x12, x9, lsl #2517; CHECK-NEXT: csel w9, w11, w13, hi518; CHECK-NEXT: st1.s { v0 }[3], [x15]519; CHECK-NEXT: str w9, [x8]520; CHECK-NEXT: ldr q0, [sp], #16521; CHECK-NEXT: ret522entry:523 %xvec = zext <4 x i16> %vec to <4 x i32>524 %xpassthru = and <4 x i32> %passthru, splat (i32 3)525 %out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %xvec, <4 x i1> %mask, <4 x i32> %xpassthru)526 %res = and <4 x i32> %out, splat (i32 65535)527 ret <4 x i32> %res528}529 530define <4 x i32> @test_compress_numsignbits_sext_v4i16_4i32(<4 x i16> %vec, <4 x i1> %mask, <4 x i32> %passthru) nounwind {531; CHECK-LABEL: test_compress_numsignbits_sext_v4i16_4i32:532; CHECK: ; %bb.0: ; %entry533; CHECK-NEXT: sub sp, sp, #16534; CHECK-NEXT: ushll.4s v1, v1, #0535; CHECK-NEXT: movi.4s v3, #1536; CHECK-NEXT: mov x14, sp537; CHECK-NEXT: movi.4s v4, #3538; CHECK-NEXT: sshll.4s v0, v0, #0539; CHECK-NEXT: mov x13, sp540; CHECK-NEXT: mov x12, sp541; CHECK-NEXT: mov x15, sp542; CHECK-NEXT: shl.4s v1, v1, #31543; CHECK-NEXT: and.16b v2, v2, v4544; CHECK-NEXT: cmlt.4s v1, v1, #0545; CHECK-NEXT: str q2, [sp]546; CHECK-NEXT: and.16b v3, v1, v3547; CHECK-NEXT: mov.s w8, v1[1]548; CHECK-NEXT: mov.s w9, v1[2]549; CHECK-NEXT: mov.s w10, v1[3]550; CHECK-NEXT: fmov w11, s1551; CHECK-NEXT: addv.4s s1, v3552; CHECK-NEXT: and x16, x11, #0x1553; CHECK-NEXT: and x8, x8, #0x1554; CHECK-NEXT: bfi x14, x11, #2, #1555; CHECK-NEXT: add x8, x16, x8556; CHECK-NEXT: and x9, x9, #0x1557; CHECK-NEXT: and x10, x10, #0x1558; CHECK-NEXT: fmov w11, s1559; CHECK-NEXT: add x9, x8, x9560; CHECK-NEXT: mov w16, #3 ; =0x3561; CHECK-NEXT: add x10, x9, x10562; CHECK-NEXT: orr x8, x12, x8, lsl #2563; CHECK-NEXT: bfi x15, x9, #2, #2564; CHECK-NEXT: cmp x10, #3565; CHECK-NEXT: bfi x13, x11, #2, #2566; CHECK-NEXT: mov.s w11, v0[3]567; CHECK-NEXT: csel x9, x10, x16, lo568; CHECK-NEXT: ldr w13, [x13]569; CHECK-NEXT: str s0, [sp]570; CHECK-NEXT: st1.s { v0 }[1], [x14]571; CHECK-NEXT: st1.s { v0 }[2], [x8]572; CHECK-NEXT: orr x8, x12, x9, lsl #2573; CHECK-NEXT: csel w9, w11, w13, hi574; CHECK-NEXT: st1.s { v0 }[3], [x15]575; CHECK-NEXT: str w9, [x8]576; CHECK-NEXT: ldr q0, [sp], #16577; CHECK-NEXT: ret578entry:579 %xvec = sext <4 x i16> %vec to <4 x i32>580 %xpassthru = and <4 x i32> %passthru, splat(i32 3)581 %out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> %xvec, <4 x i1> %mask, <4 x i32> %xpassthru)582 %shl = shl <4 x i32> %out, splat(i32 16)583 %res = ashr <4 x i32> %shl, splat(i32 16)584 ret <4 x i32> %res585}586