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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple aarch64-apple-darwin | FileCheck --check-prefixes=CHECK,NOFP16 %s3; RUN: llc < %s -mtriple aarch64-apple-darwin -mattr=+v8.2a,+fullfp16 | FileCheck --check-prefixes=CHECK,FP16 %s4 5target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"6 7;============ v1f328 9; WidenVecRes same10define <1 x float> @test_copysign_v1f32_v1f32(<1 x float> %a, <1 x float> %b) #0 {11; CHECK-LABEL: test_copysign_v1f32_v1f32:12; CHECK: ; %bb.0:13; CHECK-NEXT: mvni.2s v2, #128, lsl #2414; CHECK-NEXT: bif.8b v0, v1, v215; CHECK-NEXT: ret16 %r = call <1 x float> @llvm.copysign.v1f32(<1 x float> %a, <1 x float> %b)17 ret <1 x float> %r18}19 20; WidenVecRes mismatched21define <1 x float> @test_copysign_v1f32_v1f64(<1 x float> %a, <1 x double> %b) #0 {22; CHECK-LABEL: test_copysign_v1f32_v1f64:23; CHECK: ; %bb.0:24; CHECK-NEXT: ; kill: def $d1 killed $d1 def $q125; CHECK-NEXT: mvni.2s v2, #128, lsl #2426; CHECK-NEXT: fcvtn v1.2s, v1.2d27; CHECK-NEXT: bif.8b v0, v1, v228; CHECK-NEXT: ret29 %tmp0 = fptrunc <1 x double> %b to <1 x float>30 %r = call <1 x float> @llvm.copysign.v1f32(<1 x float> %a, <1 x float> %tmp0)31 ret <1 x float> %r32}33 34declare <1 x float> @llvm.copysign.v1f32(<1 x float> %a, <1 x float> %b) #035 36;============ v1f6437 38; WidenVecOp #139define <1 x double> @test_copysign_v1f64_v1f32(<1 x double> %a, <1 x float> %b) #0 {40; CHECK-LABEL: test_copysign_v1f64_v1f32:41; CHECK: ; %bb.0:42; CHECK-NEXT: movi.2d v2, #0xffffffffffffffff43; CHECK-NEXT: fcvtl v1.2d, v1.2s44; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q045; CHECK-NEXT: fneg.2d v2, v246; CHECK-NEXT: bif.16b v0, v1, v247; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q048; CHECK-NEXT: ret49 %tmp0 = fpext <1 x float> %b to <1 x double>50 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %tmp0)51 ret <1 x double> %r52}53 54define <1 x double> @test_copysign_v1f64_v1f64(<1 x double> %a, <1 x double> %b) #0 {55; CHECK-LABEL: test_copysign_v1f64_v1f64:56; CHECK: ; %bb.0:57; CHECK-NEXT: movi.2d v2, #0xffffffffffffffff58; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q059; CHECK-NEXT: ; kill: def $d1 killed $d1 def $q160; CHECK-NEXT: fneg.2d v2, v261; CHECK-NEXT: bif.16b v0, v1, v262; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q063; CHECK-NEXT: ret64 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b)65 ret <1 x double> %r66}67 68declare <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b) #069 70;============ v2f3271 72define <2 x float> @test_copysign_v2f32_v2f32(<2 x float> %a, <2 x float> %b) #0 {73; CHECK-LABEL: test_copysign_v2f32_v2f32:74; CHECK: ; %bb.0:75; CHECK-NEXT: mvni.2s v2, #128, lsl #2476; CHECK-NEXT: bif.8b v0, v1, v277; CHECK-NEXT: ret78 %r = call <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b)79 ret <2 x float> %r80}81 82define <2 x float> @test_copysign_v2f32_v2f64(<2 x float> %a, <2 x double> %b) #0 {83; CHECK-LABEL: test_copysign_v2f32_v2f64:84; CHECK: ; %bb.0:85; CHECK-NEXT: fcvtn v1.2s, v1.2d86; CHECK-NEXT: mvni.2s v2, #128, lsl #2487; CHECK-NEXT: bif.8b v0, v1, v288; CHECK-NEXT: ret89 %tmp0 = fptrunc <2 x double> %b to <2 x float>90 %r = call <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %tmp0)91 ret <2 x float> %r92}93 94declare <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b) #095 96;============ v4f3297 98define <4 x float> @test_copysign_v4f32_v4f32(<4 x float> %a, <4 x float> %b) #0 {99; CHECK-LABEL: test_copysign_v4f32_v4f32:100; CHECK: ; %bb.0:101; CHECK-NEXT: mvni.4s v2, #128, lsl #24102; CHECK-NEXT: bif.16b v0, v1, v2103; CHECK-NEXT: ret104 %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b)105 ret <4 x float> %r106}107 108; SplitVecOp #1109define <4 x float> @test_copysign_v4f32_v4f64(<4 x float> %a, <4 x double> %b) #0 {110; CHECK-LABEL: test_copysign_v4f32_v4f64:111; CHECK: ; %bb.0:112; CHECK-NEXT: fcvtn v1.2s, v1.2d113; CHECK-NEXT: fcvtn2 v1.4s, v2.2d114; CHECK-NEXT: mvni.4s v2, #128, lsl #24115; CHECK-NEXT: bif.16b v0, v1, v2116; CHECK-NEXT: ret117 %tmp0 = fptrunc <4 x double> %b to <4 x float>118 %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %tmp0)119 ret <4 x float> %r120}121 122declare <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b) #0123 124;============ v2f64125 126define <2 x double> @test_copysign_v2f64_v232(<2 x double> %a, <2 x float> %b) #0 {127; CHECK-LABEL: test_copysign_v2f64_v232:128; CHECK: ; %bb.0:129; CHECK-NEXT: movi.2d v2, #0xffffffffffffffff130; CHECK-NEXT: fcvtl v1.2d, v1.2s131; CHECK-NEXT: fneg.2d v2, v2132; CHECK-NEXT: bif.16b v0, v1, v2133; CHECK-NEXT: ret134 %tmp0 = fpext <2 x float> %b to <2 x double>135 %r = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %tmp0)136 ret <2 x double> %r137}138 139define <2 x double> @test_copysign_v2f64_v2f64(<2 x double> %a, <2 x double> %b) #0 {140; CHECK-LABEL: test_copysign_v2f64_v2f64:141; CHECK: ; %bb.0:142; CHECK-NEXT: movi.2d v2, #0xffffffffffffffff143; CHECK-NEXT: fneg.2d v2, v2144; CHECK-NEXT: bif.16b v0, v1, v2145; CHECK-NEXT: ret146 %r = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b)147 ret <2 x double> %r148}149 150declare <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b) #0151 152;============ v4f64153 154; SplitVecRes mismatched155define <4 x double> @test_copysign_v4f64_v4f32(<4 x double> %a, <4 x float> %b) #0 {156; CHECK-LABEL: test_copysign_v4f64_v4f32:157; CHECK: ; %bb.0:158; CHECK-NEXT: movi.2d v3, #0xffffffffffffffff159; CHECK-NEXT: fcvtl v4.2d, v2.2s160; CHECK-NEXT: fcvtl2 v2.2d, v2.4s161; CHECK-NEXT: fneg.2d v3, v3162; CHECK-NEXT: bif.16b v1, v2, v3163; CHECK-NEXT: bif.16b v0, v4, v3164; CHECK-NEXT: ret165 %tmp0 = fpext <4 x float> %b to <4 x double>166 %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %tmp0)167 ret <4 x double> %r168}169 170; SplitVecRes same171define <4 x double> @test_copysign_v4f64_v4f64(<4 x double> %a, <4 x double> %b) #0 {172; CHECK-LABEL: test_copysign_v4f64_v4f64:173; CHECK: ; %bb.0:174; CHECK-NEXT: movi.2d v4, #0xffffffffffffffff175; CHECK-NEXT: fneg.2d v4, v4176; CHECK-NEXT: bif.16b v0, v2, v4177; CHECK-NEXT: bif.16b v1, v3, v4178; CHECK-NEXT: ret179 %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b)180 ret <4 x double> %r181}182 183declare <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b) #0184 185;============ v4f16186 187define <4 x half> @test_copysign_v4f16_v4f16(<4 x half> %a, <4 x half> %b) #0 {188; CHECK-LABEL: test_copysign_v4f16_v4f16:189; CHECK: ; %bb.0:190; CHECK-NEXT: mvni.4h v2, #128, lsl #8191; CHECK-NEXT: bif.8b v0, v1, v2192; CHECK-NEXT: ret193 %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b)194 ret <4 x half> %r195}196 197define <4 x half> @test_copysign_v4f16_v4f32(<4 x half> %a, <4 x float> %b) #0 {198; CHECK-LABEL: test_copysign_v4f16_v4f32:199; CHECK: ; %bb.0:200; CHECK-NEXT: fcvtn v1.4h, v1.4s201; CHECK-NEXT: mvni.4h v2, #128, lsl #8202; CHECK-NEXT: bif.8b v0, v1, v2203; CHECK-NEXT: ret204 %tmp0 = fptrunc <4 x float> %b to <4 x half>205 %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %tmp0)206 ret <4 x half> %r207}208 209define <4 x half> @test_copysign_v4f16_v4f64(<4 x half> %a, <4 x double> %b) #0 {210; CHECK-LABEL: test_copysign_v4f16_v4f64:211; CHECK: ; %bb.0:212; CHECK-NEXT: fcvtxn v1.2s, v1.2d213; CHECK-NEXT: fcvtxn2 v1.4s, v2.2d214; CHECK-NEXT: mvni.4h v2, #128, lsl #8215; CHECK-NEXT: fcvtn v1.4h, v1.4s216; CHECK-NEXT: bif.8b v0, v1, v2217; CHECK-NEXT: ret218 %tmp0 = fptrunc <4 x double> %b to <4 x half>219 %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %tmp0)220 ret <4 x half> %r221}222 223declare <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b) #0224 225;============ v8f16226 227define <8 x half> @test_copysign_v8f16_v8f16(<8 x half> %a, <8 x half> %b) #0 {228; CHECK-LABEL: test_copysign_v8f16_v8f16:229; CHECK: ; %bb.0:230; CHECK-NEXT: mvni.8h v2, #128, lsl #8231; CHECK-NEXT: bif.16b v0, v1, v2232; CHECK-NEXT: ret233 %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b)234 ret <8 x half> %r235}236 237define <8 x half> @test_copysign_v8f16_v8f32(<8 x half> %a, <8 x float> %b) #0 {238; CHECK-LABEL: test_copysign_v8f16_v8f32:239; CHECK: ; %bb.0:240; CHECK-NEXT: fcvtn v1.4h, v1.4s241; CHECK-NEXT: fcvtn2 v1.8h, v2.4s242; CHECK-NEXT: mvni.8h v2, #128, lsl #8243; CHECK-NEXT: bif.16b v0, v1, v2244; CHECK-NEXT: ret245 %tmp0 = fptrunc <8 x float> %b to <8 x half>246 %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %tmp0)247 ret <8 x half> %r248}249 250declare <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b) #0251 252;============ v4bf16253 254define <4 x bfloat> @test_copysign_v4bf16_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {255; CHECK-LABEL: test_copysign_v4bf16_v4bf16:256; CHECK: ; %bb.0:257; CHECK-NEXT: mvni.4h v2, #128, lsl #8258; CHECK-NEXT: bif.8b v0, v1, v2259; CHECK-NEXT: ret260 %r = call <4 x bfloat> @llvm.copysign.v4bf16(<4 x bfloat> %a, <4 x bfloat> %b)261 ret <4 x bfloat> %r262}263 264define <4 x bfloat> @test_copysign_v4bf16_v4f32(<4 x bfloat> %a, <4 x float> %b) #0 {265; CHECK-LABEL: test_copysign_v4bf16_v4f32:266; CHECK: ; %bb.0:267; CHECK-NEXT: movi.4s v2, #1268; CHECK-NEXT: movi.4s v3, #127, msl #8269; CHECK-NEXT: ushr.4s v4, v1, #16270; CHECK-NEXT: and.16b v2, v4, v2271; CHECK-NEXT: add.4s v3, v1, v3272; CHECK-NEXT: fcmeq.4s v4, v1, v1273; CHECK-NEXT: orr.4s v1, #64, lsl #16274; CHECK-NEXT: add.4s v2, v2, v3275; CHECK-NEXT: bit.16b v1, v2, v4276; CHECK-NEXT: mvni.4h v2, #128, lsl #8277; CHECK-NEXT: shrn.4h v1, v1, #16278; CHECK-NEXT: bif.8b v0, v1, v2279; CHECK-NEXT: ret280 %tmp0 = fptrunc <4 x float> %b to <4 x bfloat>281 %r = call <4 x bfloat> @llvm.copysign.v4bf16(<4 x bfloat> %a, <4 x bfloat> %tmp0)282 ret <4 x bfloat> %r283}284 285define <4 x bfloat> @test_copysign_v4bf16_v4f64(<4 x bfloat> %a, <4 x double> %b) #0 {286; CHECK-LABEL: test_copysign_v4bf16_v4f64:287; CHECK: ; %bb.0:288; CHECK-NEXT: fcvtxn v1.2s, v1.2d289; CHECK-NEXT: movi.4s v3, #127, msl #8290; CHECK-NEXT: fcvtxn2 v1.4s, v2.2d291; CHECK-NEXT: movi.4s v2, #1292; CHECK-NEXT: ushr.4s v4, v1, #16293; CHECK-NEXT: add.4s v3, v1, v3294; CHECK-NEXT: and.16b v2, v4, v2295; CHECK-NEXT: fcmeq.4s v4, v1, v1296; CHECK-NEXT: orr.4s v1, #64, lsl #16297; CHECK-NEXT: add.4s v2, v2, v3298; CHECK-NEXT: bit.16b v1, v2, v4299; CHECK-NEXT: mvni.4h v2, #128, lsl #8300; CHECK-NEXT: shrn.4h v1, v1, #16301; CHECK-NEXT: bif.8b v0, v1, v2302; CHECK-NEXT: ret303 %tmp0 = fptrunc <4 x double> %b to <4 x bfloat>304 %r = call <4 x bfloat> @llvm.copysign.v4bf16(<4 x bfloat> %a, <4 x bfloat> %tmp0)305 ret <4 x bfloat> %r306}307 308declare <4 x bfloat> @llvm.copysign.v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0309 310;============ v8bf16311 312define <8 x bfloat> @test_copysign_v8bf16_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {313; CHECK-LABEL: test_copysign_v8bf16_v8bf16:314; CHECK: ; %bb.0:315; CHECK-NEXT: mvni.8h v2, #128, lsl #8316; CHECK-NEXT: bif.16b v0, v1, v2317; CHECK-NEXT: ret318 %r = call <8 x bfloat> @llvm.copysign.v8bf16(<8 x bfloat> %a, <8 x bfloat> %b)319 ret <8 x bfloat> %r320}321 322define <8 x bfloat> @test_copysign_v8bf16_v8f32(<8 x bfloat> %a, <8 x float> %b) #0 {323; CHECK-LABEL: test_copysign_v8bf16_v8f32:324; CHECK: ; %bb.0:325; CHECK-NEXT: movi.4s v3, #1326; CHECK-NEXT: movi.4s v4, #127, msl #8327; CHECK-NEXT: ushr.4s v5, v2, #16328; CHECK-NEXT: ushr.4s v6, v1, #16329; CHECK-NEXT: and.16b v5, v5, v3330; CHECK-NEXT: add.4s v7, v2, v4331; CHECK-NEXT: and.16b v3, v6, v3332; CHECK-NEXT: add.4s v4, v1, v4333; CHECK-NEXT: fcmeq.4s v6, v2, v2334; CHECK-NEXT: orr.4s v2, #64, lsl #16335; CHECK-NEXT: add.4s v5, v5, v7336; CHECK-NEXT: fcmeq.4s v7, v1, v1337; CHECK-NEXT: orr.4s v1, #64, lsl #16338; CHECK-NEXT: add.4s v3, v3, v4339; CHECK-NEXT: bit.16b v2, v5, v6340; CHECK-NEXT: bit.16b v1, v3, v7341; CHECK-NEXT: uzp2.8h v1, v1, v2342; CHECK-NEXT: mvni.8h v2, #128, lsl #8343; CHECK-NEXT: bif.16b v0, v1, v2344; CHECK-NEXT: ret345 %tmp0 = fptrunc <8 x float> %b to <8 x bfloat>346 %r = call <8 x bfloat> @llvm.copysign.v8bf16(<8 x bfloat> %a, <8 x bfloat> %tmp0)347 ret <8 x bfloat> %r348}349 350declare <8 x bfloat> @llvm.copysign.v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0351 352attributes #0 = { nounwind }353;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:354; FP16: {{.*}}355; NOFP16: {{.*}}356