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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s3 4define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) nounwind {5; CHECK-LABEL: llrint_v1i64_v1f16:6; CHECK: // %bb.0:7; CHECK-NEXT: fcvt s0, h08; CHECK-NEXT: frintx s0, s09; CHECK-NEXT: fcvtzs x8, s010; CHECK-NEXT: fmov d0, x811; CHECK-NEXT: ret12 %a = call <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half> %x)13 ret <1 x i64> %a14}15declare <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half>)16 17define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) nounwind {18; CHECK-LABEL: llrint_v1i64_v2f16:19; CHECK: // %bb.0:20; CHECK-NEXT: // kill: def $d0 killed $d0 def $q021; CHECK-NEXT: mov h1, v0.h[1]22; CHECK-NEXT: fcvt s0, h023; CHECK-NEXT: fcvt s1, h124; CHECK-NEXT: frintx s0, s025; CHECK-NEXT: frintx s1, s126; CHECK-NEXT: fcvtzs x8, s027; CHECK-NEXT: fcvtzs x9, s128; CHECK-NEXT: fmov d0, x829; CHECK-NEXT: mov v0.d[1], x930; CHECK-NEXT: ret31 %a = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> %x)32 ret <2 x i64> %a33}34declare <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half>)35 36define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) nounwind {37; CHECK-LABEL: llrint_v4i64_v4f16:38; CHECK: // %bb.0:39; CHECK-NEXT: // kill: def $d0 killed $d0 def $q040; CHECK-NEXT: mov h1, v0.h[2]41; CHECK-NEXT: mov h2, v0.h[1]42; CHECK-NEXT: mov h3, v0.h[3]43; CHECK-NEXT: fcvt s0, h044; CHECK-NEXT: fcvt s1, h145; CHECK-NEXT: fcvt s2, h246; CHECK-NEXT: fcvt s3, h347; CHECK-NEXT: frintx s0, s048; CHECK-NEXT: frintx s1, s149; CHECK-NEXT: frintx s2, s250; CHECK-NEXT: frintx s3, s351; CHECK-NEXT: fcvtzs x8, s052; CHECK-NEXT: fcvtzs x9, s153; CHECK-NEXT: fcvtzs x10, s254; CHECK-NEXT: fcvtzs x11, s355; CHECK-NEXT: fmov d0, x856; CHECK-NEXT: fmov d1, x957; CHECK-NEXT: mov v0.d[1], x1058; CHECK-NEXT: mov v1.d[1], x1159; CHECK-NEXT: ret60 %a = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> %x)61 ret <4 x i64> %a62}63declare <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half>)64 65define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) nounwind {66; CHECK-LABEL: llrint_v8i64_v8f16:67; CHECK: // %bb.0:68; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #869; CHECK-NEXT: mov h4, v0.h[2]70; CHECK-NEXT: mov h3, v0.h[1]71; CHECK-NEXT: mov h7, v0.h[3]72; CHECK-NEXT: fcvt s0, h073; CHECK-NEXT: mov h2, v1.h[2]74; CHECK-NEXT: mov h5, v1.h[1]75; CHECK-NEXT: mov h6, v1.h[3]76; CHECK-NEXT: fcvt s1, h177; CHECK-NEXT: fcvt s4, h478; CHECK-NEXT: fcvt s3, h379; CHECK-NEXT: fcvt s7, h780; CHECK-NEXT: frintx s0, s081; CHECK-NEXT: fcvt s2, h282; CHECK-NEXT: fcvt s5, h583; CHECK-NEXT: fcvt s6, h684; CHECK-NEXT: frintx s1, s185; CHECK-NEXT: frintx s4, s486; CHECK-NEXT: frintx s3, s387; CHECK-NEXT: frintx s7, s788; CHECK-NEXT: fcvtzs x9, s089; CHECK-NEXT: frintx s2, s290; CHECK-NEXT: frintx s5, s591; CHECK-NEXT: frintx s6, s692; CHECK-NEXT: fcvtzs x8, s193; CHECK-NEXT: fcvtzs x12, s494; CHECK-NEXT: fcvtzs x11, s395; CHECK-NEXT: fcvtzs x15, s796; CHECK-NEXT: fmov d0, x997; CHECK-NEXT: fcvtzs x10, s298; CHECK-NEXT: fcvtzs x13, s599; CHECK-NEXT: fcvtzs x14, s6100; CHECK-NEXT: fmov d2, x8101; CHECK-NEXT: fmov d1, x12102; CHECK-NEXT: mov v0.d[1], x11103; CHECK-NEXT: fmov d3, x10104; CHECK-NEXT: mov v2.d[1], x13105; CHECK-NEXT: mov v1.d[1], x15106; CHECK-NEXT: mov v3.d[1], x14107; CHECK-NEXT: ret108 %a = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> %x)109 ret <8 x i64> %a110}111declare <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half>)112 113define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) nounwind {114; CHECK-LABEL: llrint_v16i64_v16f16:115; CHECK: // %bb.0:116; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8117; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8118; CHECK-NEXT: mov h17, v0.h[1]119; CHECK-NEXT: mov h19, v0.h[2]120; CHECK-NEXT: fcvt s18, h0121; CHECK-NEXT: mov h0, v0.h[3]122; CHECK-NEXT: mov h4, v2.h[1]123; CHECK-NEXT: mov h5, v2.h[2]124; CHECK-NEXT: fcvt s7, h3125; CHECK-NEXT: fcvt s6, h2126; CHECK-NEXT: mov h16, v3.h[2]127; CHECK-NEXT: mov h2, v2.h[3]128; CHECK-NEXT: fcvt s17, h17129; CHECK-NEXT: fcvt s19, h19130; CHECK-NEXT: frintx s18, s18131; CHECK-NEXT: fcvt s0, h0132; CHECK-NEXT: fcvt s4, h4133; CHECK-NEXT: fcvt s5, h5134; CHECK-NEXT: frintx s7, s7135; CHECK-NEXT: frintx s6, s6136; CHECK-NEXT: fcvt s16, h16137; CHECK-NEXT: fcvt s2, h2138; CHECK-NEXT: frintx s17, s17139; CHECK-NEXT: frintx s19, s19140; CHECK-NEXT: fcvtzs x13, s18141; CHECK-NEXT: frintx s0, s0142; CHECK-NEXT: frintx s4, s4143; CHECK-NEXT: frintx s5, s5144; CHECK-NEXT: fcvtzs x9, s7145; CHECK-NEXT: mov h7, v1.h[2]146; CHECK-NEXT: fcvtzs x8, s6147; CHECK-NEXT: mov h6, v1.h[1]148; CHECK-NEXT: frintx s16, s16149; CHECK-NEXT: fcvtzs x14, s17150; CHECK-NEXT: fcvtzs x15, s19151; CHECK-NEXT: fcvtzs x10, s4152; CHECK-NEXT: mov h4, v3.h[1]153; CHECK-NEXT: fcvtzs x11, s5154; CHECK-NEXT: mov h5, v1.h[3]155; CHECK-NEXT: mov h3, v3.h[3]156; CHECK-NEXT: fcvt s1, h1157; CHECK-NEXT: fcvt s7, h7158; CHECK-NEXT: fcvt s6, h6159; CHECK-NEXT: fcvtzs x12, s16160; CHECK-NEXT: frintx s16, s2161; CHECK-NEXT: fmov d2, x8162; CHECK-NEXT: fcvt s4, h4163; CHECK-NEXT: fcvt s3, h3164; CHECK-NEXT: fcvt s5, h5165; CHECK-NEXT: frintx s1, s1166; CHECK-NEXT: frintx s7, s7167; CHECK-NEXT: frintx s17, s6168; CHECK-NEXT: fmov d6, x9169; CHECK-NEXT: mov v2.d[1], x10170; CHECK-NEXT: frintx s4, s4171; CHECK-NEXT: frintx s18, s3172; CHECK-NEXT: frintx s5, s5173; CHECK-NEXT: fcvtzs x8, s1174; CHECK-NEXT: fcvtzs x9, s7175; CHECK-NEXT: fmov d3, x11176; CHECK-NEXT: fcvtzs x11, s0177; CHECK-NEXT: fmov d7, x12178; CHECK-NEXT: fcvtzs x12, s16179; CHECK-NEXT: fcvtzs x16, s17180; CHECK-NEXT: fcvtzs x17, s4181; CHECK-NEXT: fmov d0, x13182; CHECK-NEXT: fmov d1, x15183; CHECK-NEXT: fcvtzs x18, s18184; CHECK-NEXT: fcvtzs x0, s5185; CHECK-NEXT: fmov d4, x8186; CHECK-NEXT: fmov d5, x9187; CHECK-NEXT: mov v0.d[1], x14188; CHECK-NEXT: mov v1.d[1], x11189; CHECK-NEXT: mov v3.d[1], x12190; CHECK-NEXT: mov v4.d[1], x16191; CHECK-NEXT: mov v6.d[1], x17192; CHECK-NEXT: mov v7.d[1], x18193; CHECK-NEXT: mov v5.d[1], x0194; CHECK-NEXT: ret195 %a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x)196 ret <16 x i64> %a197}198declare <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half>)199 200define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) nounwind {201; CHECK-LABEL: llrint_v32i64_v32f16:202; CHECK: // %bb.0:203; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8204; CHECK-NEXT: ext v5.16b, v2.16b, v2.16b, #8205; CHECK-NEXT: ext v6.16b, v3.16b, v3.16b, #8206; CHECK-NEXT: ext v7.16b, v0.16b, v0.16b, #8207; CHECK-NEXT: mov h19, v0.h[1]208; CHECK-NEXT: fcvt s21, h0209; CHECK-NEXT: mov h23, v1.h[2]210; CHECK-NEXT: fcvt s22, h1211; CHECK-NEXT: fcvt s26, h2212; CHECK-NEXT: mov h27, v2.h[1]213; CHECK-NEXT: mov h28, v2.h[2]214; CHECK-NEXT: mov h16, v4.h[2]215; CHECK-NEXT: fcvt s17, h5216; CHECK-NEXT: mov h18, v5.h[2]217; CHECK-NEXT: mov h20, v6.h[2]218; CHECK-NEXT: fcvt s24, h7219; CHECK-NEXT: fcvt s25, h6220; CHECK-NEXT: fcvt s19, h19221; CHECK-NEXT: frintx s22, s22222; CHECK-NEXT: fcvt s16, h16223; CHECK-NEXT: frintx s17, s17224; CHECK-NEXT: fcvt s18, h18225; CHECK-NEXT: fcvt s20, h20226; CHECK-NEXT: frintx s16, s16227; CHECK-NEXT: fcvtzs x12, s17228; CHECK-NEXT: frintx s17, s18229; CHECK-NEXT: frintx s18, s21230; CHECK-NEXT: fcvt s21, h23231; CHECK-NEXT: frintx s23, s24232; CHECK-NEXT: frintx s24, s25233; CHECK-NEXT: frintx s25, s19234; CHECK-NEXT: mov h19, v7.h[1]235; CHECK-NEXT: fcvtzs x13, s16236; CHECK-NEXT: frintx s16, s20237; CHECK-NEXT: frintx s20, s26238; CHECK-NEXT: fcvtzs x9, s23239; CHECK-NEXT: mov h23, v3.h[2]240; CHECK-NEXT: fcvt s26, h27241; CHECK-NEXT: fcvtzs x15, s24242; CHECK-NEXT: fcvtzs x10, s25243; CHECK-NEXT: fcvt s24, h28244; CHECK-NEXT: mov h25, v3.h[3]245; CHECK-NEXT: fcvtzs x14, s17246; CHECK-NEXT: frintx s21, s21247; CHECK-NEXT: fmov d17, x12248; CHECK-NEXT: fcvtzs x12, s16249; CHECK-NEXT: fmov d16, x13250; CHECK-NEXT: fcvtzs x13, s22251; CHECK-NEXT: fcvt s22, h3252; CHECK-NEXT: mov h3, v3.h[1]253; CHECK-NEXT: mov h27, v0.h[2]254; CHECK-NEXT: mov h28, v2.h[3]255; CHECK-NEXT: fcvt s23, h23256; CHECK-NEXT: frintx s26, s26257; CHECK-NEXT: fcvtzs x16, s20258; CHECK-NEXT: frintx s20, s24259; CHECK-NEXT: fcvt s24, h25260; CHECK-NEXT: fcvtzs x11, s18261; CHECK-NEXT: fmov d18, x14262; CHECK-NEXT: fcvtzs x14, s21263; CHECK-NEXT: frintx s22, s22264; CHECK-NEXT: fcvt s3, h3265; CHECK-NEXT: fcvt s25, h27266; CHECK-NEXT: fcvt s27, h28267; CHECK-NEXT: frintx s23, s23268; CHECK-NEXT: mov h21, v1.h[3]269; CHECK-NEXT: fmov d2, x15270; CHECK-NEXT: fcvtzs x15, s26271; CHECK-NEXT: fmov d26, x13272; CHECK-NEXT: mov h1, v1.h[1]273; CHECK-NEXT: fcvtzs x13, s20274; CHECK-NEXT: frintx s20, s24275; CHECK-NEXT: fmov d24, x14276; CHECK-NEXT: fcvtzs x14, s22277; CHECK-NEXT: frintx s3, s3278; CHECK-NEXT: fmov d22, x16279; CHECK-NEXT: frintx s27, s27280; CHECK-NEXT: fcvtzs x16, s23281; CHECK-NEXT: fcvt s21, h21282; CHECK-NEXT: frintx s25, s25283; CHECK-NEXT: fcvt s1, h1284; CHECK-NEXT: mov h0, v0.h[3]285; CHECK-NEXT: mov h23, v7.h[2]286; CHECK-NEXT: mov v22.d[1], x15287; CHECK-NEXT: fcvtzs x15, s20288; CHECK-NEXT: fmov d20, x13289; CHECK-NEXT: fcvtzs x13, s3290; CHECK-NEXT: fmov d3, x14291; CHECK-NEXT: fcvtzs x14, s27292; CHECK-NEXT: fmov d27, x16293; CHECK-NEXT: frintx s21, s21294; CHECK-NEXT: mov h7, v7.h[3]295; CHECK-NEXT: frintx s1, s1296; CHECK-NEXT: fcvt s0, h0297; CHECK-NEXT: fcvt s23, h23298; CHECK-NEXT: fcvt s19, h19299; CHECK-NEXT: mov v27.d[1], x15300; CHECK-NEXT: fcvtzs x15, s25301; CHECK-NEXT: mov h25, v6.h[3]302; CHECK-NEXT: mov h6, v6.h[1]303; CHECK-NEXT: mov v3.d[1], x13304; CHECK-NEXT: fcvtzs x13, s21305; CHECK-NEXT: mov h21, v5.h[1]306; CHECK-NEXT: mov h5, v5.h[3]307; CHECK-NEXT: mov v20.d[1], x14308; CHECK-NEXT: fcvtzs x14, s1309; CHECK-NEXT: mov h1, v4.h[1]310; CHECK-NEXT: frintx s0, s0311; CHECK-NEXT: fcvt s25, h25312; CHECK-NEXT: fcvt s7, h7313; CHECK-NEXT: stp q3, q27, [x8, #192]314; CHECK-NEXT: fcvt s6, h6315; CHECK-NEXT: mov h3, v4.h[3]316; CHECK-NEXT: stp q22, q20, [x8, #128]317; CHECK-NEXT: fcvt s21, h21318; CHECK-NEXT: fcvt s5, h5319; CHECK-NEXT: mov v24.d[1], x13320; CHECK-NEXT: mov v26.d[1], x14321; CHECK-NEXT: fcvt s4, h4322; CHECK-NEXT: frintx s22, s25323; CHECK-NEXT: fmov d20, x12324; CHECK-NEXT: fcvt s1, h1325; CHECK-NEXT: frintx s6, s6326; CHECK-NEXT: fcvt s3, h3327; CHECK-NEXT: fcvtzs x12, s0328; CHECK-NEXT: frintx s5, s5329; CHECK-NEXT: frintx s21, s21330; CHECK-NEXT: fmov d0, x11331; CHECK-NEXT: stp q26, q24, [x8, #64]332; CHECK-NEXT: fmov d24, x15333; CHECK-NEXT: frintx s4, s4334; CHECK-NEXT: fcvtzs x11, s22335; CHECK-NEXT: frintx s22, s23336; CHECK-NEXT: frintx s1, s1337; CHECK-NEXT: fcvtzs x13, s6338; CHECK-NEXT: frintx s3, s3339; CHECK-NEXT: frintx s6, s7340; CHECK-NEXT: fcvtzs x14, s5341; CHECK-NEXT: mov v24.d[1], x12342; CHECK-NEXT: frintx s5, s19343; CHECK-NEXT: fcvtzs x12, s21344; CHECK-NEXT: mov v0.d[1], x10345; CHECK-NEXT: fcvtzs x10, s4346; CHECK-NEXT: mov v20.d[1], x11347; CHECK-NEXT: fcvtzs x11, s22348; CHECK-NEXT: mov v2.d[1], x13349; CHECK-NEXT: fcvtzs x15, s3350; CHECK-NEXT: fcvtzs x13, s1351; CHECK-NEXT: mov v18.d[1], x14352; CHECK-NEXT: fcvtzs x14, s6353; CHECK-NEXT: stp q0, q24, [x8]354; CHECK-NEXT: mov v17.d[1], x12355; CHECK-NEXT: fcvtzs x12, s5356; CHECK-NEXT: fmov d0, x10357; CHECK-NEXT: fmov d1, x11358; CHECK-NEXT: stp q2, q20, [x8, #224]359; CHECK-NEXT: fmov d2, x9360; CHECK-NEXT: mov v16.d[1], x15361; CHECK-NEXT: stp q17, q18, [x8, #160]362; CHECK-NEXT: mov v0.d[1], x13363; CHECK-NEXT: mov v1.d[1], x14364; CHECK-NEXT: mov v2.d[1], x12365; CHECK-NEXT: stp q0, q16, [x8, #96]366; CHECK-NEXT: stp q2, q1, [x8, #32]367; CHECK-NEXT: ret368 %a = call <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half> %x)369 ret <32 x i64> %a370}371declare <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half>)372 373define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) nounwind {374; CHECK-LABEL: llrint_v1i64_v1f32:375; CHECK: // %bb.0:376; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0377; CHECK-NEXT: frintx s0, s0378; CHECK-NEXT: fcvtzs x8, s0379; CHECK-NEXT: fmov d0, x8380; CHECK-NEXT: ret381 %a = call <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float> %x)382 ret <1 x i64> %a383}384declare <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float>)385 386define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) nounwind {387; CHECK-LABEL: llrint_v2i64_v2f32:388; CHECK: // %bb.0:389; CHECK-NEXT: frintx v0.2s, v0.2s390; CHECK-NEXT: fcvtl v0.2d, v0.2s391; CHECK-NEXT: fcvtzs v0.2d, v0.2d392; CHECK-NEXT: ret393 %a = call <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float> %x)394 ret <2 x i64> %a395}396declare <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float>)397 398define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) nounwind {399; CHECK-LABEL: llrint_v4i64_v4f32:400; CHECK: // %bb.0:401; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8402; CHECK-NEXT: frintx v0.2s, v0.2s403; CHECK-NEXT: frintx v1.2s, v1.2s404; CHECK-NEXT: fcvtl v0.2d, v0.2s405; CHECK-NEXT: fcvtl v1.2d, v1.2s406; CHECK-NEXT: fcvtzs v0.2d, v0.2d407; CHECK-NEXT: fcvtzs v1.2d, v1.2d408; CHECK-NEXT: ret409 %a = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> %x)410 ret <4 x i64> %a411}412declare <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float>)413 414define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) nounwind {415; CHECK-LABEL: llrint_v8i64_v8f32:416; CHECK: // %bb.0:417; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8418; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8419; CHECK-NEXT: frintx v0.2s, v0.2s420; CHECK-NEXT: frintx v1.2s, v1.2s421; CHECK-NEXT: frintx v2.2s, v2.2s422; CHECK-NEXT: frintx v3.2s, v3.2s423; CHECK-NEXT: fcvtl v0.2d, v0.2s424; CHECK-NEXT: fcvtl v1.2d, v1.2s425; CHECK-NEXT: fcvtl v4.2d, v2.2s426; CHECK-NEXT: fcvtl v3.2d, v3.2s427; CHECK-NEXT: fcvtzs v0.2d, v0.2d428; CHECK-NEXT: fcvtzs v2.2d, v1.2d429; CHECK-NEXT: fcvtzs v1.2d, v4.2d430; CHECK-NEXT: fcvtzs v3.2d, v3.2d431; CHECK-NEXT: ret432 %a = call <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float> %x)433 ret <8 x i64> %a434}435declare <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float>)436 437define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) nounwind {438; CHECK-LABEL: llrint_v16i64_v16f32:439; CHECK: // %bb.0:440; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8441; CHECK-NEXT: ext v5.16b, v0.16b, v0.16b, #8442; CHECK-NEXT: ext v6.16b, v2.16b, v2.16b, #8443; CHECK-NEXT: ext v7.16b, v3.16b, v3.16b, #8444; CHECK-NEXT: frintx v0.2s, v0.2s445; CHECK-NEXT: frintx v1.2s, v1.2s446; CHECK-NEXT: frintx v2.2s, v2.2s447; CHECK-NEXT: frintx v3.2s, v3.2s448; CHECK-NEXT: frintx v5.2s, v5.2s449; CHECK-NEXT: frintx v4.2s, v4.2s450; CHECK-NEXT: frintx v6.2s, v6.2s451; CHECK-NEXT: frintx v7.2s, v7.2s452; CHECK-NEXT: fcvtl v0.2d, v0.2s453; CHECK-NEXT: fcvtl v1.2d, v1.2s454; CHECK-NEXT: fcvtl v16.2d, v2.2s455; CHECK-NEXT: fcvtl v18.2d, v3.2s456; CHECK-NEXT: fcvtl v5.2d, v5.2s457; CHECK-NEXT: fcvtl v17.2d, v4.2s458; CHECK-NEXT: fcvtl v19.2d, v6.2s459; CHECK-NEXT: fcvtl v7.2d, v7.2s460; CHECK-NEXT: fcvtzs v0.2d, v0.2d461; CHECK-NEXT: fcvtzs v2.2d, v1.2d462; CHECK-NEXT: fcvtzs v4.2d, v16.2d463; CHECK-NEXT: fcvtzs v6.2d, v18.2d464; CHECK-NEXT: fcvtzs v1.2d, v5.2d465; CHECK-NEXT: fcvtzs v3.2d, v17.2d466; CHECK-NEXT: fcvtzs v5.2d, v19.2d467; CHECK-NEXT: fcvtzs v7.2d, v7.2d468; CHECK-NEXT: ret469 %a = call <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float> %x)470 ret <16 x i64> %a471}472declare <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float>)473 474define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) nounwind {475; CHECK-LABEL: llrint_v32i64_v32f32:476; CHECK: // %bb.0:477; CHECK-NEXT: ext v16.16b, v7.16b, v7.16b, #8478; CHECK-NEXT: ext v17.16b, v6.16b, v6.16b, #8479; CHECK-NEXT: frintx v7.2s, v7.2s480; CHECK-NEXT: frintx v6.2s, v6.2s481; CHECK-NEXT: ext v18.16b, v5.16b, v5.16b, #8482; CHECK-NEXT: ext v21.16b, v4.16b, v4.16b, #8483; CHECK-NEXT: ext v22.16b, v2.16b, v2.16b, #8484; CHECK-NEXT: frintx v5.2s, v5.2s485; CHECK-NEXT: ext v23.16b, v3.16b, v3.16b, #8486; CHECK-NEXT: frintx v4.2s, v4.2s487; CHECK-NEXT: ext v19.16b, v0.16b, v0.16b, #8488; CHECK-NEXT: ext v20.16b, v1.16b, v1.16b, #8489; CHECK-NEXT: frintx v16.2s, v16.2s490; CHECK-NEXT: frintx v17.2s, v17.2s491; CHECK-NEXT: fcvtl v7.2d, v7.2s492; CHECK-NEXT: fcvtl v6.2d, v6.2s493; CHECK-NEXT: frintx v18.2s, v18.2s494; CHECK-NEXT: frintx v21.2s, v21.2s495; CHECK-NEXT: frintx v2.2s, v2.2s496; CHECK-NEXT: frintx v3.2s, v3.2s497; CHECK-NEXT: fcvtl v5.2d, v5.2s498; CHECK-NEXT: frintx v23.2s, v23.2s499; CHECK-NEXT: fcvtl v4.2d, v4.2s500; CHECK-NEXT: frintx v1.2s, v1.2s501; CHECK-NEXT: fcvtl v16.2d, v16.2s502; CHECK-NEXT: fcvtl v17.2d, v17.2s503; CHECK-NEXT: fcvtzs v7.2d, v7.2d504; CHECK-NEXT: fcvtzs v6.2d, v6.2d505; CHECK-NEXT: fcvtl v18.2d, v18.2s506; CHECK-NEXT: fcvtl v21.2d, v21.2s507; CHECK-NEXT: frintx v20.2s, v20.2s508; CHECK-NEXT: fcvtl v3.2d, v3.2s509; CHECK-NEXT: fcvtzs v5.2d, v5.2d510; CHECK-NEXT: frintx v0.2s, v0.2s511; CHECK-NEXT: fcvtl v2.2d, v2.2s512; CHECK-NEXT: fcvtzs v4.2d, v4.2d513; CHECK-NEXT: fcvtzs v16.2d, v16.2d514; CHECK-NEXT: fcvtzs v17.2d, v17.2d515; CHECK-NEXT: fcvtl v1.2d, v1.2s516; CHECK-NEXT: fcvtzs v3.2d, v3.2d517; CHECK-NEXT: fcvtl v0.2d, v0.2s518; CHECK-NEXT: fcvtzs v2.2d, v2.2d519; CHECK-NEXT: stp q6, q17, [x8, #192]520; CHECK-NEXT: fcvtl v6.2d, v23.2s521; CHECK-NEXT: frintx v17.2s, v19.2s522; CHECK-NEXT: stp q7, q16, [x8, #224]523; CHECK-NEXT: frintx v7.2s, v22.2s524; CHECK-NEXT: fcvtzs v16.2d, v18.2d525; CHECK-NEXT: fcvtzs v18.2d, v21.2d526; CHECK-NEXT: fcvtzs v1.2d, v1.2d527; CHECK-NEXT: fcvtzs v0.2d, v0.2d528; CHECK-NEXT: fcvtzs v6.2d, v6.2d529; CHECK-NEXT: stp q5, q16, [x8, #160]530; CHECK-NEXT: fcvtl v7.2d, v7.2s531; CHECK-NEXT: fcvtl v5.2d, v20.2s532; CHECK-NEXT: stp q4, q18, [x8, #128]533; CHECK-NEXT: fcvtl v4.2d, v17.2s534; CHECK-NEXT: stp q3, q6, [x8, #96]535; CHECK-NEXT: fcvtzs v7.2d, v7.2d536; CHECK-NEXT: fcvtzs v3.2d, v5.2d537; CHECK-NEXT: stp q1, q3, [x8, #32]538; CHECK-NEXT: stp q2, q7, [x8, #64]539; CHECK-NEXT: fcvtzs v2.2d, v4.2d540; CHECK-NEXT: stp q0, q2, [x8]541; CHECK-NEXT: ret542 %a = call <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float> %x)543 ret <32 x i64> %a544}545declare <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float>)546 547define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) nounwind {548; CHECK-LABEL: llrint_v1i64_v1f64:549; CHECK: // %bb.0:550; CHECK-NEXT: frintx d0, d0551; CHECK-NEXT: fcvtzs x8, d0552; CHECK-NEXT: fmov d0, x8553; CHECK-NEXT: ret554 %a = call <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double> %x)555 ret <1 x i64> %a556}557declare <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double>)558 559define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) nounwind {560; CHECK-LABEL: llrint_v2i64_v2f64:561; CHECK: // %bb.0:562; CHECK-NEXT: frintx v0.2d, v0.2d563; CHECK-NEXT: fcvtzs v0.2d, v0.2d564; CHECK-NEXT: ret565 %a = call <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double> %x)566 ret <2 x i64> %a567}568declare <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double>)569 570define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) nounwind {571; CHECK-LABEL: llrint_v4i64_v4f64:572; CHECK: // %bb.0:573; CHECK-NEXT: frintx v0.2d, v0.2d574; CHECK-NEXT: frintx v1.2d, v1.2d575; CHECK-NEXT: fcvtzs v0.2d, v0.2d576; CHECK-NEXT: fcvtzs v1.2d, v1.2d577; CHECK-NEXT: ret578 %a = call <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double> %x)579 ret <4 x i64> %a580}581declare <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double>)582 583define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) nounwind {584; CHECK-LABEL: llrint_v8i64_v8f64:585; CHECK: // %bb.0:586; CHECK-NEXT: frintx v0.2d, v0.2d587; CHECK-NEXT: frintx v1.2d, v1.2d588; CHECK-NEXT: frintx v2.2d, v2.2d589; CHECK-NEXT: frintx v3.2d, v3.2d590; CHECK-NEXT: fcvtzs v0.2d, v0.2d591; CHECK-NEXT: fcvtzs v1.2d, v1.2d592; CHECK-NEXT: fcvtzs v2.2d, v2.2d593; CHECK-NEXT: fcvtzs v3.2d, v3.2d594; CHECK-NEXT: ret595 %a = call <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double> %x)596 ret <8 x i64> %a597}598declare <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double>)599 600define <16 x i64> @llrint_v16f64(<16 x double> %x) nounwind {601; CHECK-LABEL: llrint_v16f64:602; CHECK: // %bb.0:603; CHECK-NEXT: frintx v0.2d, v0.2d604; CHECK-NEXT: frintx v1.2d, v1.2d605; CHECK-NEXT: frintx v2.2d, v2.2d606; CHECK-NEXT: frintx v3.2d, v3.2d607; CHECK-NEXT: frintx v4.2d, v4.2d608; CHECK-NEXT: frintx v5.2d, v5.2d609; CHECK-NEXT: frintx v6.2d, v6.2d610; CHECK-NEXT: frintx v7.2d, v7.2d611; CHECK-NEXT: fcvtzs v0.2d, v0.2d612; CHECK-NEXT: fcvtzs v1.2d, v1.2d613; CHECK-NEXT: fcvtzs v2.2d, v2.2d614; CHECK-NEXT: fcvtzs v3.2d, v3.2d615; CHECK-NEXT: fcvtzs v4.2d, v4.2d616; CHECK-NEXT: fcvtzs v5.2d, v5.2d617; CHECK-NEXT: fcvtzs v6.2d, v6.2d618; CHECK-NEXT: fcvtzs v7.2d, v7.2d619; CHECK-NEXT: ret620 %a = call <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double> %x)621 ret <16 x i64> %a622}623declare <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double>)624 625define <32 x i64> @llrint_v32f64(<32 x double> %x) nounwind {626; CHECK-LABEL: llrint_v32f64:627; CHECK: // %bb.0:628; CHECK-NEXT: ldp q17, q16, [sp, #96]629; CHECK-NEXT: frintx v7.2d, v7.2d630; CHECK-NEXT: ldp q19, q18, [sp, #64]631; CHECK-NEXT: frintx v6.2d, v6.2d632; CHECK-NEXT: ldp q21, q20, [sp, #32]633; CHECK-NEXT: frintx v5.2d, v5.2d634; CHECK-NEXT: frintx v16.2d, v16.2d635; CHECK-NEXT: frintx v17.2d, v17.2d636; CHECK-NEXT: frintx v4.2d, v4.2d637; CHECK-NEXT: frintx v18.2d, v18.2d638; CHECK-NEXT: frintx v19.2d, v19.2d639; CHECK-NEXT: frintx v3.2d, v3.2d640; CHECK-NEXT: ldp q23, q22, [sp]641; CHECK-NEXT: frintx v20.2d, v20.2d642; CHECK-NEXT: frintx v21.2d, v21.2d643; CHECK-NEXT: frintx v2.2d, v2.2d644; CHECK-NEXT: frintx v1.2d, v1.2d645; CHECK-NEXT: fcvtzs v16.2d, v16.2d646; CHECK-NEXT: fcvtzs v17.2d, v17.2d647; CHECK-NEXT: frintx v0.2d, v0.2d648; CHECK-NEXT: frintx v22.2d, v22.2d649; CHECK-NEXT: fcvtzs v18.2d, v18.2d650; CHECK-NEXT: frintx v23.2d, v23.2d651; CHECK-NEXT: fcvtzs v19.2d, v19.2d652; CHECK-NEXT: fcvtzs v20.2d, v20.2d653; CHECK-NEXT: fcvtzs v7.2d, v7.2d654; CHECK-NEXT: fcvtzs v6.2d, v6.2d655; CHECK-NEXT: fcvtzs v5.2d, v5.2d656; CHECK-NEXT: fcvtzs v4.2d, v4.2d657; CHECK-NEXT: stp q17, q16, [x8, #224]658; CHECK-NEXT: fcvtzs v16.2d, v21.2d659; CHECK-NEXT: fcvtzs v3.2d, v3.2d660; CHECK-NEXT: fcvtzs v17.2d, v22.2d661; CHECK-NEXT: fcvtzs v2.2d, v2.2d662; CHECK-NEXT: fcvtzs v1.2d, v1.2d663; CHECK-NEXT: stp q19, q18, [x8, #192]664; CHECK-NEXT: fcvtzs v18.2d, v23.2d665; CHECK-NEXT: fcvtzs v0.2d, v0.2d666; CHECK-NEXT: stp q4, q5, [x8, #64]667; CHECK-NEXT: stp q6, q7, [x8, #96]668; CHECK-NEXT: stp q2, q3, [x8, #32]669; CHECK-NEXT: stp q0, q1, [x8]670; CHECK-NEXT: stp q18, q17, [x8, #128]671; CHECK-NEXT: stp q16, q20, [x8, #160]672; CHECK-NEXT: ret673 %a = call <32 x i64> @llvm.llrint.v32i64.v16f64(<32 x double> %x)674 ret <32 x i64> %a675}676declare <32 x i64> @llvm.llrint.v32i64.v32f64(<32 x double>)677 678define <1 x i64> @llrint_v1i64_v1f128(<1 x fp128> %x) nounwind {679; CHECK-LABEL: llrint_v1i64_v1f128:680; CHECK: // %bb.0:681; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill682; CHECK-NEXT: bl llrintl683; CHECK-NEXT: fmov d0, x0684; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload685; CHECK-NEXT: ret686 %a = call <1 x i64> @llvm.llrint.v1i64.v1f128(<1 x fp128> %x)687 ret <1 x i64> %a688}689declare <1 x i64> @llvm.llrint.v1i64.v1f128(<1 x fp128>)690 691define <2 x i64> @llrint_v2i64_v2f128(<2 x fp128> %x) nounwind {692; CHECK-LABEL: llrint_v2i64_v2f128:693; CHECK: // %bb.0:694; CHECK-NEXT: sub sp, sp, #48695; CHECK-NEXT: str q0, [sp] // 16-byte Spill696; CHECK-NEXT: mov v0.16b, v1.16b697; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill698; CHECK-NEXT: bl llrintl699; CHECK-NEXT: fmov d0, x0700; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill701; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload702; CHECK-NEXT: bl llrintl703; CHECK-NEXT: fmov d0, x0704; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload705; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload706; CHECK-NEXT: mov v0.d[1], v1.d[0]707; CHECK-NEXT: add sp, sp, #48708; CHECK-NEXT: ret709 %a = call <2 x i64> @llvm.llrint.v2i64.v2f128(<2 x fp128> %x)710 ret <2 x i64> %a711}712declare <2 x i64> @llvm.llrint.v2i64.v2f128(<2 x fp128>)713 714define <4 x i64> @llrint_v4i64_v4f128(<4 x fp128> %x) nounwind {715; CHECK-LABEL: llrint_v4i64_v4f128:716; CHECK: // %bb.0:717; CHECK-NEXT: sub sp, sp, #80718; CHECK-NEXT: str q0, [sp] // 16-byte Spill719; CHECK-NEXT: mov v0.16b, v1.16b720; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill721; CHECK-NEXT: stp q3, q2, [sp, #32] // 32-byte Folded Spill722; CHECK-NEXT: bl llrintl723; CHECK-NEXT: fmov d0, x0724; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill725; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload726; CHECK-NEXT: bl llrintl727; CHECK-NEXT: fmov d0, x0728; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload729; CHECK-NEXT: mov v0.d[1], v1.d[0]730; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill731; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Reload732; CHECK-NEXT: bl llrintl733; CHECK-NEXT: fmov d0, x0734; CHECK-NEXT: str q0, [sp, #32] // 16-byte Spill735; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Reload736; CHECK-NEXT: bl llrintl737; CHECK-NEXT: fmov d1, x0738; CHECK-NEXT: ldp q0, q4, [sp, #16] // 32-byte Folded Reload739; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload740; CHECK-NEXT: mov v1.d[1], v4.d[0]741; CHECK-NEXT: add sp, sp, #80742; CHECK-NEXT: ret743 %a = call <4 x i64> @llvm.llrint.v4i64.v4f128(<4 x fp128> %x)744 ret <4 x i64> %a745}746declare <4 x i64> @llvm.llrint.v4i64.v4f128(<4 x fp128>)747 748define <8 x i64> @llrint_v8i64_v8f128(<8 x fp128> %x) nounwind {749; CHECK-LABEL: llrint_v8i64_v8f128:750; CHECK: // %bb.0:751; CHECK-NEXT: sub sp, sp, #144752; CHECK-NEXT: str q0, [sp] // 16-byte Spill753; CHECK-NEXT: mov v0.16b, v1.16b754; CHECK-NEXT: str x30, [sp, #128] // 8-byte Spill755; CHECK-NEXT: stp q3, q2, [sp, #16] // 32-byte Folded Spill756; CHECK-NEXT: stp q5, q4, [sp, #48] // 32-byte Folded Spill757; CHECK-NEXT: stp q7, q6, [sp, #96] // 32-byte Folded Spill758; CHECK-NEXT: bl llrintl759; CHECK-NEXT: fmov d0, x0760; CHECK-NEXT: str q0, [sp, #80] // 16-byte Spill761; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload762; CHECK-NEXT: bl llrintl763; CHECK-NEXT: fmov d0, x0764; CHECK-NEXT: ldr q1, [sp, #80] // 16-byte Reload765; CHECK-NEXT: mov v0.d[1], v1.d[0]766; CHECK-NEXT: str q0, [sp, #80] // 16-byte Spill767; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload768; CHECK-NEXT: bl llrintl769; CHECK-NEXT: fmov d0, x0770; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill771; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Reload772; CHECK-NEXT: bl llrintl773; CHECK-NEXT: fmov d0, x0774; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload775; CHECK-NEXT: mov v0.d[1], v1.d[0]776; CHECK-NEXT: str q0, [sp, #32] // 16-byte Spill777; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Reload778; CHECK-NEXT: bl llrintl779; CHECK-NEXT: fmov d0, x0780; CHECK-NEXT: str q0, [sp, #48] // 16-byte Spill781; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Reload782; CHECK-NEXT: bl llrintl783; CHECK-NEXT: fmov d0, x0784; CHECK-NEXT: ldr q1, [sp, #48] // 16-byte Reload785; CHECK-NEXT: mov v0.d[1], v1.d[0]786; CHECK-NEXT: str q0, [sp, #64] // 16-byte Spill787; CHECK-NEXT: ldr q0, [sp, #96] // 16-byte Reload788; CHECK-NEXT: bl llrintl789; CHECK-NEXT: fmov d0, x0790; CHECK-NEXT: str q0, [sp, #96] // 16-byte Spill791; CHECK-NEXT: ldr q0, [sp, #112] // 16-byte Reload792; CHECK-NEXT: bl llrintl793; CHECK-NEXT: fmov d3, x0794; CHECK-NEXT: ldp q0, q1, [sp, #80] // 32-byte Folded Reload795; CHECK-NEXT: ldr q2, [sp, #64] // 16-byte Reload796; CHECK-NEXT: ldr x30, [sp, #128] // 8-byte Reload797; CHECK-NEXT: mov v3.d[1], v1.d[0]798; CHECK-NEXT: ldr q1, [sp, #32] // 16-byte Reload799; CHECK-NEXT: add sp, sp, #144800; CHECK-NEXT: ret801 %a = call <8 x i64> @llvm.llrint.v8i64.v8f128(<8 x fp128> %x)802 ret <8 x i64> %a803}804declare <8 x i64> @llvm.llrint.v8i64.v8f128(<8 x fp128>)805 806define <16 x i64> @llrint_v16f128(<16 x fp128> %x) nounwind {807; CHECK-LABEL: llrint_v16f128:808; CHECK: // %bb.0:809; CHECK-NEXT: sub sp, sp, #272810; CHECK-NEXT: str q2, [sp, #160] // 16-byte Spill811; CHECK-NEXT: ldr q2, [sp, #368]812; CHECK-NEXT: stp q0, q3, [sp] // 32-byte Folded Spill813; CHECK-NEXT: mov v0.16b, v1.16b814; CHECK-NEXT: str q2, [sp, #240] // 16-byte Spill815; CHECK-NEXT: ldr q2, [sp, #384]816; CHECK-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill817; CHECK-NEXT: str q2, [sp, #224] // 16-byte Spill818; CHECK-NEXT: ldr q2, [sp, #336]819; CHECK-NEXT: stp q5, q7, [sp, #32] // 32-byte Folded Spill820; CHECK-NEXT: str q2, [sp, #192] // 16-byte Spill821; CHECK-NEXT: ldr q2, [sp, #352]822; CHECK-NEXT: str q2, [sp, #176] // 16-byte Spill823; CHECK-NEXT: ldr q2, [sp, #304]824; CHECK-NEXT: str q2, [sp, #144] // 16-byte Spill825; CHECK-NEXT: ldr q2, [sp, #320]826; CHECK-NEXT: stp q4, q2, [sp, #112] // 32-byte Folded Spill827; CHECK-NEXT: ldr q2, [sp, #272]828; CHECK-NEXT: stp q6, q2, [sp, #80] // 32-byte Folded Spill829; CHECK-NEXT: ldr q2, [sp, #288]830; CHECK-NEXT: str q2, [sp, #64] // 16-byte Spill831; CHECK-NEXT: bl llrintl832; CHECK-NEXT: fmov d0, x0833; CHECK-NEXT: str q0, [sp, #208] // 16-byte Spill834; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload835; CHECK-NEXT: bl llrintl836; CHECK-NEXT: fmov d0, x0837; CHECK-NEXT: ldr q1, [sp, #208] // 16-byte Reload838; CHECK-NEXT: mov v0.d[1], v1.d[0]839; CHECK-NEXT: str q0, [sp, #208] // 16-byte Spill840; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload841; CHECK-NEXT: bl llrintl842; CHECK-NEXT: fmov d0, x0843; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill844; CHECK-NEXT: ldr q0, [sp, #160] // 16-byte Reload845; CHECK-NEXT: bl llrintl846; CHECK-NEXT: fmov d0, x0847; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload848; CHECK-NEXT: mov v0.d[1], v1.d[0]849; CHECK-NEXT: str q0, [sp, #160] // 16-byte Spill850; CHECK-NEXT: ldr q0, [sp, #32] // 16-byte Reload851; CHECK-NEXT: bl llrintl852; CHECK-NEXT: fmov d0, x0853; CHECK-NEXT: str q0, [sp, #32] // 16-byte Spill854; CHECK-NEXT: ldr q0, [sp, #112] // 16-byte Reload855; CHECK-NEXT: bl llrintl856; CHECK-NEXT: fmov d0, x0857; CHECK-NEXT: ldr q1, [sp, #32] // 16-byte Reload858; CHECK-NEXT: mov v0.d[1], v1.d[0]859; CHECK-NEXT: str q0, [sp, #112] // 16-byte Spill860; CHECK-NEXT: ldr q0, [sp, #48] // 16-byte Reload861; CHECK-NEXT: bl llrintl862; CHECK-NEXT: fmov d0, x0863; CHECK-NEXT: str q0, [sp, #48] // 16-byte Spill864; CHECK-NEXT: ldr q0, [sp, #80] // 16-byte Reload865; CHECK-NEXT: bl llrintl866; CHECK-NEXT: fmov d0, x0867; CHECK-NEXT: ldr q1, [sp, #48] // 16-byte Reload868; CHECK-NEXT: mov v0.d[1], v1.d[0]869; CHECK-NEXT: str q0, [sp, #80] // 16-byte Spill870; CHECK-NEXT: ldr q0, [sp, #64] // 16-byte Reload871; CHECK-NEXT: bl llrintl872; CHECK-NEXT: fmov d0, x0873; CHECK-NEXT: str q0, [sp, #64] // 16-byte Spill874; CHECK-NEXT: ldr q0, [sp, #96] // 16-byte Reload875; CHECK-NEXT: bl llrintl876; CHECK-NEXT: fmov d0, x0877; CHECK-NEXT: ldr q1, [sp, #64] // 16-byte Reload878; CHECK-NEXT: mov v0.d[1], v1.d[0]879; CHECK-NEXT: str q0, [sp, #96] // 16-byte Spill880; CHECK-NEXT: ldr q0, [sp, #128] // 16-byte Reload881; CHECK-NEXT: bl llrintl882; CHECK-NEXT: fmov d0, x0883; CHECK-NEXT: str q0, [sp, #128] // 16-byte Spill884; CHECK-NEXT: ldr q0, [sp, #144] // 16-byte Reload885; CHECK-NEXT: bl llrintl886; CHECK-NEXT: fmov d0, x0887; CHECK-NEXT: ldr q1, [sp, #128] // 16-byte Reload888; CHECK-NEXT: mov v0.d[1], v1.d[0]889; CHECK-NEXT: str q0, [sp, #144] // 16-byte Spill890; CHECK-NEXT: ldr q0, [sp, #176] // 16-byte Reload891; CHECK-NEXT: bl llrintl892; CHECK-NEXT: fmov d0, x0893; CHECK-NEXT: str q0, [sp, #176] // 16-byte Spill894; CHECK-NEXT: ldr q0, [sp, #192] // 16-byte Reload895; CHECK-NEXT: bl llrintl896; CHECK-NEXT: fmov d0, x0897; CHECK-NEXT: ldr q1, [sp, #176] // 16-byte Reload898; CHECK-NEXT: mov v0.d[1], v1.d[0]899; CHECK-NEXT: str q0, [sp, #192] // 16-byte Spill900; CHECK-NEXT: ldr q0, [sp, #224] // 16-byte Reload901; CHECK-NEXT: bl llrintl902; CHECK-NEXT: fmov d0, x0903; CHECK-NEXT: str q0, [sp, #224] // 16-byte Spill904; CHECK-NEXT: ldr q0, [sp, #240] // 16-byte Reload905; CHECK-NEXT: bl llrintl906; CHECK-NEXT: fmov d7, x0907; CHECK-NEXT: ldp q0, q1, [sp, #208] // 32-byte Folded Reload908; CHECK-NEXT: ldp q4, q2, [sp, #96] // 32-byte Folded Reload909; CHECK-NEXT: ldr q3, [sp, #80] // 16-byte Reload910; CHECK-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload911; CHECK-NEXT: ldr q6, [sp, #192] // 16-byte Reload912; CHECK-NEXT: mov v7.d[1], v1.d[0]913; CHECK-NEXT: ldp q5, q1, [sp, #144] // 32-byte Folded Reload914; CHECK-NEXT: add sp, sp, #272915; CHECK-NEXT: ret916 %a = call <16 x i64> @llvm.llrint.v16i64.v16f128(<16 x fp128> %x)917 ret <16 x i64> %a918}919declare <16 x i64> @llvm.llrint.v16i64.v16f128(<16 x fp128>)920