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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4; The mask is all-ones, potentially shifted.5 6;------------------------------------------------------------------------------;7; 128-bit vector; 8-bit elements = 16 elements8;------------------------------------------------------------------------------;9 10; lshr11 12define <16 x i8> @test_128_i8_x_16_7_mask_lshr_1(<16 x i8> %a0) {13; CHECK-LABEL: test_128_i8_x_16_7_mask_lshr_1:14; CHECK: // %bb.0:15; CHECK-NEXT: movi v1.16b, #716; CHECK-NEXT: and v0.16b, v0.16b, v1.16b17; CHECK-NEXT: ushr v0.16b, v0.16b, #118; CHECK-NEXT: ret19 %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>20 %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>21 ret <16 x i8> %t122}23 24define <16 x i8> @test_128_i8_x_16_28_mask_lshr_1(<16 x i8> %a0) {25; CHECK-LABEL: test_128_i8_x_16_28_mask_lshr_1:26; CHECK: // %bb.0:27; CHECK-NEXT: movi v1.16b, #2828; CHECK-NEXT: and v0.16b, v0.16b, v1.16b29; CHECK-NEXT: ushr v0.16b, v0.16b, #130; CHECK-NEXT: ret31 %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>32 %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>33 ret <16 x i8> %t134}35define <16 x i8> @test_128_i8_x_16_28_mask_lshr_2(<16 x i8> %a0) {36; CHECK-LABEL: test_128_i8_x_16_28_mask_lshr_2:37; CHECK: // %bb.0:38; CHECK-NEXT: movi v1.16b, #2839; CHECK-NEXT: and v0.16b, v0.16b, v1.16b40; CHECK-NEXT: ushr v0.16b, v0.16b, #241; CHECK-NEXT: ret42 %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>43 %t1 = lshr <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>44 ret <16 x i8> %t145}46define <16 x i8> @test_128_i8_x_16_28_mask_lshr_3(<16 x i8> %a0) {47; CHECK-LABEL: test_128_i8_x_16_28_mask_lshr_3:48; CHECK: // %bb.0:49; CHECK-NEXT: movi v1.16b, #2850; CHECK-NEXT: and v0.16b, v0.16b, v1.16b51; CHECK-NEXT: ushr v0.16b, v0.16b, #352; CHECK-NEXT: ret53 %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>54 %t1 = lshr <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>55 ret <16 x i8> %t156}57define <16 x i8> @test_128_i8_x_16_28_mask_lshr_4(<16 x i8> %a0) {58; CHECK-LABEL: test_128_i8_x_16_28_mask_lshr_4:59; CHECK: // %bb.0:60; CHECK-NEXT: movi v1.16b, #2861; CHECK-NEXT: and v0.16b, v0.16b, v1.16b62; CHECK-NEXT: ushr v0.16b, v0.16b, #463; CHECK-NEXT: ret64 %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>65 %t1 = lshr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>66 ret <16 x i8> %t167}68 69define <16 x i8> @test_128_i8_x_16_224_mask_lshr_1(<16 x i8> %a0) {70; CHECK-LABEL: test_128_i8_x_16_224_mask_lshr_1:71; CHECK: // %bb.0:72; CHECK-NEXT: movi v1.16b, #22473; CHECK-NEXT: and v0.16b, v0.16b, v1.16b74; CHECK-NEXT: ushr v0.16b, v0.16b, #175; CHECK-NEXT: ret76 %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>77 %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>78 ret <16 x i8> %t179}80define <16 x i8> @test_128_i8_x_16_224_mask_lshr_4(<16 x i8> %a0) {81; CHECK-LABEL: test_128_i8_x_16_224_mask_lshr_4:82; CHECK: // %bb.0:83; CHECK-NEXT: movi v1.16b, #22484; CHECK-NEXT: and v0.16b, v0.16b, v1.16b85; CHECK-NEXT: ushr v0.16b, v0.16b, #486; CHECK-NEXT: ret87 %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>88 %t1 = lshr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>89 ret <16 x i8> %t190}91define <16 x i8> @test_128_i8_x_16_224_mask_lshr_5(<16 x i8> %a0) {92; CHECK-LABEL: test_128_i8_x_16_224_mask_lshr_5:93; CHECK: // %bb.0:94; CHECK-NEXT: ushr v0.16b, v0.16b, #595; CHECK-NEXT: ret96 %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>97 %t1 = lshr <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>98 ret <16 x i8> %t199}100define <16 x i8> @test_128_i8_x_16_224_mask_lshr_6(<16 x i8> %a0) {101; CHECK-LABEL: test_128_i8_x_16_224_mask_lshr_6:102; CHECK: // %bb.0:103; CHECK-NEXT: ushr v0.16b, v0.16b, #6104; CHECK-NEXT: ret105 %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>106 %t1 = lshr <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>107 ret <16 x i8> %t1108}109 110; ashr111 112define <16 x i8> @test_128_i8_x_16_7_mask_ashr_1(<16 x i8> %a0) {113; CHECK-LABEL: test_128_i8_x_16_7_mask_ashr_1:114; CHECK: // %bb.0:115; CHECK-NEXT: movi v1.16b, #7116; CHECK-NEXT: and v0.16b, v0.16b, v1.16b117; CHECK-NEXT: ushr v0.16b, v0.16b, #1118; CHECK-NEXT: ret119 %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>120 %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>121 ret <16 x i8> %t1122}123 124define <16 x i8> @test_128_i8_x_16_28_mask_ashr_1(<16 x i8> %a0) {125; CHECK-LABEL: test_128_i8_x_16_28_mask_ashr_1:126; CHECK: // %bb.0:127; CHECK-NEXT: movi v1.16b, #28128; CHECK-NEXT: and v0.16b, v0.16b, v1.16b129; CHECK-NEXT: ushr v0.16b, v0.16b, #1130; CHECK-NEXT: ret131 %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>132 %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>133 ret <16 x i8> %t1134}135define <16 x i8> @test_128_i8_x_16_28_mask_ashr_2(<16 x i8> %a0) {136; CHECK-LABEL: test_128_i8_x_16_28_mask_ashr_2:137; CHECK: // %bb.0:138; CHECK-NEXT: movi v1.16b, #28139; CHECK-NEXT: and v0.16b, v0.16b, v1.16b140; CHECK-NEXT: ushr v0.16b, v0.16b, #2141; CHECK-NEXT: ret142 %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>143 %t1 = ashr <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>144 ret <16 x i8> %t1145}146define <16 x i8> @test_128_i8_x_16_28_mask_ashr_3(<16 x i8> %a0) {147; CHECK-LABEL: test_128_i8_x_16_28_mask_ashr_3:148; CHECK: // %bb.0:149; CHECK-NEXT: movi v1.16b, #28150; CHECK-NEXT: and v0.16b, v0.16b, v1.16b151; CHECK-NEXT: ushr v0.16b, v0.16b, #3152; CHECK-NEXT: ret153 %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>154 %t1 = ashr <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>155 ret <16 x i8> %t1156}157define <16 x i8> @test_128_i8_x_16_28_mask_ashr_4(<16 x i8> %a0) {158; CHECK-LABEL: test_128_i8_x_16_28_mask_ashr_4:159; CHECK: // %bb.0:160; CHECK-NEXT: movi v1.16b, #28161; CHECK-NEXT: and v0.16b, v0.16b, v1.16b162; CHECK-NEXT: ushr v0.16b, v0.16b, #4163; CHECK-NEXT: ret164 %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>165 %t1 = ashr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>166 ret <16 x i8> %t1167}168 169define <16 x i8> @test_128_i8_x_16_224_mask_ashr_1(<16 x i8> %a0) {170; CHECK-LABEL: test_128_i8_x_16_224_mask_ashr_1:171; CHECK: // %bb.0:172; CHECK-NEXT: movi v1.16b, #224173; CHECK-NEXT: and v0.16b, v0.16b, v1.16b174; CHECK-NEXT: sshr v0.16b, v0.16b, #1175; CHECK-NEXT: ret176 %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>177 %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>178 ret <16 x i8> %t1179}180define <16 x i8> @test_128_i8_x_16_224_mask_ashr_4(<16 x i8> %a0) {181; CHECK-LABEL: test_128_i8_x_16_224_mask_ashr_4:182; CHECK: // %bb.0:183; CHECK-NEXT: movi v1.16b, #224184; CHECK-NEXT: and v0.16b, v0.16b, v1.16b185; CHECK-NEXT: sshr v0.16b, v0.16b, #4186; CHECK-NEXT: ret187 %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>188 %t1 = ashr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>189 ret <16 x i8> %t1190}191define <16 x i8> @test_128_i8_x_16_224_mask_ashr_5(<16 x i8> %a0) {192; CHECK-LABEL: test_128_i8_x_16_224_mask_ashr_5:193; CHECK: // %bb.0:194; CHECK-NEXT: sshr v0.16b, v0.16b, #5195; CHECK-NEXT: ret196 %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>197 %t1 = ashr <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>198 ret <16 x i8> %t1199}200define <16 x i8> @test_128_i8_x_16_224_mask_ashr_6(<16 x i8> %a0) {201; CHECK-LABEL: test_128_i8_x_16_224_mask_ashr_6:202; CHECK: // %bb.0:203; CHECK-NEXT: sshr v0.16b, v0.16b, #6204; CHECK-NEXT: ret205 %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>206 %t1 = ashr <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>207 ret <16 x i8> %t1208}209 210; shl211 212define <16 x i8> @test_128_i8_x_16_7_mask_shl_1(<16 x i8> %a0) {213; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_1:214; CHECK: // %bb.0:215; CHECK-NEXT: movi v1.16b, #7216; CHECK-NEXT: and v0.16b, v0.16b, v1.16b217; CHECK-NEXT: add v0.16b, v0.16b, v0.16b218; CHECK-NEXT: ret219 %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>220 %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>221 ret <16 x i8> %t1222}223define <16 x i8> @test_128_i8_x_16_7_mask_shl_4(<16 x i8> %a0) {224; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_4:225; CHECK: // %bb.0:226; CHECK-NEXT: movi v1.16b, #7227; CHECK-NEXT: and v0.16b, v0.16b, v1.16b228; CHECK-NEXT: shl v0.16b, v0.16b, #4229; CHECK-NEXT: ret230 %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>231 %t1 = shl <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>232 ret <16 x i8> %t1233}234define <16 x i8> @test_128_i8_x_16_7_mask_shl_5(<16 x i8> %a0) {235; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_5:236; CHECK: // %bb.0:237; CHECK-NEXT: shl v0.16b, v0.16b, #5238; CHECK-NEXT: ret239 %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>240 %t1 = shl <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>241 ret <16 x i8> %t1242}243define <16 x i8> @test_128_i8_x_16_7_mask_shl_6(<16 x i8> %a0) {244; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_6:245; CHECK: // %bb.0:246; CHECK-NEXT: shl v0.16b, v0.16b, #6247; CHECK-NEXT: ret248 %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>249 %t1 = shl <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>250 ret <16 x i8> %t1251}252 253define <16 x i8> @test_128_i8_x_16_28_mask_shl_1(<16 x i8> %a0) {254; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_1:255; CHECK: // %bb.0:256; CHECK-NEXT: movi v1.16b, #28257; CHECK-NEXT: and v0.16b, v0.16b, v1.16b258; CHECK-NEXT: add v0.16b, v0.16b, v0.16b259; CHECK-NEXT: ret260 %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>261 %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>262 ret <16 x i8> %t1263}264define <16 x i8> @test_128_i8_x_16_28_mask_shl_2(<16 x i8> %a0) {265; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_2:266; CHECK: // %bb.0:267; CHECK-NEXT: movi v1.16b, #28268; CHECK-NEXT: and v0.16b, v0.16b, v1.16b269; CHECK-NEXT: shl v0.16b, v0.16b, #2270; CHECK-NEXT: ret271 %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>272 %t1 = shl <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>273 ret <16 x i8> %t1274}275define <16 x i8> @test_128_i8_x_16_28_mask_shl_3(<16 x i8> %a0) {276; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_3:277; CHECK: // %bb.0:278; CHECK-NEXT: movi v1.16b, #28279; CHECK-NEXT: and v0.16b, v0.16b, v1.16b280; CHECK-NEXT: shl v0.16b, v0.16b, #3281; CHECK-NEXT: ret282 %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>283 %t1 = shl <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>284 ret <16 x i8> %t1285}286define <16 x i8> @test_128_i8_x_16_28_mask_shl_4(<16 x i8> %a0) {287; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_4:288; CHECK: // %bb.0:289; CHECK-NEXT: movi v1.16b, #28290; CHECK-NEXT: and v0.16b, v0.16b, v1.16b291; CHECK-NEXT: shl v0.16b, v0.16b, #4292; CHECK-NEXT: ret293 %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>294 %t1 = shl <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>295 ret <16 x i8> %t1296}297 298define <16 x i8> @test_128_i8_x_16_224_mask_shl_1(<16 x i8> %a0) {299; CHECK-LABEL: test_128_i8_x_16_224_mask_shl_1:300; CHECK: // %bb.0:301; CHECK-NEXT: movi v1.16b, #224302; CHECK-NEXT: and v0.16b, v0.16b, v1.16b303; CHECK-NEXT: add v0.16b, v0.16b, v0.16b304; CHECK-NEXT: ret305 %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>306 %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>307 ret <16 x i8> %t1308}309 310;------------------------------------------------------------------------------;311; 128-bit vector; 16-bit elements = 8 elements312;------------------------------------------------------------------------------;313 314; lshr315 316define <8 x i16> @test_128_i16_x_8_127_mask_lshr_1(<8 x i16> %a0) {317; CHECK-LABEL: test_128_i16_x_8_127_mask_lshr_1:318; CHECK: // %bb.0:319; CHECK-NEXT: movi v1.8h, #127320; CHECK-NEXT: and v0.16b, v0.16b, v1.16b321; CHECK-NEXT: ushr v0.8h, v0.8h, #1322; CHECK-NEXT: ret323 %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>324 %t1 = lshr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>325 ret <8 x i16> %t1326}327 328define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_3(<8 x i16> %a0) {329; CHECK-LABEL: test_128_i16_x_8_2032_mask_lshr_3:330; CHECK: // %bb.0:331; CHECK-NEXT: mov w8, #2032332; CHECK-NEXT: dup v1.8h, w8333; CHECK-NEXT: and v0.16b, v0.16b, v1.16b334; CHECK-NEXT: ushr v0.8h, v0.8h, #3335; CHECK-NEXT: ret336 %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>337 %t1 = lshr <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>338 ret <8 x i16> %t1339}340define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_4(<8 x i16> %a0) {341; CHECK-LABEL: test_128_i16_x_8_2032_mask_lshr_4:342; CHECK: // %bb.0:343; CHECK-NEXT: mov w8, #2032344; CHECK-NEXT: dup v1.8h, w8345; CHECK-NEXT: and v0.16b, v0.16b, v1.16b346; CHECK-NEXT: ushr v0.8h, v0.8h, #4347; CHECK-NEXT: ret348 %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>349 %t1 = lshr <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>350 ret <8 x i16> %t1351}352define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_5(<8 x i16> %a0) {353; CHECK-LABEL: test_128_i16_x_8_2032_mask_lshr_5:354; CHECK: // %bb.0:355; CHECK-NEXT: mov w8, #2032356; CHECK-NEXT: dup v1.8h, w8357; CHECK-NEXT: and v0.16b, v0.16b, v1.16b358; CHECK-NEXT: ushr v0.8h, v0.8h, #5359; CHECK-NEXT: ret360 %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>361 %t1 = lshr <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>362 ret <8 x i16> %t1363}364define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_6(<8 x i16> %a0) {365; CHECK-LABEL: test_128_i16_x_8_2032_mask_lshr_6:366; CHECK: // %bb.0:367; CHECK-NEXT: mov w8, #2032368; CHECK-NEXT: dup v1.8h, w8369; CHECK-NEXT: and v0.16b, v0.16b, v1.16b370; CHECK-NEXT: ushr v0.8h, v0.8h, #6371; CHECK-NEXT: ret372 %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>373 %t1 = lshr <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>374 ret <8 x i16> %t1375}376 377define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_1(<8 x i16> %a0) {378; CHECK-LABEL: test_128_i16_x_8_65024_mask_lshr_1:379; CHECK: // %bb.0:380; CHECK-NEXT: movi v1.8h, #254, lsl #8381; CHECK-NEXT: and v0.16b, v0.16b, v1.16b382; CHECK-NEXT: ushr v0.8h, v0.8h, #1383; CHECK-NEXT: ret384 %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>385 %t1 = lshr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>386 ret <8 x i16> %t1387}388define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_8(<8 x i16> %a0) {389; CHECK-LABEL: test_128_i16_x_8_65024_mask_lshr_8:390; CHECK: // %bb.0:391; CHECK-NEXT: movi v1.8h, #254, lsl #8392; CHECK-NEXT: and v0.16b, v0.16b, v1.16b393; CHECK-NEXT: ushr v0.8h, v0.8h, #8394; CHECK-NEXT: ret395 %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>396 %t1 = lshr <8 x i16> %t0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>397 ret <8 x i16> %t1398}399define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_9(<8 x i16> %a0) {400; CHECK-LABEL: test_128_i16_x_8_65024_mask_lshr_9:401; CHECK: // %bb.0:402; CHECK-NEXT: ushr v0.8h, v0.8h, #9403; CHECK-NEXT: ret404 %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>405 %t1 = lshr <8 x i16> %t0, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>406 ret <8 x i16> %t1407}408define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_10(<8 x i16> %a0) {409; CHECK-LABEL: test_128_i16_x_8_65024_mask_lshr_10:410; CHECK: // %bb.0:411; CHECK-NEXT: ushr v0.8h, v0.8h, #10412; CHECK-NEXT: ret413 %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>414 %t1 = lshr <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>415 ret <8 x i16> %t1416}417 418; ashr419 420define <8 x i16> @test_128_i16_x_8_127_mask_ashr_1(<8 x i16> %a0) {421; CHECK-LABEL: test_128_i16_x_8_127_mask_ashr_1:422; CHECK: // %bb.0:423; CHECK-NEXT: movi v1.8h, #127424; CHECK-NEXT: and v0.16b, v0.16b, v1.16b425; CHECK-NEXT: ushr v0.8h, v0.8h, #1426; CHECK-NEXT: ret427 %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>428 %t1 = ashr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>429 ret <8 x i16> %t1430}431 432define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_3(<8 x i16> %a0) {433; CHECK-LABEL: test_128_i16_x_8_2032_mask_ashr_3:434; CHECK: // %bb.0:435; CHECK-NEXT: mov w8, #2032436; CHECK-NEXT: dup v1.8h, w8437; CHECK-NEXT: and v0.16b, v0.16b, v1.16b438; CHECK-NEXT: ushr v0.8h, v0.8h, #3439; CHECK-NEXT: ret440 %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>441 %t1 = ashr <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>442 ret <8 x i16> %t1443}444define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_4(<8 x i16> %a0) {445; CHECK-LABEL: test_128_i16_x_8_2032_mask_ashr_4:446; CHECK: // %bb.0:447; CHECK-NEXT: mov w8, #2032448; CHECK-NEXT: dup v1.8h, w8449; CHECK-NEXT: and v0.16b, v0.16b, v1.16b450; CHECK-NEXT: ushr v0.8h, v0.8h, #4451; CHECK-NEXT: ret452 %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>453 %t1 = ashr <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>454 ret <8 x i16> %t1455}456define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_5(<8 x i16> %a0) {457; CHECK-LABEL: test_128_i16_x_8_2032_mask_ashr_5:458; CHECK: // %bb.0:459; CHECK-NEXT: mov w8, #2032460; CHECK-NEXT: dup v1.8h, w8461; CHECK-NEXT: and v0.16b, v0.16b, v1.16b462; CHECK-NEXT: ushr v0.8h, v0.8h, #5463; CHECK-NEXT: ret464 %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>465 %t1 = ashr <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>466 ret <8 x i16> %t1467}468define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_6(<8 x i16> %a0) {469; CHECK-LABEL: test_128_i16_x_8_2032_mask_ashr_6:470; CHECK: // %bb.0:471; CHECK-NEXT: mov w8, #2032472; CHECK-NEXT: dup v1.8h, w8473; CHECK-NEXT: and v0.16b, v0.16b, v1.16b474; CHECK-NEXT: ushr v0.8h, v0.8h, #6475; CHECK-NEXT: ret476 %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>477 %t1 = ashr <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>478 ret <8 x i16> %t1479}480 481define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_1(<8 x i16> %a0) {482; CHECK-LABEL: test_128_i16_x_8_65024_mask_ashr_1:483; CHECK: // %bb.0:484; CHECK-NEXT: movi v1.8h, #254, lsl #8485; CHECK-NEXT: and v0.16b, v0.16b, v1.16b486; CHECK-NEXT: sshr v0.8h, v0.8h, #1487; CHECK-NEXT: ret488 %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>489 %t1 = ashr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>490 ret <8 x i16> %t1491}492define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_8(<8 x i16> %a0) {493; CHECK-LABEL: test_128_i16_x_8_65024_mask_ashr_8:494; CHECK: // %bb.0:495; CHECK-NEXT: movi v1.8h, #254, lsl #8496; CHECK-NEXT: and v0.16b, v0.16b, v1.16b497; CHECK-NEXT: sshr v0.8h, v0.8h, #8498; CHECK-NEXT: ret499 %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>500 %t1 = ashr <8 x i16> %t0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>501 ret <8 x i16> %t1502}503define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_9(<8 x i16> %a0) {504; CHECK-LABEL: test_128_i16_x_8_65024_mask_ashr_9:505; CHECK: // %bb.0:506; CHECK-NEXT: sshr v0.8h, v0.8h, #9507; CHECK-NEXT: ret508 %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>509 %t1 = ashr <8 x i16> %t0, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>510 ret <8 x i16> %t1511}512define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_10(<8 x i16> %a0) {513; CHECK-LABEL: test_128_i16_x_8_65024_mask_ashr_10:514; CHECK: // %bb.0:515; CHECK-NEXT: sshr v0.8h, v0.8h, #10516; CHECK-NEXT: ret517 %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>518 %t1 = ashr <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>519 ret <8 x i16> %t1520}521 522; shl523 524define <8 x i16> @test_128_i16_x_8_127_mask_shl_1(<8 x i16> %a0) {525; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_1:526; CHECK: // %bb.0:527; CHECK-NEXT: movi v1.8h, #127528; CHECK-NEXT: and v0.16b, v0.16b, v1.16b529; CHECK-NEXT: add v0.8h, v0.8h, v0.8h530; CHECK-NEXT: ret531 %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>532 %t1 = shl <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>533 ret <8 x i16> %t1534}535define <8 x i16> @test_128_i16_x_8_127_mask_shl_8(<8 x i16> %a0) {536; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_8:537; CHECK: // %bb.0:538; CHECK-NEXT: movi v1.8h, #127539; CHECK-NEXT: and v0.16b, v0.16b, v1.16b540; CHECK-NEXT: shl v0.8h, v0.8h, #8541; CHECK-NEXT: ret542 %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>543 %t1 = shl <8 x i16> %t0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>544 ret <8 x i16> %t1545}546define <8 x i16> @test_128_i16_x_8_127_mask_shl_9(<8 x i16> %a0) {547; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_9:548; CHECK: // %bb.0:549; CHECK-NEXT: shl v0.8h, v0.8h, #9550; CHECK-NEXT: ret551 %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>552 %t1 = shl <8 x i16> %t0, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>553 ret <8 x i16> %t1554}555define <8 x i16> @test_128_i16_x_8_127_mask_shl_10(<8 x i16> %a0) {556; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_10:557; CHECK: // %bb.0:558; CHECK-NEXT: shl v0.8h, v0.8h, #10559; CHECK-NEXT: ret560 %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>561 %t1 = shl <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>562 ret <8 x i16> %t1563}564 565define <8 x i16> @test_128_i16_x_8_2032_mask_shl_3(<8 x i16> %a0) {566; CHECK-LABEL: test_128_i16_x_8_2032_mask_shl_3:567; CHECK: // %bb.0:568; CHECK-NEXT: mov w8, #2032569; CHECK-NEXT: dup v1.8h, w8570; CHECK-NEXT: and v0.16b, v0.16b, v1.16b571; CHECK-NEXT: shl v0.8h, v0.8h, #3572; CHECK-NEXT: ret573 %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>574 %t1 = shl <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>575 ret <8 x i16> %t1576}577define <8 x i16> @test_128_i16_x_8_2032_mask_shl_4(<8 x i16> %a0) {578; CHECK-LABEL: test_128_i16_x_8_2032_mask_shl_4:579; CHECK: // %bb.0:580; CHECK-NEXT: mov w8, #2032581; CHECK-NEXT: dup v1.8h, w8582; CHECK-NEXT: and v0.16b, v0.16b, v1.16b583; CHECK-NEXT: shl v0.8h, v0.8h, #4584; CHECK-NEXT: ret585 %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>586 %t1 = shl <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>587 ret <8 x i16> %t1588}589define <8 x i16> @test_128_i16_x_8_2032_mask_shl_5(<8 x i16> %a0) {590; CHECK-LABEL: test_128_i16_x_8_2032_mask_shl_5:591; CHECK: // %bb.0:592; CHECK-NEXT: mov w8, #2032593; CHECK-NEXT: dup v1.8h, w8594; CHECK-NEXT: and v0.16b, v0.16b, v1.16b595; CHECK-NEXT: shl v0.8h, v0.8h, #5596; CHECK-NEXT: ret597 %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>598 %t1 = shl <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>599 ret <8 x i16> %t1600}601define <8 x i16> @test_128_i16_x_8_2032_mask_shl_6(<8 x i16> %a0) {602; CHECK-LABEL: test_128_i16_x_8_2032_mask_shl_6:603; CHECK: // %bb.0:604; CHECK-NEXT: mov w8, #2032605; CHECK-NEXT: dup v1.8h, w8606; CHECK-NEXT: and v0.16b, v0.16b, v1.16b607; CHECK-NEXT: shl v0.8h, v0.8h, #6608; CHECK-NEXT: ret609 %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>610 %t1 = shl <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>611 ret <8 x i16> %t1612}613 614define <8 x i16> @test_128_i16_x_8_65024_mask_shl_1(<8 x i16> %a0) {615; CHECK-LABEL: test_128_i16_x_8_65024_mask_shl_1:616; CHECK: // %bb.0:617; CHECK-NEXT: movi v1.8h, #254, lsl #8618; CHECK-NEXT: and v0.16b, v0.16b, v1.16b619; CHECK-NEXT: add v0.8h, v0.8h, v0.8h620; CHECK-NEXT: ret621 %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>622 %t1 = shl <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>623 ret <8 x i16> %t1624}625 626;------------------------------------------------------------------------------;627; 128-bit vector; 32-bit elements = 4 elements628;------------------------------------------------------------------------------;629 630; lshr631 632define <4 x i32> @test_128_i32_x_4_32767_mask_lshr_1(<4 x i32> %a0) {633; CHECK-LABEL: test_128_i32_x_4_32767_mask_lshr_1:634; CHECK: // %bb.0:635; CHECK-NEXT: movi v1.4s, #127, msl #8636; CHECK-NEXT: and v0.16b, v0.16b, v1.16b637; CHECK-NEXT: ushr v0.4s, v0.4s, #1638; CHECK-NEXT: ret639 %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>640 %t1 = lshr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>641 ret <4 x i32> %t1642}643 644define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_7(<4 x i32> %a0) {645; CHECK-LABEL: test_128_i32_x_4_8388352_mask_lshr_7:646; CHECK: // %bb.0:647; CHECK-NEXT: mov w8, #8388352648; CHECK-NEXT: dup v1.4s, w8649; CHECK-NEXT: and v0.16b, v0.16b, v1.16b650; CHECK-NEXT: ushr v0.4s, v0.4s, #7651; CHECK-NEXT: ret652 %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>653 %t1 = lshr <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>654 ret <4 x i32> %t1655}656define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_8(<4 x i32> %a0) {657; CHECK-LABEL: test_128_i32_x_4_8388352_mask_lshr_8:658; CHECK: // %bb.0:659; CHECK-NEXT: mov w8, #8388352660; CHECK-NEXT: dup v1.4s, w8661; CHECK-NEXT: and v0.16b, v0.16b, v1.16b662; CHECK-NEXT: ushr v0.4s, v0.4s, #8663; CHECK-NEXT: ret664 %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>665 %t1 = lshr <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>666 ret <4 x i32> %t1667}668define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_9(<4 x i32> %a0) {669; CHECK-LABEL: test_128_i32_x_4_8388352_mask_lshr_9:670; CHECK: // %bb.0:671; CHECK-NEXT: mov w8, #8388352672; CHECK-NEXT: dup v1.4s, w8673; CHECK-NEXT: and v0.16b, v0.16b, v1.16b674; CHECK-NEXT: ushr v0.4s, v0.4s, #9675; CHECK-NEXT: ret676 %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>677 %t1 = lshr <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>678 ret <4 x i32> %t1679}680define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_10(<4 x i32> %a0) {681; CHECK-LABEL: test_128_i32_x_4_8388352_mask_lshr_10:682; CHECK: // %bb.0:683; CHECK-NEXT: mov w8, #8388352684; CHECK-NEXT: dup v1.4s, w8685; CHECK-NEXT: and v0.16b, v0.16b, v1.16b686; CHECK-NEXT: ushr v0.4s, v0.4s, #10687; CHECK-NEXT: ret688 %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>689 %t1 = lshr <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>690 ret <4 x i32> %t1691}692 693define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_1(<4 x i32> %a0) {694; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1:695; CHECK: // %bb.0:696; CHECK-NEXT: mvni v1.4s, #1, msl #16697; CHECK-NEXT: and v0.16b, v0.16b, v1.16b698; CHECK-NEXT: ushr v0.4s, v0.4s, #1699; CHECK-NEXT: ret700 %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>701 %t1 = lshr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>702 ret <4 x i32> %t1703}704define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_16(<4 x i32> %a0) {705; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16:706; CHECK: // %bb.0:707; CHECK-NEXT: mvni v1.4s, #1, msl #16708; CHECK-NEXT: and v0.16b, v0.16b, v1.16b709; CHECK-NEXT: ushr v0.4s, v0.4s, #16710; CHECK-NEXT: ret711 %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>712 %t1 = lshr <4 x i32> %t0, <i32 16, i32 16, i32 16, i32 16>713 ret <4 x i32> %t1714}715define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_17(<4 x i32> %a0) {716; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_lshr_17:717; CHECK: // %bb.0:718; CHECK-NEXT: ushr v0.4s, v0.4s, #17719; CHECK-NEXT: ret720 %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>721 %t1 = lshr <4 x i32> %t0, <i32 17, i32 17, i32 17, i32 17>722 ret <4 x i32> %t1723}724define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_18(<4 x i32> %a0) {725; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_lshr_18:726; CHECK: // %bb.0:727; CHECK-NEXT: ushr v0.4s, v0.4s, #18728; CHECK-NEXT: ret729 %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>730 %t1 = lshr <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18>731 ret <4 x i32> %t1732}733 734; ashr735 736define <4 x i32> @test_128_i32_x_4_32767_mask_ashr_1(<4 x i32> %a0) {737; CHECK-LABEL: test_128_i32_x_4_32767_mask_ashr_1:738; CHECK: // %bb.0:739; CHECK-NEXT: movi v1.4s, #127, msl #8740; CHECK-NEXT: and v0.16b, v0.16b, v1.16b741; CHECK-NEXT: ushr v0.4s, v0.4s, #1742; CHECK-NEXT: ret743 %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>744 %t1 = ashr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>745 ret <4 x i32> %t1746}747 748define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_7(<4 x i32> %a0) {749; CHECK-LABEL: test_128_i32_x_4_8388352_mask_ashr_7:750; CHECK: // %bb.0:751; CHECK-NEXT: mov w8, #8388352752; CHECK-NEXT: dup v1.4s, w8753; CHECK-NEXT: and v0.16b, v0.16b, v1.16b754; CHECK-NEXT: ushr v0.4s, v0.4s, #7755; CHECK-NEXT: ret756 %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>757 %t1 = ashr <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>758 ret <4 x i32> %t1759}760define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_8(<4 x i32> %a0) {761; CHECK-LABEL: test_128_i32_x_4_8388352_mask_ashr_8:762; CHECK: // %bb.0:763; CHECK-NEXT: mov w8, #8388352764; CHECK-NEXT: dup v1.4s, w8765; CHECK-NEXT: and v0.16b, v0.16b, v1.16b766; CHECK-NEXT: ushr v0.4s, v0.4s, #8767; CHECK-NEXT: ret768 %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>769 %t1 = ashr <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>770 ret <4 x i32> %t1771}772define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_9(<4 x i32> %a0) {773; CHECK-LABEL: test_128_i32_x_4_8388352_mask_ashr_9:774; CHECK: // %bb.0:775; CHECK-NEXT: mov w8, #8388352776; CHECK-NEXT: dup v1.4s, w8777; CHECK-NEXT: and v0.16b, v0.16b, v1.16b778; CHECK-NEXT: ushr v0.4s, v0.4s, #9779; CHECK-NEXT: ret780 %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>781 %t1 = ashr <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>782 ret <4 x i32> %t1783}784define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_10(<4 x i32> %a0) {785; CHECK-LABEL: test_128_i32_x_4_8388352_mask_ashr_10:786; CHECK: // %bb.0:787; CHECK-NEXT: mov w8, #8388352788; CHECK-NEXT: dup v1.4s, w8789; CHECK-NEXT: and v0.16b, v0.16b, v1.16b790; CHECK-NEXT: ushr v0.4s, v0.4s, #10791; CHECK-NEXT: ret792 %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>793 %t1 = ashr <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>794 ret <4 x i32> %t1795}796 797define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_1(<4 x i32> %a0) {798; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1:799; CHECK: // %bb.0:800; CHECK-NEXT: mvni v1.4s, #1, msl #16801; CHECK-NEXT: and v0.16b, v0.16b, v1.16b802; CHECK-NEXT: sshr v0.4s, v0.4s, #1803; CHECK-NEXT: ret804 %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>805 %t1 = ashr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>806 ret <4 x i32> %t1807}808define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_16(<4 x i32> %a0) {809; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16:810; CHECK: // %bb.0:811; CHECK-NEXT: mvni v1.4s, #1, msl #16812; CHECK-NEXT: and v0.16b, v0.16b, v1.16b813; CHECK-NEXT: sshr v0.4s, v0.4s, #16814; CHECK-NEXT: ret815 %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>816 %t1 = ashr <4 x i32> %t0, <i32 16, i32 16, i32 16, i32 16>817 ret <4 x i32> %t1818}819define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_17(<4 x i32> %a0) {820; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_ashr_17:821; CHECK: // %bb.0:822; CHECK-NEXT: sshr v0.4s, v0.4s, #17823; CHECK-NEXT: ret824 %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>825 %t1 = ashr <4 x i32> %t0, <i32 17, i32 17, i32 17, i32 17>826 ret <4 x i32> %t1827}828define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_18(<4 x i32> %a0) {829; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_ashr_18:830; CHECK: // %bb.0:831; CHECK-NEXT: sshr v0.4s, v0.4s, #18832; CHECK-NEXT: ret833 %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>834 %t1 = ashr <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18>835 ret <4 x i32> %t1836}837 838; shl839 840define <4 x i32> @test_128_i32_x_4_32767_mask_shl_1(<4 x i32> %a0) {841; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_1:842; CHECK: // %bb.0:843; CHECK-NEXT: movi v1.4s, #127, msl #8844; CHECK-NEXT: and v0.16b, v0.16b, v1.16b845; CHECK-NEXT: add v0.4s, v0.4s, v0.4s846; CHECK-NEXT: ret847 %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>848 %t1 = shl <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>849 ret <4 x i32> %t1850}851define <4 x i32> @test_128_i32_x_4_32767_mask_shl_16(<4 x i32> %a0) {852; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_16:853; CHECK: // %bb.0:854; CHECK-NEXT: movi v1.4s, #127, msl #8855; CHECK-NEXT: and v0.16b, v0.16b, v1.16b856; CHECK-NEXT: shl v0.4s, v0.4s, #16857; CHECK-NEXT: ret858 %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>859 %t1 = shl <4 x i32> %t0, <i32 16, i32 16, i32 16, i32 16>860 ret <4 x i32> %t1861}862define <4 x i32> @test_128_i32_x_4_32767_mask_shl_17(<4 x i32> %a0) {863; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_17:864; CHECK: // %bb.0:865; CHECK-NEXT: shl v0.4s, v0.4s, #17866; CHECK-NEXT: ret867 %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>868 %t1 = shl <4 x i32> %t0, <i32 17, i32 17, i32 17, i32 17>869 ret <4 x i32> %t1870}871define <4 x i32> @test_128_i32_x_4_32767_mask_shl_18(<4 x i32> %a0) {872; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_18:873; CHECK: // %bb.0:874; CHECK-NEXT: shl v0.4s, v0.4s, #18875; CHECK-NEXT: ret876 %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>877 %t1 = shl <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18>878 ret <4 x i32> %t1879}880 881define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_7(<4 x i32> %a0) {882; CHECK-LABEL: test_128_i32_x_4_8388352_mask_shl_7:883; CHECK: // %bb.0:884; CHECK-NEXT: mov w8, #8388352885; CHECK-NEXT: dup v1.4s, w8886; CHECK-NEXT: and v0.16b, v0.16b, v1.16b887; CHECK-NEXT: shl v0.4s, v0.4s, #7888; CHECK-NEXT: ret889 %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>890 %t1 = shl <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>891 ret <4 x i32> %t1892}893define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_8(<4 x i32> %a0) {894; CHECK-LABEL: test_128_i32_x_4_8388352_mask_shl_8:895; CHECK: // %bb.0:896; CHECK-NEXT: mov w8, #8388352897; CHECK-NEXT: dup v1.4s, w8898; CHECK-NEXT: and v0.16b, v0.16b, v1.16b899; CHECK-NEXT: shl v0.4s, v0.4s, #8900; CHECK-NEXT: ret901 %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>902 %t1 = shl <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>903 ret <4 x i32> %t1904}905define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_9(<4 x i32> %a0) {906; CHECK-LABEL: test_128_i32_x_4_8388352_mask_shl_9:907; CHECK: // %bb.0:908; CHECK-NEXT: mov w8, #8388352909; CHECK-NEXT: dup v1.4s, w8910; CHECK-NEXT: and v0.16b, v0.16b, v1.16b911; CHECK-NEXT: shl v0.4s, v0.4s, #9912; CHECK-NEXT: ret913 %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>914 %t1 = shl <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>915 ret <4 x i32> %t1916}917define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_10(<4 x i32> %a0) {918; CHECK-LABEL: test_128_i32_x_4_8388352_mask_shl_10:919; CHECK: // %bb.0:920; CHECK-NEXT: mov w8, #8388352921; CHECK-NEXT: dup v1.4s, w8922; CHECK-NEXT: and v0.16b, v0.16b, v1.16b923; CHECK-NEXT: shl v0.4s, v0.4s, #10924; CHECK-NEXT: ret925 %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>926 %t1 = shl <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>927 ret <4 x i32> %t1928}929 930define <4 x i32> @test_128_i32_x_4_4294836224_mask_shl_1(<4 x i32> %a0) {931; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_shl_1:932; CHECK: // %bb.0:933; CHECK-NEXT: mvni v1.4s, #1, msl #16934; CHECK-NEXT: and v0.16b, v0.16b, v1.16b935; CHECK-NEXT: add v0.4s, v0.4s, v0.4s936; CHECK-NEXT: ret937 %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>938 %t1 = shl <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>939 ret <4 x i32> %t1940}941 942;------------------------------------------------------------------------------;943; 128-bit vector; 64-bit elements = 2 elements944;------------------------------------------------------------------------------;945 946; lshr947 948define <2 x i64> @test_128_i64_x_2_2147483647_mask_lshr_1(<2 x i64> %a0) {949; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1:950; CHECK: // %bb.0:951; CHECK-NEXT: mov w8, #2147483647952; CHECK-NEXT: dup v1.2d, x8953; CHECK-NEXT: and v0.16b, v0.16b, v1.16b954; CHECK-NEXT: ushr v0.2d, v0.2d, #1955; CHECK-NEXT: ret956 %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>957 %t1 = lshr <2 x i64> %t0, <i64 1, i64 1>958 ret <2 x i64> %t1959}960 961define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_15(<2 x i64> %a0) {962; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15:963; CHECK: // %bb.0:964; CHECK-NEXT: mov x8, #140737488289792965; CHECK-NEXT: dup v1.2d, x8966; CHECK-NEXT: and v0.16b, v0.16b, v1.16b967; CHECK-NEXT: ushr v0.2d, v0.2d, #15968; CHECK-NEXT: ret969 %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>970 %t1 = lshr <2 x i64> %t0, <i64 15, i64 15>971 ret <2 x i64> %t1972}973define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_16(<2 x i64> %a0) {974; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16:975; CHECK: // %bb.0:976; CHECK-NEXT: mov x8, #140737488289792977; CHECK-NEXT: dup v1.2d, x8978; CHECK-NEXT: and v0.16b, v0.16b, v1.16b979; CHECK-NEXT: ushr v0.2d, v0.2d, #16980; CHECK-NEXT: ret981 %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>982 %t1 = lshr <2 x i64> %t0, <i64 16, i64 16>983 ret <2 x i64> %t1984}985define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_17(<2 x i64> %a0) {986; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17:987; CHECK: // %bb.0:988; CHECK-NEXT: mov x8, #140737488289792989; CHECK-NEXT: dup v1.2d, x8990; CHECK-NEXT: and v0.16b, v0.16b, v1.16b991; CHECK-NEXT: ushr v0.2d, v0.2d, #17992; CHECK-NEXT: ret993 %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>994 %t1 = lshr <2 x i64> %t0, <i64 17, i64 17>995 ret <2 x i64> %t1996}997define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_18(<2 x i64> %a0) {998; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18:999; CHECK: // %bb.0:1000; CHECK-NEXT: mov x8, #1407374882897921001; CHECK-NEXT: dup v1.2d, x81002; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1003; CHECK-NEXT: ushr v0.2d, v0.2d, #181004; CHECK-NEXT: ret1005 %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>1006 %t1 = lshr <2 x i64> %t0, <i64 18, i64 18>1007 ret <2 x i64> %t11008}1009 1010define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_1(<2 x i64> %a0) {1011; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1:1012; CHECK: // %bb.0:1013; CHECK-NEXT: mov x8, #-85899345921014; CHECK-NEXT: dup v1.2d, x81015; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1016; CHECK-NEXT: ushr v0.2d, v0.2d, #11017; CHECK-NEXT: ret1018 %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>1019 %t1 = lshr <2 x i64> %t0, <i64 1, i64 1>1020 ret <2 x i64> %t11021}1022define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_32(<2 x i64> %a0) {1023; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32:1024; CHECK: // %bb.0:1025; CHECK-NEXT: mov x8, #-85899345921026; CHECK-NEXT: dup v1.2d, x81027; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1028; CHECK-NEXT: ushr v0.2d, v0.2d, #321029; CHECK-NEXT: ret1030 %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>1031 %t1 = lshr <2 x i64> %t0, <i64 32, i64 32>1032 ret <2 x i64> %t11033}1034define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_33(<2 x i64> %a0) {1035; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_33:1036; CHECK: // %bb.0:1037; CHECK-NEXT: ushr v0.2d, v0.2d, #331038; CHECK-NEXT: ret1039 %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>1040 %t1 = lshr <2 x i64> %t0, <i64 33, i64 33>1041 ret <2 x i64> %t11042}1043define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_34(<2 x i64> %a0) {1044; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_34:1045; CHECK: // %bb.0:1046; CHECK-NEXT: ushr v0.2d, v0.2d, #341047; CHECK-NEXT: ret1048 %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>1049 %t1 = lshr <2 x i64> %t0, <i64 34, i64 34>1050 ret <2 x i64> %t11051}1052 1053; ashr1054 1055define <2 x i64> @test_128_i64_x_2_2147483647_mask_ashr_1(<2 x i64> %a0) {1056; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1:1057; CHECK: // %bb.0:1058; CHECK-NEXT: mov w8, #21474836471059; CHECK-NEXT: dup v1.2d, x81060; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1061; CHECK-NEXT: ushr v0.2d, v0.2d, #11062; CHECK-NEXT: ret1063 %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>1064 %t1 = ashr <2 x i64> %t0, <i64 1, i64 1>1065 ret <2 x i64> %t11066}1067 1068define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_15(<2 x i64> %a0) {1069; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15:1070; CHECK: // %bb.0:1071; CHECK-NEXT: mov x8, #1407374882897921072; CHECK-NEXT: dup v1.2d, x81073; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1074; CHECK-NEXT: ushr v0.2d, v0.2d, #151075; CHECK-NEXT: ret1076 %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>1077 %t1 = ashr <2 x i64> %t0, <i64 15, i64 15>1078 ret <2 x i64> %t11079}1080define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_16(<2 x i64> %a0) {1081; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16:1082; CHECK: // %bb.0:1083; CHECK-NEXT: mov x8, #1407374882897921084; CHECK-NEXT: dup v1.2d, x81085; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1086; CHECK-NEXT: ushr v0.2d, v0.2d, #161087; CHECK-NEXT: ret1088 %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>1089 %t1 = ashr <2 x i64> %t0, <i64 16, i64 16>1090 ret <2 x i64> %t11091}1092define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_17(<2 x i64> %a0) {1093; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17:1094; CHECK: // %bb.0:1095; CHECK-NEXT: mov x8, #1407374882897921096; CHECK-NEXT: dup v1.2d, x81097; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1098; CHECK-NEXT: ushr v0.2d, v0.2d, #171099; CHECK-NEXT: ret1100 %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>1101 %t1 = ashr <2 x i64> %t0, <i64 17, i64 17>1102 ret <2 x i64> %t11103}1104define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_18(<2 x i64> %a0) {1105; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18:1106; CHECK: // %bb.0:1107; CHECK-NEXT: mov x8, #1407374882897921108; CHECK-NEXT: dup v1.2d, x81109; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1110; CHECK-NEXT: ushr v0.2d, v0.2d, #181111; CHECK-NEXT: ret1112 %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>1113 %t1 = ashr <2 x i64> %t0, <i64 18, i64 18>1114 ret <2 x i64> %t11115}1116 1117define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_1(<2 x i64> %a0) {1118; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:1119; CHECK: // %bb.0:1120; CHECK-NEXT: mov x8, #-85899345921121; CHECK-NEXT: dup v1.2d, x81122; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1123; CHECK-NEXT: sshr v0.2d, v0.2d, #11124; CHECK-NEXT: ret1125 %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>1126 %t1 = ashr <2 x i64> %t0, <i64 1, i64 1>1127 ret <2 x i64> %t11128}1129define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_32(<2 x i64> %a0) {1130; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:1131; CHECK: // %bb.0:1132; CHECK-NEXT: mov x8, #-85899345921133; CHECK-NEXT: dup v1.2d, x81134; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1135; CHECK-NEXT: sshr v0.2d, v0.2d, #321136; CHECK-NEXT: ret1137 %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>1138 %t1 = ashr <2 x i64> %t0, <i64 32, i64 32>1139 ret <2 x i64> %t11140}1141define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_33(<2 x i64> %a0) {1142; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_33:1143; CHECK: // %bb.0:1144; CHECK-NEXT: sshr v0.2d, v0.2d, #331145; CHECK-NEXT: ret1146 %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>1147 %t1 = ashr <2 x i64> %t0, <i64 33, i64 33>1148 ret <2 x i64> %t11149}1150define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_34(<2 x i64> %a0) {1151; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_34:1152; CHECK: // %bb.0:1153; CHECK-NEXT: sshr v0.2d, v0.2d, #341154; CHECK-NEXT: ret1155 %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>1156 %t1 = ashr <2 x i64> %t0, <i64 34, i64 34>1157 ret <2 x i64> %t11158}1159 1160; shl1161 1162define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_1(<2 x i64> %a0) {1163; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_1:1164; CHECK: // %bb.0:1165; CHECK-NEXT: mov w8, #21474836471166; CHECK-NEXT: dup v1.2d, x81167; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1168; CHECK-NEXT: add v0.2d, v0.2d, v0.2d1169; CHECK-NEXT: ret1170 %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>1171 %t1 = shl <2 x i64> %t0, <i64 1, i64 1>1172 ret <2 x i64> %t11173}1174define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_32(<2 x i64> %a0) {1175; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_32:1176; CHECK: // %bb.0:1177; CHECK-NEXT: mov w8, #21474836471178; CHECK-NEXT: dup v1.2d, x81179; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1180; CHECK-NEXT: shl v0.2d, v0.2d, #321181; CHECK-NEXT: ret1182 %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>1183 %t1 = shl <2 x i64> %t0, <i64 32, i64 32>1184 ret <2 x i64> %t11185}1186define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_33(<2 x i64> %a0) {1187; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_33:1188; CHECK: // %bb.0:1189; CHECK-NEXT: shl v0.2d, v0.2d, #331190; CHECK-NEXT: ret1191 %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>1192 %t1 = shl <2 x i64> %t0, <i64 33, i64 33>1193 ret <2 x i64> %t11194}1195define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_34(<2 x i64> %a0) {1196; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_34:1197; CHECK: // %bb.0:1198; CHECK-NEXT: shl v0.2d, v0.2d, #341199; CHECK-NEXT: ret1200 %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>1201 %t1 = shl <2 x i64> %t0, <i64 34, i64 34>1202 ret <2 x i64> %t11203}1204 1205define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_15(<2 x i64> %a0) {1206; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15:1207; CHECK: // %bb.0:1208; CHECK-NEXT: mov x8, #1407374882897921209; CHECK-NEXT: dup v1.2d, x81210; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1211; CHECK-NEXT: shl v0.2d, v0.2d, #151212; CHECK-NEXT: ret1213 %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>1214 %t1 = shl <2 x i64> %t0, <i64 15, i64 15>1215 ret <2 x i64> %t11216}1217define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_16(<2 x i64> %a0) {1218; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16:1219; CHECK: // %bb.0:1220; CHECK-NEXT: mov x8, #1407374882897921221; CHECK-NEXT: dup v1.2d, x81222; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1223; CHECK-NEXT: shl v0.2d, v0.2d, #161224; CHECK-NEXT: ret1225 %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>1226 %t1 = shl <2 x i64> %t0, <i64 16, i64 16>1227 ret <2 x i64> %t11228}1229define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_17(<2 x i64> %a0) {1230; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17:1231; CHECK: // %bb.0:1232; CHECK-NEXT: mov x8, #1407374882897921233; CHECK-NEXT: dup v1.2d, x81234; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1235; CHECK-NEXT: shl v0.2d, v0.2d, #171236; CHECK-NEXT: ret1237 %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>1238 %t1 = shl <2 x i64> %t0, <i64 17, i64 17>1239 ret <2 x i64> %t11240}1241define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_18(<2 x i64> %a0) {1242; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18:1243; CHECK: // %bb.0:1244; CHECK-NEXT: mov x8, #1407374882897921245; CHECK-NEXT: dup v1.2d, x81246; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1247; CHECK-NEXT: shl v0.2d, v0.2d, #181248; CHECK-NEXT: ret1249 %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>1250 %t1 = shl <2 x i64> %t0, <i64 18, i64 18>1251 ret <2 x i64> %t11252}1253 1254define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_shl_1(<2 x i64> %a0) {1255; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1:1256; CHECK: // %bb.0:1257; CHECK-NEXT: mov x8, #-85899345921258; CHECK-NEXT: dup v1.2d, x81259; CHECK-NEXT: and v0.16b, v0.16b, v1.16b1260; CHECK-NEXT: add v0.2d, v0.2d, v0.2d1261; CHECK-NEXT: ret1262 %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>1263 %t1 = shl <2 x i64> %t0, <i64 1, i64 1>1264 ret <2 x i64> %t11265}1266