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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s3 4; First, check the generic pattern for any 2 vector constants. Then, check special cases where5; the constants are all off-by-one. Finally, check the extra special cases where the constants6; include 0 or -1.7; Each minimal select test is repeated with a more typical pattern that includes a compare to8; generate the condition value.9 10define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) {11; CHECK-LABEL: sel_C1_or_C2_vec:12; CHECK: // %bb.0:13; CHECK-NEXT: ushll v0.4s, v0.4h, #014; CHECK-NEXT: adrp x8, .LCPI0_015; CHECK-NEXT: adrp x9, .LCPI0_116; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]17; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI0_1]18; CHECK-NEXT: shl v0.4s, v0.4s, #3119; CHECK-NEXT: cmlt v0.4s, v0.4s, #020; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b21; CHECK-NEXT: ret22 %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>23 ret <4 x i32> %add24}25 26define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {27; CHECK-LABEL: cmp_sel_C1_or_C2_vec:28; CHECK: // %bb.0:29; CHECK-NEXT: adrp x8, .LCPI1_030; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s31; CHECK-NEXT: adrp x9, .LCPI1_132; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]33; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI1_1]34; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b35; CHECK-NEXT: ret36 %cond = icmp eq <4 x i32> %x, %y37 %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>38 ret <4 x i32> %add39}40 41define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) {42; CHECK-LABEL: sel_Cplus1_or_C_vec:43; CHECK: // %bb.0:44; CHECK-NEXT: ushll v0.4s, v0.4h, #045; CHECK-NEXT: adrp x8, .LCPI2_046; CHECK-NEXT: adrp x9, .LCPI2_147; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]48; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI2_1]49; CHECK-NEXT: shl v0.4s, v0.4s, #3150; CHECK-NEXT: cmlt v0.4s, v0.4s, #051; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b52; CHECK-NEXT: ret53 %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>54 ret <4 x i32> %add55}56 57define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {58; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec:59; CHECK: // %bb.0:60; CHECK-NEXT: adrp x8, .LCPI3_061; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s62; CHECK-NEXT: adrp x9, .LCPI3_163; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]64; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI3_1]65; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b66; CHECK-NEXT: ret67 %cond = icmp eq <4 x i32> %x, %y68 %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>69 ret <4 x i32> %add70}71 72define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {73; CHECK-LABEL: sel_Cminus1_or_C_vec:74; CHECK: // %bb.0:75; CHECK-NEXT: ushll v0.4s, v0.4h, #076; CHECK-NEXT: adrp x8, .LCPI4_077; CHECK-NEXT: adrp x9, .LCPI4_178; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]79; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI4_1]80; CHECK-NEXT: shl v0.4s, v0.4s, #3181; CHECK-NEXT: cmlt v0.4s, v0.4s, #082; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b83; CHECK-NEXT: ret84 %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>85 ret <4 x i32> %add86}87 88define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {89; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec:90; CHECK: // %bb.0:91; CHECK-NEXT: adrp x8, .LCPI5_092; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s93; CHECK-NEXT: adrp x9, .LCPI5_194; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0]95; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI5_1]96; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b97; CHECK-NEXT: ret98 %cond = icmp eq <4 x i32> %x, %y99 %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>100 ret <4 x i32> %add101}102 103define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) {104; CHECK-LABEL: sel_minus1_or_0_vec:105; CHECK: // %bb.0:106; CHECK-NEXT: ushll v0.4s, v0.4h, #0107; CHECK-NEXT: shl v0.4s, v0.4s, #31108; CHECK-NEXT: cmlt v0.4s, v0.4s, #0109; CHECK-NEXT: ret110 %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>111 ret <4 x i32> %add112}113 114define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {115; CHECK-LABEL: cmp_sel_minus1_or_0_vec:116; CHECK: // %bb.0:117; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s118; CHECK-NEXT: ret119 %cond = icmp eq <4 x i32> %x, %y120 %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>121 ret <4 x i32> %add122}123 124define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {125; CHECK-LABEL: sel_0_or_minus1_vec:126; CHECK: // %bb.0:127; CHECK-NEXT: ushll v0.4s, v0.4h, #0128; CHECK-NEXT: shl v0.4s, v0.4s, #31129; CHECK-NEXT: cmge v0.4s, v0.4s, #0130; CHECK-NEXT: ret131 %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>132 ret <4 x i32> %add133}134 135define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {136; CHECK-LABEL: cmp_sel_0_or_minus1_vec:137; CHECK: // %bb.0:138; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s139; CHECK-NEXT: mvn v0.16b, v0.16b140; CHECK-NEXT: ret141 %cond = icmp eq <4 x i32> %x, %y142 %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>143 ret <4 x i32> %add144}145 146define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) {147; CHECK-LABEL: sel_1_or_0_vec:148; CHECK: // %bb.0:149; CHECK-NEXT: movi v1.4s, #1150; CHECK-NEXT: ushll v0.4s, v0.4h, #0151; CHECK-NEXT: and v0.16b, v0.16b, v1.16b152; CHECK-NEXT: ret153 %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>154 ret <4 x i32> %add155}156 157define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {158; CHECK-LABEL: cmp_sel_1_or_0_vec:159; CHECK: // %bb.0:160; CHECK-NEXT: movi v2.4s, #1161; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s162; CHECK-NEXT: and v0.16b, v0.16b, v2.16b163; CHECK-NEXT: ret164 %cond = icmp eq <4 x i32> %x, %y165 %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>166 ret <4 x i32> %add167}168 169define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) {170; CHECK-LABEL: sel_0_or_1_vec:171; CHECK: // %bb.0:172; CHECK-NEXT: movi v1.4s, #1173; CHECK-NEXT: ushll v0.4s, v0.4h, #0174; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b175; CHECK-NEXT: ret176 %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>177 ret <4 x i32> %add178}179 180define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) {181; CHECK-LABEL: cmp_sel_0_or_1_vec:182; CHECK: // %bb.0:183; CHECK-NEXT: movi v2.4s, #1184; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s185; CHECK-NEXT: bic v0.16b, v2.16b, v0.16b186; CHECK-NEXT: ret187 %cond = icmp eq <4 x i32> %x, %y188 %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>189 ret <4 x i32> %add190}191 192define <16 x i8> @signbit_mask_v16i8(<16 x i8> %a, <16 x i8> %b) {193; CHECK-LABEL: signbit_mask_v16i8:194; CHECK: // %bb.0:195; CHECK-NEXT: cmlt v0.16b, v0.16b, #0196; CHECK-NEXT: and v0.16b, v0.16b, v1.16b197; CHECK-NEXT: ret198 %cond = icmp slt <16 x i8> %a, zeroinitializer199 %r = select <16 x i1> %cond, <16 x i8> %b, <16 x i8> zeroinitializer200 ret <16 x i8> %r201}202 203; Swap cmp pred and select ops. This is logically equivalent to the above test.204 205define <16 x i8> @signbit_mask_swap_v16i8(<16 x i8> %a, <16 x i8> %b) {206; CHECK-LABEL: signbit_mask_swap_v16i8:207; CHECK: // %bb.0:208; CHECK-NEXT: cmlt v0.16b, v0.16b, #0209; CHECK-NEXT: and v0.16b, v0.16b, v1.16b210; CHECK-NEXT: ret211 %cond = icmp sgt <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>212 %r = select <16 x i1> %cond, <16 x i8> zeroinitializer, <16 x i8> %b213 ret <16 x i8> %r214}215 216define <8 x i16> @signbit_mask_v8i16(<8 x i16> %a, <8 x i16> %b) {217; CHECK-LABEL: signbit_mask_v8i16:218; CHECK: // %bb.0:219; CHECK-NEXT: cmlt v0.8h, v0.8h, #0220; CHECK-NEXT: and v0.16b, v0.16b, v1.16b221; CHECK-NEXT: ret222 %cond = icmp slt <8 x i16> %a, zeroinitializer223 %r = select <8 x i1> %cond, <8 x i16> %b, <8 x i16> zeroinitializer224 ret <8 x i16> %r225}226 227define <4 x i32> @signbit_mask_v4i32(<4 x i32> %a, <4 x i32> %b) {228; CHECK-LABEL: signbit_mask_v4i32:229; CHECK: // %bb.0:230; CHECK-NEXT: cmlt v0.4s, v0.4s, #0231; CHECK-NEXT: and v0.16b, v0.16b, v1.16b232; CHECK-NEXT: ret233 %cond = icmp slt <4 x i32> %a, zeroinitializer234 %r = select <4 x i1> %cond, <4 x i32> %b, <4 x i32> zeroinitializer235 ret <4 x i32> %r236}237 238define <2 x i64> @signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {239; CHECK-LABEL: signbit_mask_v2i64:240; CHECK: // %bb.0:241; CHECK-NEXT: cmlt v0.2d, v0.2d, #0242; CHECK-NEXT: and v0.16b, v0.16b, v1.16b243; CHECK-NEXT: ret244 %cond = icmp slt <2 x i64> %a, zeroinitializer245 %r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer246 ret <2 x i64> %r247}248 249define <16 x i8> @signbit_setmask_v16i8(<16 x i8> %a, <16 x i8> %b) {250; CHECK-LABEL: signbit_setmask_v16i8:251; CHECK: // %bb.0:252; CHECK-NEXT: cmlt v0.16b, v0.16b, #0253; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b254; CHECK-NEXT: ret255 %cond = icmp slt <16 x i8> %a, zeroinitializer256 %r = select <16 x i1> %cond, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %b257 ret <16 x i8> %r258}259 260define <8 x i16> @signbit_setmask_v8i16(<8 x i16> %a, <8 x i16> %b) {261; CHECK-LABEL: signbit_setmask_v8i16:262; CHECK: // %bb.0:263; CHECK-NEXT: cmlt v0.8h, v0.8h, #0264; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b265; CHECK-NEXT: ret266 %cond = icmp slt <8 x i16> %a, zeroinitializer267 %r = select <8 x i1> %cond, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %b268 ret <8 x i16> %r269}270 271; Swap cmp pred and select ops. This is logically equivalent to the above test.272 273define <8 x i16> @signbit_setmask_swap_v8i16(<8 x i16> %a, <8 x i16> %b) {274; CHECK-LABEL: signbit_setmask_swap_v8i16:275; CHECK: // %bb.0:276; CHECK-NEXT: cmlt v0.8h, v0.8h, #0277; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b278; CHECK-NEXT: ret279 %cond = icmp sgt <8 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>280 %r = select <8 x i1> %cond, <8 x i16> %b, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>281 ret <8 x i16> %r282}283 284define <4 x i32> @signbit_setmask_v4i32(<4 x i32> %a, <4 x i32> %b) {285; CHECK-LABEL: signbit_setmask_v4i32:286; CHECK: // %bb.0:287; CHECK-NEXT: cmlt v0.4s, v0.4s, #0288; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b289; CHECK-NEXT: ret290 %cond = icmp slt <4 x i32> %a, zeroinitializer291 %r = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %b292 ret <4 x i32> %r293}294 295define <2 x i64> @signbit_setmask_v2i64(<2 x i64> %a, <2 x i64> %b) {296; CHECK-LABEL: signbit_setmask_v2i64:297; CHECK: // %bb.0:298; CHECK-NEXT: cmlt v0.2d, v0.2d, #0299; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b300; CHECK-NEXT: ret301 %cond = icmp slt <2 x i64> %a, zeroinitializer302 %r = select <2 x i1> %cond, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %b303 ret <2 x i64> %r304}305 306define <16 x i8> @not_signbit_mask_v16i8(<16 x i8> %a, <16 x i8> %b) {307; CHECK-LABEL: not_signbit_mask_v16i8:308; CHECK: // %bb.0:309; CHECK-NEXT: cmge v0.16b, v0.16b, #0310; CHECK-NEXT: and v0.16b, v0.16b, v1.16b311; CHECK-NEXT: ret312 %cond = icmp sgt <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>313 %r = select <16 x i1> %cond, <16 x i8> %b, <16 x i8> zeroinitializer314 ret <16 x i8> %r315}316 317define <8 x i16> @not_signbit_mask_v8i16(<8 x i16> %a, <8 x i16> %b) {318; CHECK-LABEL: not_signbit_mask_v8i16:319; CHECK: // %bb.0:320; CHECK-NEXT: cmge v0.8h, v0.8h, #0321; CHECK-NEXT: and v0.16b, v0.16b, v1.16b322; CHECK-NEXT: ret323 %cond = icmp sgt <8 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>324 %r = select <8 x i1> %cond, <8 x i16> %b, <8 x i16> zeroinitializer325 ret <8 x i16> %r326}327 328define <4 x i32> @not_signbit_mask_v4i32(<4 x i32> %a, <4 x i32> %b) {329; CHECK-LABEL: not_signbit_mask_v4i32:330; CHECK: // %bb.0:331; CHECK-NEXT: cmge v0.4s, v0.4s, #0332; CHECK-NEXT: and v0.16b, v0.16b, v1.16b333; CHECK-NEXT: ret334 %cond = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>335 %r = select <4 x i1> %cond, <4 x i32> %b, <4 x i32> zeroinitializer336 ret <4 x i32> %r337}338 339; Swap cmp pred and select ops. This is logically equivalent to the above test.340 341define <4 x i32> @not_signbit_mask_swap_v4i32(<4 x i32> %a, <4 x i32> %b) {342; CHECK-LABEL: not_signbit_mask_swap_v4i32:343; CHECK: // %bb.0:344; CHECK-NEXT: cmge v0.4s, v0.4s, #0345; CHECK-NEXT: and v0.16b, v0.16b, v1.16b346; CHECK-NEXT: ret347 %cond = icmp slt <4 x i32> %a, zeroinitializer348 %r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %b349 ret <4 x i32> %r350}351 352define <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {353; CHECK-LABEL: not_signbit_mask_v2i64:354; CHECK: // %bb.0:355; CHECK-NEXT: cmge v0.2d, v0.2d, #0356; CHECK-NEXT: and v0.16b, v0.16b, v1.16b357; CHECK-NEXT: ret358 %cond = icmp sgt <2 x i64> %a, <i64 -1, i64 -1>359 %r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer360 ret <2 x i64> %r361}362 363; SVE364 365define <vscale x 16 x i8> @signbit_mask_xor_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {366; CHECK-LABEL: signbit_mask_xor_nxv16i8:367; CHECK: // %bb.0:368; CHECK-NEXT: eor z1.d, z0.d, z1.d369; CHECK-NEXT: asr z0.b, z0.b, #7370; CHECK-NEXT: bic z0.d, z1.d, z0.d371; CHECK-NEXT: ret372 %cond = icmp slt <vscale x 16 x i8> %a, zeroinitializer373 %xor = xor <vscale x 16 x i8> %a, %b374 %r = select <vscale x 16 x i1> %cond, <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %xor375 ret <vscale x 16 x i8> %r376}377 378attributes #0 = { "target-features"="+sve" }379