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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm64-apple-ios -o - %s | FileCheck %s3 4define <16 x i32> @no_existing_zext(<16 x i8> %a, <16 x i32> %op) {5; CHECK-LABEL: no_existing_zext:6; CHECK: ; %bb.0: ; %entry7; CHECK-NEXT: movi.16b v5, #108; CHECK-NEXT: cmhi.16b v0, v0, v59; CHECK-NEXT: sshll.8h v5, v0, #010; CHECK-NEXT: sshll2.8h v0, v0, #011; CHECK-NEXT: sshll2.4s v16, v0, #012; CHECK-NEXT: sshll.4s v6, v5, #013; CHECK-NEXT: sshll.4s v7, v0, #014; CHECK-NEXT: sshll2.4s v5, v5, #015; CHECK-NEXT: and.16b v4, v16, v416; CHECK-NEXT: and.16b v0, v6, v117; CHECK-NEXT: and.16b v1, v5, v218; CHECK-NEXT: and.16b v2, v7, v319; CHECK-NEXT: mov.16b v3, v420; CHECK-NEXT: ret21entry:22 %cmp = icmp ugt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>23 %sel = select <16 x i1> %cmp, <16 x i32> %op, <16 x i32> zeroinitializer24 ret <16 x i32> %sel25}26 27define <16 x i32> @second_compare_operand_not_splat(<16 x i8> %a, <16 x i8> %b) {28; CHECK-LABEL: second_compare_operand_not_splat:29; CHECK: ; %bb.0: ; %entry30; CHECK-NEXT: cmgt.16b v1, v0, v131; CHECK-NEXT: ushll.8h v2, v0, #032; CHECK-NEXT: ushll2.8h v0, v0, #033; CHECK-NEXT: sshll.8h v3, v1, #034; CHECK-NEXT: sshll2.8h v1, v1, #035; CHECK-NEXT: ushll.4s v4, v2, #036; CHECK-NEXT: ushll.4s v5, v0, #037; CHECK-NEXT: ushll2.4s v2, v2, #038; CHECK-NEXT: ushll2.4s v6, v0, #039; CHECK-NEXT: sshll.4s v0, v3, #040; CHECK-NEXT: sshll.4s v7, v1, #041; CHECK-NEXT: sshll2.4s v16, v3, #042; CHECK-NEXT: sshll2.4s v1, v1, #043; CHECK-NEXT: and.16b v0, v0, v444; CHECK-NEXT: and.16b v3, v1, v645; CHECK-NEXT: and.16b v1, v16, v246; CHECK-NEXT: and.16b v2, v7, v547; CHECK-NEXT: ret48entry:49 %ext = zext <16 x i8> %a to <16 x i32>50 %cmp = icmp sgt <16 x i8> %a, %b51 %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer52 ret <16 x i32> %sel53}54 55define <16 x i32> @same_zext_used_in_cmp_signed_pred_and_select(<16 x i8> %a) {56; CHECK-LABEL: same_zext_used_in_cmp_signed_pred_and_select:57; CHECK: ; %bb.0: ; %entry58; CHECK-NEXT: movi.16b v1, #1059; CHECK-NEXT: ushll.8h v2, v0, #060; CHECK-NEXT: ushll.4s v4, v2, #061; CHECK-NEXT: ushll2.4s v2, v2, #062; CHECK-NEXT: cmgt.16b v1, v0, v163; CHECK-NEXT: ushll2.8h v0, v0, #064; CHECK-NEXT: sshll.8h v3, v1, #065; CHECK-NEXT: sshll2.8h v1, v1, #066; CHECK-NEXT: ushll.4s v5, v0, #067; CHECK-NEXT: ushll2.4s v6, v0, #068; CHECK-NEXT: sshll.4s v0, v3, #069; CHECK-NEXT: sshll.4s v7, v1, #070; CHECK-NEXT: sshll2.4s v16, v3, #071; CHECK-NEXT: sshll2.4s v1, v1, #072; CHECK-NEXT: and.16b v0, v0, v473; CHECK-NEXT: and.16b v3, v1, v674; CHECK-NEXT: and.16b v1, v16, v275; CHECK-NEXT: and.16b v2, v7, v576; CHECK-NEXT: ret77entry:78 %ext = zext <16 x i8> %a to <16 x i32>79 %cmp = icmp sgt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>80 %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer81 ret <16 x i32> %sel82}83 84define <8 x i64> @same_zext_used_in_cmp_unsigned_pred_and_select_v8i64(<8 x i8> %a) {85; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v8i64:86; CHECK: ; %bb.0:87; CHECK-NEXT: ushll.8h v0, v0, #088; CHECK-NEXT: mov w8, #10 ; =0xa89; CHECK-NEXT: dup.2d v2, x890; CHECK-NEXT: ushll.4s v1, v0, #091; CHECK-NEXT: ushll2.4s v0, v0, #092; CHECK-NEXT: ushll.2d v3, v1, #093; CHECK-NEXT: ushll2.2d v4, v0, #094; CHECK-NEXT: ushll2.2d v1, v1, #095; CHECK-NEXT: ushll.2d v5, v0, #096; CHECK-NEXT: cmhi.2d v0, v3, v297; CHECK-NEXT: cmhi.2d v7, v1, v298; CHECK-NEXT: cmhi.2d v6, v5, v299; CHECK-NEXT: cmhi.2d v2, v4, v2100; CHECK-NEXT: and.16b v0, v0, v3101; CHECK-NEXT: and.16b v1, v7, v1102; CHECK-NEXT: and.16b v3, v2, v4103; CHECK-NEXT: and.16b v2, v6, v5104; CHECK-NEXT: ret105 %ext = zext <8 x i8> %a to <8 x i64>106 %cmp = icmp ugt <8 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>107 %sel = select <8 x i1> %cmp, <8 x i64> %ext, <8 x i64> zeroinitializer108 ret <8 x i64> %sel109}110 111 112define <16 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v16i32(<16 x i8> %a) {113; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v16i32:114; CHECK: ; %bb.0:115; CHECK-NEXT: ushll.8h v2, v0, #0116; CHECK-NEXT: ushll2.8h v0, v0, #0117; CHECK-NEXT: movi.4s v1, #10118; CHECK-NEXT: ushll.4s v3, v2, #0119; CHECK-NEXT: ushll2.4s v4, v0, #0120; CHECK-NEXT: ushll2.4s v2, v2, #0121; CHECK-NEXT: ushll.4s v5, v0, #0122; CHECK-NEXT: cmhi.4s v0, v3, v1123; CHECK-NEXT: cmhi.4s v7, v2, v1124; CHECK-NEXT: cmhi.4s v6, v5, v1125; CHECK-NEXT: cmhi.4s v1, v4, v1126; CHECK-NEXT: and.16b v0, v0, v3127; CHECK-NEXT: and.16b v3, v1, v4128; CHECK-NEXT: and.16b v1, v7, v2129; CHECK-NEXT: and.16b v2, v6, v5130; CHECK-NEXT: ret131 %ext = zext <16 x i8> %a to <16 x i32>132 %cmp = icmp ugt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>133 %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer134 ret <16 x i32> %sel135}136 137define <8 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v8i32(<8 x i8> %a) {138; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v8i32:139; CHECK: ; %bb.0:140; CHECK-NEXT: ushll.8h v0, v0, #0141; CHECK-NEXT: movi.4s v1, #10142; CHECK-NEXT: ushll2.4s v2, v0, #0143; CHECK-NEXT: ushll.4s v0, v0, #0144; CHECK-NEXT: cmhi.4s v3, v0, v1145; CHECK-NEXT: cmhi.4s v1, v2, v1146; CHECK-NEXT: and.16b v1, v1, v2147; CHECK-NEXT: and.16b v0, v3, v0148; CHECK-NEXT: ret149 %ext = zext <8 x i8> %a to <8 x i32>150 %cmp = icmp ugt <8 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>151 %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer152 ret <8 x i32> %sel153}154 155define <8 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_2(<8 x i16> %a) {156; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_2:157; CHECK: ; %bb.0:158; CHECK-NEXT: movi.4s v1, #10159; CHECK-NEXT: ushll2.4s v2, v0, #0160; CHECK-NEXT: ushll.4s v0, v0, #0161; CHECK-NEXT: cmhi.4s v3, v0, v1162; CHECK-NEXT: cmhi.4s v1, v2, v1163; CHECK-NEXT: and.16b v1, v1, v2164; CHECK-NEXT: and.16b v0, v3, v0165; CHECK-NEXT: ret166 %ext = zext <8 x i16> %a to <8 x i32>167 %cmp = icmp ugt <8 x i16> %a, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>168 %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer169 ret <8 x i32> %sel170}171 172 173define <8 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_from_v8i15(<8 x i15> %a) {174; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_from_v8i15:175; CHECK: ; %bb.0:176; CHECK-NEXT: bic.8h v0, #128, lsl #8177; CHECK-NEXT: movi.4s v1, #10178; CHECK-NEXT: ushll2.4s v2, v0, #0179; CHECK-NEXT: ushll.4s v0, v0, #0180; CHECK-NEXT: cmhi.4s v3, v0, v1181; CHECK-NEXT: cmhi.4s v1, v2, v1182; CHECK-NEXT: and.16b v1, v1, v2183; CHECK-NEXT: and.16b v0, v3, v0184; CHECK-NEXT: ret185 %ext = zext <8 x i15> %a to <8 x i32>186 %cmp = icmp ugt <8 x i15> %a, <i15 10, i15 10, i15 10, i15 10, i15 10, i15 10, i15 10, i15 10>187 %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer188 ret <8 x i32> %sel189}190 191define <7 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v7i32(<7 x i16> %a) {192; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v7i32:193; CHECK: ; %bb.0:194; CHECK-NEXT: movi.8h v1, #10195; CHECK-NEXT: ushll.4s v2, v0, #0196; CHECK-NEXT: cmhi.8h v1, v0, v1197; CHECK-NEXT: ushll2.4s v0, v0, #0198; CHECK-NEXT: sshll.4s v3, v1, #0199; CHECK-NEXT: sshll2.4s v1, v1, #0200; CHECK-NEXT: and.16b v2, v3, v2201; CHECK-NEXT: and.16b v0, v1, v0202; CHECK-NEXT: mov.s w1, v2[1]203; CHECK-NEXT: mov.s w2, v2[2]204; CHECK-NEXT: mov.s w3, v2[3]205; CHECK-NEXT: mov.s w5, v0[1]206; CHECK-NEXT: mov.s w6, v0[2]207; CHECK-NEXT: fmov w0, s2208; CHECK-NEXT: fmov w4, s0209; CHECK-NEXT: ret210 %ext = zext <7 x i16> %a to <7 x i32>211 %cmp = icmp ugt <7 x i16> %a, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>212 %sel = select <7 x i1> %cmp, <7 x i32> %ext, <7 x i32> zeroinitializer213 ret <7 x i32> %sel214}215 216define <3 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v3i16(<3 x i8> %a) {217; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v3i16:218; CHECK: ; %bb.0:219; CHECK-NEXT: fmov s0, w0220; CHECK-NEXT: Lloh0:221; CHECK-NEXT: adrp x8, lCPI9_0@PAGE222; CHECK-NEXT: movi.2d v3, #0x0000ff000000ff223; CHECK-NEXT: Lloh1:224; CHECK-NEXT: ldr d2, [x8, lCPI9_0@PAGEOFF]225; CHECK-NEXT: mov.h v0[1], w1226; CHECK-NEXT: mov.h v0[2], w2227; CHECK-NEXT: ushll.4s v1, v0, #0228; CHECK-NEXT: bic.4h v0, #255, lsl #8229; CHECK-NEXT: cmhi.4h v0, v0, v2230; CHECK-NEXT: and.16b v1, v1, v3231; CHECK-NEXT: sshll.4s v0, v0, #0232; CHECK-NEXT: and.16b v0, v1, v0233; CHECK-NEXT: ret234; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1235 %ext = zext <3 x i8> %a to <3 x i32>236 %cmp = icmp ugt <3 x i8> %a, <i8 10, i8 10, i8 10>237 %sel = select <3 x i1> %cmp, <3 x i32> %ext, <3 x i32> zeroinitializer238 ret <3 x i32> %sel239}240 241define <4 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v4i32(<4 x i16> %a) {242; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v4i32:243; CHECK: ; %bb.0:244; CHECK-NEXT: movi.4s v1, #10245; CHECK-NEXT: ushll.4s v0, v0, #0246; CHECK-NEXT: cmhi.4s v1, v0, v1247; CHECK-NEXT: and.16b v0, v1, v0248; CHECK-NEXT: ret249 %ext = zext <4 x i16> %a to <4 x i32>250 %cmp = icmp ugt <4 x i16> %a, <i16 10, i16 10, i16 10, i16 10>251 %sel = select <4 x i1> %cmp, <4 x i32> %ext, <4 x i32> zeroinitializer252 ret <4 x i32> %sel253}254 255define <2 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v2i32(<2 x i16> %a) {256; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v2i32:257; CHECK: ; %bb.0:258; CHECK-NEXT: movi d1, #0x00ffff0000ffff259; CHECK-NEXT: movi.2s v2, #10260; CHECK-NEXT: and.8b v0, v0, v1261; CHECK-NEXT: cmhi.2s v1, v0, v2262; CHECK-NEXT: and.8b v0, v1, v0263; CHECK-NEXT: ret264 %ext = zext <2 x i16> %a to <2 x i32>265 %cmp = icmp ugt <2 x i16> %a, <i16 10, i16 10>266 %sel = select <2 x i1> %cmp, <2 x i32> %ext, <2 x i32> zeroinitializer267 ret <2 x i32> %sel268}269 270define <8 x i32> @same_zext_used_in_cmp_eq_and_select_v8i32(<8 x i16> %a) {271; CHECK-LABEL: same_zext_used_in_cmp_eq_and_select_v8i32:272; CHECK: ; %bb.0:273; CHECK-NEXT: movi.4s v1, #10274; CHECK-NEXT: ushll2.4s v2, v0, #0275; CHECK-NEXT: ushll.4s v0, v0, #0276; CHECK-NEXT: cmeq.4s v3, v0, v1277; CHECK-NEXT: cmeq.4s v1, v2, v1278; CHECK-NEXT: and.16b v1, v1, v2279; CHECK-NEXT: and.16b v0, v3, v0280; CHECK-NEXT: ret281 %ext = zext <8 x i16> %a to <8 x i32>282 %cmp = icmp eq <8 x i16> %a, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>283 %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer284 ret <8 x i32> %sel285}286 287define <8 x i32> @same_zext_used_in_cmp_eq_and_select_v8i32_from_v8i13(<8 x i13> %a) {288; CHECK-LABEL: same_zext_used_in_cmp_eq_and_select_v8i32_from_v8i13:289; CHECK: ; %bb.0:290; CHECK-NEXT: bic.8h v0, #224, lsl #8291; CHECK-NEXT: movi.4s v1, #10292; CHECK-NEXT: ushll2.4s v2, v0, #0293; CHECK-NEXT: ushll.4s v0, v0, #0294; CHECK-NEXT: cmeq.4s v3, v0, v1295; CHECK-NEXT: cmeq.4s v1, v2, v1296; CHECK-NEXT: and.16b v1, v1, v2297; CHECK-NEXT: and.16b v0, v3, v0298; CHECK-NEXT: ret299 %ext = zext <8 x i13> %a to <8 x i32>300 %cmp = icmp eq <8 x i13> %a, <i13 10, i13 10, i13 10, i13 10, i13 10, i13 10, i13 10, i13 10>301 %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer302 ret <8 x i32> %sel303}304 305define <16 x i32> @same_zext_used_in_cmp_ne_and_select_v8i32(<16 x i8> %a) {306; CHECK-LABEL: same_zext_used_in_cmp_ne_and_select_v8i32:307; CHECK: ; %bb.0:308; CHECK-NEXT: ushll.8h v2, v0, #0309; CHECK-NEXT: ushll2.8h v0, v0, #0310; CHECK-NEXT: movi.4s v1, #10311; CHECK-NEXT: ushll.4s v3, v2, #0312; CHECK-NEXT: ushll2.4s v4, v0, #0313; CHECK-NEXT: ushll2.4s v2, v2, #0314; CHECK-NEXT: ushll.4s v5, v0, #0315; CHECK-NEXT: cmeq.4s v0, v3, v1316; CHECK-NEXT: cmeq.4s v7, v2, v1317; CHECK-NEXT: cmeq.4s v6, v5, v1318; CHECK-NEXT: cmeq.4s v1, v4, v1319; CHECK-NEXT: bic.16b v0, v3, v0320; CHECK-NEXT: bic.16b v3, v4, v1321; CHECK-NEXT: bic.16b v1, v2, v7322; CHECK-NEXT: bic.16b v2, v5, v6323; CHECK-NEXT: ret324 %ext = zext <16 x i8> %a to <16 x i32>325 %cmp = icmp ne <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>326 %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer327 ret <16 x i32> %sel328}329 330; A variation of @same_zext_used_in_cmp_unsigned_pred_and_select, with with331; multiple users of the compare.332define <16 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_other_use(<16 x i8> %a, <16 x i64> %v, ptr %ptr) {333; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_other_use:334; CHECK: ; %bb.0: ; %entry335; CHECK-NEXT: movi.16b v16, #10336; CHECK-NEXT: ushll.8h v19, v0, #0337; CHECK-NEXT: ldr q22, [sp]338; CHECK-NEXT: ushll.4s v24, v19, #0339; CHECK-NEXT: ushll2.4s v19, v19, #0340; CHECK-NEXT: cmhi.16b v16, v0, v16341; CHECK-NEXT: ushll2.8h v0, v0, #0342; CHECK-NEXT: sshll2.8h v17, v16, #0343; CHECK-NEXT: sshll.8h v16, v16, #0344; CHECK-NEXT: ushll.4s v25, v0, #0345; CHECK-NEXT: ushll2.4s v0, v0, #0346; CHECK-NEXT: sshll2.4s v18, v17, #0347; CHECK-NEXT: sshll.4s v17, v17, #0348; CHECK-NEXT: sshll2.4s v20, v16, #0349; CHECK-NEXT: sshll.4s v16, v16, #0350; CHECK-NEXT: sshll2.2d v21, v18, #0351; CHECK-NEXT: sshll.2d v23, v18, #0352; CHECK-NEXT: sshll2.2d v26, v17, #0353; CHECK-NEXT: sshll2.2d v27, v20, #0354; CHECK-NEXT: and.16b v21, v22, v21355; CHECK-NEXT: sshll.2d v22, v17, #0356; CHECK-NEXT: and.16b v7, v7, v23357; CHECK-NEXT: sshll.2d v23, v20, #0358; CHECK-NEXT: and.16b v6, v6, v26359; CHECK-NEXT: sshll2.2d v26, v16, #0360; CHECK-NEXT: and.16b v27, v4, v27361; CHECK-NEXT: and.16b v4, v18, v0362; CHECK-NEXT: and.16b v0, v16, v24363; CHECK-NEXT: stp q7, q21, [x0, #96]364; CHECK-NEXT: sshll.2d v21, v16, #0365; CHECK-NEXT: and.16b v5, v5, v22366; CHECK-NEXT: and.16b v7, v3, v23367; CHECK-NEXT: and.16b v3, v20, v19368; CHECK-NEXT: stp q5, q6, [x0, #64]369; CHECK-NEXT: and.16b v6, v2, v26370; CHECK-NEXT: and.16b v2, v17, v25371; CHECK-NEXT: and.16b v5, v1, v21372; CHECK-NEXT: mov.16b v1, v3373; CHECK-NEXT: mov.16b v3, v4374; CHECK-NEXT: stp q7, q27, [x0, #32]375; CHECK-NEXT: stp q5, q6, [x0]376; CHECK-NEXT: ret377entry:378 %ext = zext <16 x i8> %a to <16 x i32>379 %cmp = icmp ugt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>380 %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer381 %sel.2 = select <16 x i1> %cmp, <16 x i64> %v, <16 x i64> zeroinitializer382 store <16 x i64> %sel.2, ptr %ptr383 ret <16 x i32> %sel384}385 386define <16 x i32> @same_sext_used_in_cmp_signed_pred_and_select_v16i32(<16 x i8> %a) {387; CHECK-LABEL: same_sext_used_in_cmp_signed_pred_and_select_v16i32:388; CHECK: ; %bb.0: ; %entry389; CHECK-NEXT: sshll.8h v2, v0, #0390; CHECK-NEXT: sshll2.8h v0, v0, #0391; CHECK-NEXT: movi.4s v1, #10392; CHECK-NEXT: sshll.4s v3, v2, #0393; CHECK-NEXT: sshll2.4s v4, v0, #0394; CHECK-NEXT: sshll2.4s v2, v2, #0395; CHECK-NEXT: sshll.4s v5, v0, #0396; CHECK-NEXT: cmgt.4s v0, v3, v1397; CHECK-NEXT: cmgt.4s v7, v2, v1398; CHECK-NEXT: cmgt.4s v6, v5, v1399; CHECK-NEXT: cmgt.4s v1, v4, v1400; CHECK-NEXT: and.16b v0, v0, v3401; CHECK-NEXT: and.16b v3, v1, v4402; CHECK-NEXT: and.16b v1, v7, v2403; CHECK-NEXT: and.16b v2, v6, v5404; CHECK-NEXT: ret405entry:406 %ext = sext <16 x i8> %a to <16 x i32>407 %cmp = icmp sgt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>408 %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer409 ret <16 x i32> %sel410}411 412define <8 x i32> @same_sext_used_in_cmp_eq_and_select_v8i32(<8 x i16> %a) {413; CHECK-LABEL: same_sext_used_in_cmp_eq_and_select_v8i32:414; CHECK: ; %bb.0:415; CHECK-NEXT: movi.4s v1, #10416; CHECK-NEXT: sshll2.4s v2, v0, #0417; CHECK-NEXT: sshll.4s v0, v0, #0418; CHECK-NEXT: cmeq.4s v3, v0, v1419; CHECK-NEXT: cmeq.4s v1, v2, v1420; CHECK-NEXT: and.16b v1, v1, v2421; CHECK-NEXT: and.16b v0, v3, v0422; CHECK-NEXT: ret423 %ext = sext <8 x i16> %a to <8 x i32>424 %cmp = icmp eq <8 x i16> %a, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>425 %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer426 ret <8 x i32> %sel427}428 429define <8 x i32> @same_sext_used_in_cmp_eq_and_select_v8i32_from_v8i13(<8 x i13> %a) {430; CHECK-LABEL: same_sext_used_in_cmp_eq_and_select_v8i32_from_v8i13:431; CHECK: ; %bb.0:432; CHECK-NEXT: ushll.4s v2, v0, #0433; CHECK-NEXT: ushll2.4s v0, v0, #0434; CHECK-NEXT: movi.4s v1, #10435; CHECK-NEXT: shl.4s v0, v0, #19436; CHECK-NEXT: shl.4s v2, v2, #19437; CHECK-NEXT: sshr.4s v0, v0, #19438; CHECK-NEXT: sshr.4s v2, v2, #19439; CHECK-NEXT: cmeq.4s v3, v2, v1440; CHECK-NEXT: cmeq.4s v1, v0, v1441; CHECK-NEXT: and.16b v1, v1, v0442; CHECK-NEXT: and.16b v0, v3, v2443; CHECK-NEXT: ret444 %ext = sext <8 x i13> %a to <8 x i32>445 %cmp = icmp eq <8 x i13> %a, <i13 10, i13 10, i13 10, i13 10, i13 10, i13 10, i13 10, i13 10>446 %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer447 ret <8 x i32> %sel448}449 450define <16 x i32> @same_sext_used_in_cmp_ne_and_select_v8i32(<16 x i8> %a) {451; CHECK-LABEL: same_sext_used_in_cmp_ne_and_select_v8i32:452; CHECK: ; %bb.0:453; CHECK-NEXT: sshll.8h v2, v0, #0454; CHECK-NEXT: sshll2.8h v0, v0, #0455; CHECK-NEXT: movi.4s v1, #10456; CHECK-NEXT: sshll.4s v3, v2, #0457; CHECK-NEXT: sshll2.4s v4, v0, #0458; CHECK-NEXT: sshll2.4s v2, v2, #0459; CHECK-NEXT: sshll.4s v5, v0, #0460; CHECK-NEXT: cmeq.4s v0, v3, v1461; CHECK-NEXT: cmeq.4s v7, v2, v1462; CHECK-NEXT: cmeq.4s v6, v5, v1463; CHECK-NEXT: cmeq.4s v1, v4, v1464; CHECK-NEXT: bic.16b v0, v3, v0465; CHECK-NEXT: bic.16b v3, v4, v1466; CHECK-NEXT: bic.16b v1, v2, v7467; CHECK-NEXT: bic.16b v2, v5, v6468; CHECK-NEXT: ret469 %ext = sext <16 x i8> %a to <16 x i32>470 %cmp = icmp ne <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>471 %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer472 ret <16 x i32> %sel473}474 475define <8 x i32> @same_sext_used_in_cmp_signed_pred_and_select_v8i32(<8 x i16> %a) {476; CHECK-LABEL: same_sext_used_in_cmp_signed_pred_and_select_v8i32:477; CHECK: ; %bb.0: ; %entry478; CHECK-NEXT: movi.4s v1, #10479; CHECK-NEXT: sshll2.4s v2, v0, #0480; CHECK-NEXT: sshll.4s v0, v0, #0481; CHECK-NEXT: cmgt.4s v3, v0, v1482; CHECK-NEXT: cmgt.4s v1, v2, v1483; CHECK-NEXT: and.16b v1, v1, v2484; CHECK-NEXT: and.16b v0, v3, v0485; CHECK-NEXT: ret486entry:487 %ext = sext <8 x i16> %a to <8 x i32>488 %cmp = icmp sgt <8 x i16> %a, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>489 %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer490 ret <8 x i32> %sel491}492 493define <8 x i32> @same_sext_used_in_cmp_unsigned_pred_and_select_v8i32_from_v8i15(<8 x i15> %a) {494; CHECK-LABEL: same_sext_used_in_cmp_unsigned_pred_and_select_v8i32_from_v8i15:495; CHECK: ; %bb.0:496; CHECK-NEXT: ushll.4s v2, v0, #0497; CHECK-NEXT: ushll2.4s v0, v0, #0498; CHECK-NEXT: movi.4s v1, #10499; CHECK-NEXT: shl.4s v0, v0, #17500; CHECK-NEXT: shl.4s v2, v2, #17501; CHECK-NEXT: sshr.4s v0, v0, #17502; CHECK-NEXT: sshr.4s v2, v2, #17503; CHECK-NEXT: cmge.4s v3, v2, v1504; CHECK-NEXT: cmge.4s v1, v0, v1505; CHECK-NEXT: and.16b v1, v1, v0506; CHECK-NEXT: and.16b v0, v3, v2507; CHECK-NEXT: ret508 %ext = sext <8 x i15> %a to <8 x i32>509 %cmp = icmp sge <8 x i15> %a, <i15 10, i15 10, i15 10, i15 10, i15 10, i15 10, i15 10, i15 10>510 %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer511 ret <8 x i32> %sel512}513 514define <16 x i32> @same_sext_used_in_cmp_unsigned_pred_and_select(<16 x i8> %a) {515; CHECK-LABEL: same_sext_used_in_cmp_unsigned_pred_and_select:516; CHECK: ; %bb.0: ; %entry517; CHECK-NEXT: movi.16b v1, #10518; CHECK-NEXT: sshll.8h v2, v0, #0519; CHECK-NEXT: ext.16b v4, v2, v2, #8520; CHECK-NEXT: cmhi.16b v1, v0, v1521; CHECK-NEXT: sshll2.8h v0, v0, #0522; CHECK-NEXT: sshll.8h v3, v1, #0523; CHECK-NEXT: sshll2.8h v1, v1, #0524; CHECK-NEXT: ext.16b v5, v0, v0, #8525; CHECK-NEXT: ext.16b v6, v3, v3, #8526; CHECK-NEXT: ext.16b v7, v1, v1, #8527; CHECK-NEXT: and.8b v2, v3, v2528; CHECK-NEXT: and.8b v1, v1, v0529; CHECK-NEXT: sshll.4s v0, v2, #0530; CHECK-NEXT: and.8b v3, v7, v5531; CHECK-NEXT: and.8b v4, v6, v4532; CHECK-NEXT: sshll.4s v2, v1, #0533; CHECK-NEXT: sshll.4s v3, v3, #0534; CHECK-NEXT: sshll.4s v1, v4, #0535; CHECK-NEXT: ret536entry:537 %ext = sext <16 x i8> %a to <16 x i32>538 %cmp = icmp ugt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>539 %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer540 ret <16 x i32> %sel541}542 543define <16 x i32> @same_zext_used_in_cmp_signed_pred_and_select_can_convert_to_unsigned_pred(<16 x i8> %a) {544; CHECK-LABEL: same_zext_used_in_cmp_signed_pred_and_select_can_convert_to_unsigned_pred:545; CHECK: ; %bb.0: ; %entry546; CHECK-NEXT: cmge.16b v1, v0, #0547; CHECK-NEXT: ushll.8h v2, v0, #0548; CHECK-NEXT: ushll2.8h v0, v0, #0549; CHECK-NEXT: sshll.8h v3, v1, #0550; CHECK-NEXT: sshll2.8h v1, v1, #0551; CHECK-NEXT: ushll.4s v4, v2, #0552; CHECK-NEXT: ushll.4s v5, v0, #0553; CHECK-NEXT: ushll2.4s v2, v2, #0554; CHECK-NEXT: ushll2.4s v6, v0, #0555; CHECK-NEXT: sshll.4s v0, v3, #0556; CHECK-NEXT: sshll.4s v7, v1, #0557; CHECK-NEXT: sshll2.4s v16, v3, #0558; CHECK-NEXT: sshll2.4s v1, v1, #0559; CHECK-NEXT: and.16b v0, v0, v4560; CHECK-NEXT: and.16b v3, v1, v6561; CHECK-NEXT: and.16b v1, v16, v2562; CHECK-NEXT: and.16b v2, v7, v5563; CHECK-NEXT: ret564entry:565 %ext = zext <16 x i8> %a to <16 x i32>566 %cmp = icmp sgt <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>567 %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer568 ret <16 x i32> %sel569}570 571define void @extension_in_loop_v16i8_to_v16i32(ptr %src, ptr %dst) {572; CHECK-LABEL: extension_in_loop_v16i8_to_v16i32:573; CHECK: ; %bb.0: ; %entry574; CHECK-NEXT: Lloh2:575; CHECK-NEXT: adrp x8, lCPI24_0@PAGE576; CHECK-NEXT: Lloh3:577; CHECK-NEXT: adrp x9, lCPI24_1@PAGE578; CHECK-NEXT: Lloh4:579; CHECK-NEXT: adrp x10, lCPI24_2@PAGE580; CHECK-NEXT: Lloh5:581; CHECK-NEXT: ldr q0, [x8, lCPI24_0@PAGEOFF]582; CHECK-NEXT: Lloh6:583; CHECK-NEXT: adrp x8, lCPI24_3@PAGE584; CHECK-NEXT: Lloh7:585; CHECK-NEXT: ldr q1, [x9, lCPI24_1@PAGEOFF]586; CHECK-NEXT: Lloh8:587; CHECK-NEXT: ldr q2, [x10, lCPI24_2@PAGEOFF]588; CHECK-NEXT: Lloh9:589; CHECK-NEXT: ldr q3, [x8, lCPI24_3@PAGEOFF]590; CHECK-NEXT: mov x8, xzr591; CHECK-NEXT: LBB24_1: ; %loop592; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1593; CHECK-NEXT: ldr q4, [x0, x8]594; CHECK-NEXT: add x8, x8, #16595; CHECK-NEXT: cmp x8, #128596; CHECK-NEXT: cmge.16b v5, v4, #0597; CHECK-NEXT: tbl.16b v7, { v4 }, v0598; CHECK-NEXT: tbl.16b v16, { v4 }, v1599; CHECK-NEXT: tbl.16b v18, { v4 }, v2600; CHECK-NEXT: tbl.16b v4, { v4 }, v3601; CHECK-NEXT: sshll2.8h v6, v5, #0602; CHECK-NEXT: sshll.8h v5, v5, #0603; CHECK-NEXT: sshll2.4s v17, v6, #0604; CHECK-NEXT: sshll.4s v6, v6, #0605; CHECK-NEXT: sshll2.4s v19, v5, #0606; CHECK-NEXT: sshll.4s v5, v5, #0607; CHECK-NEXT: and.16b v7, v17, v7608; CHECK-NEXT: and.16b v6, v6, v16609; CHECK-NEXT: and.16b v16, v19, v18610; CHECK-NEXT: and.16b v4, v5, v4611; CHECK-NEXT: stp q6, q7, [x1, #32]612; CHECK-NEXT: stp q4, q16, [x1], #64613; CHECK-NEXT: b.ne LBB24_1614; CHECK-NEXT: ; %bb.2: ; %exit615; CHECK-NEXT: ret616; CHECK-NEXT: .loh AdrpLdr Lloh6, Lloh9617; CHECK-NEXT: .loh AdrpLdr Lloh4, Lloh8618; CHECK-NEXT: .loh AdrpLdr Lloh3, Lloh7619; CHECK-NEXT: .loh AdrpAdrp Lloh2, Lloh6620; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh5621entry:622 br label %loop623 624loop:625 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]626 %src.gep = getelementptr i8, ptr %src, i64 %iv627 %load = load <16 x i8>, ptr %src.gep628 %cmp = icmp sgt <16 x i8> %load, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>629 %ext = zext <16 x i8> %load to <16 x i32>630 %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer631 %dst.gep = getelementptr i32, ptr %dst, i64 %iv632 store <16 x i32> %sel, ptr %dst.gep633 %iv.next = add nuw i64 %iv, 16634 %ec = icmp eq i64 %iv.next, 128635 br i1 %ec, label %exit, label %loop636 637exit:638 ret void639}640 641define void @extension_in_loop_as_shuffle_v16i8_to_v16i32(ptr %src, ptr %dst) {642; CHECK-LABEL: extension_in_loop_as_shuffle_v16i8_to_v16i32:643; CHECK: ; %bb.0: ; %entry644; CHECK-NEXT: Lloh10:645; CHECK-NEXT: adrp x8, lCPI25_0@PAGE646; CHECK-NEXT: Lloh11:647; CHECK-NEXT: adrp x9, lCPI25_1@PAGE648; CHECK-NEXT: Lloh12:649; CHECK-NEXT: adrp x10, lCPI25_2@PAGE650; CHECK-NEXT: Lloh13:651; CHECK-NEXT: ldr q0, [x8, lCPI25_0@PAGEOFF]652; CHECK-NEXT: Lloh14:653; CHECK-NEXT: adrp x8, lCPI25_3@PAGE654; CHECK-NEXT: Lloh15:655; CHECK-NEXT: ldr q1, [x9, lCPI25_1@PAGEOFF]656; CHECK-NEXT: Lloh16:657; CHECK-NEXT: ldr q2, [x10, lCPI25_2@PAGEOFF]658; CHECK-NEXT: Lloh17:659; CHECK-NEXT: ldr q3, [x8, lCPI25_3@PAGEOFF]660; CHECK-NEXT: mov x8, xzr661; CHECK-NEXT: LBB25_1: ; %loop662; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1663; CHECK-NEXT: ldr q4, [x0, x8]664; CHECK-NEXT: add x8, x8, #16665; CHECK-NEXT: cmp x8, #128666; CHECK-NEXT: cmge.16b v5, v4, #0667; CHECK-NEXT: tbl.16b v7, { v4 }, v0668; CHECK-NEXT: tbl.16b v16, { v4 }, v1669; CHECK-NEXT: tbl.16b v18, { v4 }, v2670; CHECK-NEXT: tbl.16b v4, { v4 }, v3671; CHECK-NEXT: sshll2.8h v6, v5, #0672; CHECK-NEXT: sshll.8h v5, v5, #0673; CHECK-NEXT: sshll2.4s v17, v6, #0674; CHECK-NEXT: sshll.4s v6, v6, #0675; CHECK-NEXT: sshll2.4s v19, v5, #0676; CHECK-NEXT: sshll.4s v5, v5, #0677; CHECK-NEXT: and.16b v7, v17, v7678; CHECK-NEXT: and.16b v6, v6, v16679; CHECK-NEXT: and.16b v16, v19, v18680; CHECK-NEXT: and.16b v4, v5, v4681; CHECK-NEXT: stp q6, q7, [x1, #32]682; CHECK-NEXT: stp q4, q16, [x1], #64683; CHECK-NEXT: b.ne LBB25_1684; CHECK-NEXT: ; %bb.2: ; %exit685; CHECK-NEXT: ret686; CHECK-NEXT: .loh AdrpLdr Lloh14, Lloh17687; CHECK-NEXT: .loh AdrpLdr Lloh12, Lloh16688; CHECK-NEXT: .loh AdrpLdr Lloh11, Lloh15689; CHECK-NEXT: .loh AdrpAdrp Lloh10, Lloh14690; CHECK-NEXT: .loh AdrpLdr Lloh10, Lloh13691entry:692 br label %loop693 694loop:695 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]696 %src.gep = getelementptr i8, ptr %src, i64 %iv697 %load = load <16 x i8>, ptr %src.gep698 %cmp = icmp sgt <16 x i8> %load, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>699 %ext.shuf = shufflevector <16 x i8> %load, <16 x i8> zeroinitializer, <64 x i32> <i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 1, i32 16, i32 16, i32 16, i32 2, i32 16, i32 16, i32 16, i32 3, i32 16, i32 16, i32 16, i32 4, i32 16, i32 16, i32 16, i32 5, i32 16, i32 16, i32 16, i32 6, i32 16, i32 16, i32 16, i32 7, i32 16, i32 16, i32 16, i32 8, i32 16, i32 16, i32 16, i32 9, i32 16, i32 16, i32 16, i32 10, i32 16, i32 16, i32 16, i32 11, i32 16, i32 16, i32 16, i32 12, i32 16, i32 16, i32 16, i32 13, i32 16, i32 16, i32 16, i32 14, i32 16, i32 16, i32 16, i32 15>700 %ext = bitcast <64 x i8> %ext.shuf to <16 x i32>701 %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer702 %dst.gep = getelementptr i32, ptr %dst, i64 %iv703 store <16 x i32> %sel, ptr %dst.gep704 %iv.next = add nuw i64 %iv, 16705 %ec = icmp eq i64 %iv.next, 128706 br i1 %ec, label %exit, label %loop707 708exit:709 ret void710}711 712define void @shuffle_in_loop_is_no_extend_v16i8_to_v16i32(ptr %src, ptr %dst) {713; CHECK-LABEL: shuffle_in_loop_is_no_extend_v16i8_to_v16i32:714; CHECK: ; %bb.0: ; %entry715; CHECK-NEXT: Lloh18:716; CHECK-NEXT: adrp x8, lCPI26_0@PAGE717; CHECK-NEXT: Lloh19:718; CHECK-NEXT: adrp x9, lCPI26_1@PAGE719; CHECK-NEXT: Lloh20:720; CHECK-NEXT: adrp x10, lCPI26_2@PAGE721; CHECK-NEXT: Lloh21:722; CHECK-NEXT: ldr q0, [x8, lCPI26_0@PAGEOFF]723; CHECK-NEXT: Lloh22:724; CHECK-NEXT: adrp x8, lCPI26_3@PAGE725; CHECK-NEXT: Lloh23:726; CHECK-NEXT: ldr q1, [x9, lCPI26_1@PAGEOFF]727; CHECK-NEXT: Lloh24:728; CHECK-NEXT: ldr q2, [x10, lCPI26_2@PAGEOFF]729; CHECK-NEXT: Lloh25:730; CHECK-NEXT: ldr q3, [x8, lCPI26_3@PAGEOFF]731; CHECK-NEXT: mov x8, xzr732; CHECK-NEXT: LBB26_1: ; %loop733; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1734; CHECK-NEXT: ldr q4, [x0, x8]735; CHECK-NEXT: add x8, x8, #16736; CHECK-NEXT: cmp x8, #128737; CHECK-NEXT: cmge.16b v5, v4, #0738; CHECK-NEXT: tbl.16b v7, { v4 }, v0739; CHECK-NEXT: tbl.16b v16, { v4 }, v1740; CHECK-NEXT: tbl.16b v18, { v4 }, v2741; CHECK-NEXT: tbl.16b v4, { v4 }, v3742; CHECK-NEXT: sshll2.8h v6, v5, #0743; CHECK-NEXT: sshll.8h v5, v5, #0744; CHECK-NEXT: sshll2.4s v17, v6, #0745; CHECK-NEXT: sshll.4s v6, v6, #0746; CHECK-NEXT: sshll2.4s v19, v5, #0747; CHECK-NEXT: sshll.4s v5, v5, #0748; CHECK-NEXT: and.16b v7, v17, v7749; CHECK-NEXT: and.16b v6, v6, v16750; CHECK-NEXT: and.16b v16, v19, v18751; CHECK-NEXT: and.16b v4, v5, v4752; CHECK-NEXT: stp q6, q7, [x1, #32]753; CHECK-NEXT: stp q4, q16, [x1], #64754; CHECK-NEXT: b.ne LBB26_1755; CHECK-NEXT: ; %bb.2: ; %exit756; CHECK-NEXT: ret757; CHECK-NEXT: .loh AdrpLdr Lloh22, Lloh25758; CHECK-NEXT: .loh AdrpLdr Lloh20, Lloh24759; CHECK-NEXT: .loh AdrpLdr Lloh19, Lloh23760; CHECK-NEXT: .loh AdrpAdrp Lloh18, Lloh22761; CHECK-NEXT: .loh AdrpLdr Lloh18, Lloh21762entry:763 br label %loop764 765loop:766 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]767 %src.gep = getelementptr i8, ptr %src, i64 %iv768 %load = load <16 x i8>, ptr %src.gep769 %cmp = icmp sgt <16 x i8> %load, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>770 %ext.shuf = shufflevector <16 x i8> %load, <16 x i8> zeroinitializer, <64 x i32> <i32 1, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 1, i32 16, i32 16, i32 16, i32 2, i32 16, i32 16, i32 16, i32 3, i32 16, i32 16, i32 16, i32 4, i32 16, i32 16, i32 16, i32 5, i32 16, i32 16, i32 16, i32 6, i32 16, i32 16, i32 16, i32 7, i32 16, i32 16, i32 16, i32 8, i32 16, i32 16, i32 16, i32 9, i32 16, i32 16, i32 16, i32 10, i32 16, i32 16, i32 16, i32 11, i32 16, i32 16, i32 16, i32 12, i32 16, i32 16, i32 16, i32 13, i32 16, i32 16, i32 16, i32 14, i32 16, i32 16, i32 16, i32 15>771 %ext = bitcast <64 x i8> %ext.shuf to <16 x i32>772 %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer773 %dst.gep = getelementptr i32, ptr %dst, i64 %iv774 store <16 x i32> %sel, ptr %dst.gep775 %iv.next = add nuw i64 %iv, 16776 %ec = icmp eq i64 %iv.next, 128777 br i1 %ec, label %exit, label %loop778 779exit:780 ret void781}782