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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cortex-a53 | FileCheck %s3 4; Test for DAGCombiner optimization: fold (xor (smin(x, C), C)) -> select (x < C), xor (x, C), 05 6define i64 @test_smin_neg_one(i64 %a) {7; CHECK-LABEL: test_smin_neg_one:8; CHECK: // %bb.0:9; CHECK-NEXT: cmn x0, #110; CHECK-NEXT: csinv x0, xzr, x0, ge11; CHECK-NEXT: ret12 %1 = tail call i64 @llvm.smin.i64(i64 %a, i64 -1)13 %retval.0 = xor i64 %1, -114 ret i64 %retval.015}16 17define i64 @test_smin_constant(i64 %a) {18; CHECK-LABEL: test_smin_constant:19; CHECK: // %bb.0:20; CHECK-NEXT: eor x8, x0, #0x821; CHECK-NEXT: cmp x0, #822; CHECK-NEXT: csel x0, x8, xzr, lt23; CHECK-NEXT: ret24 %1 = tail call i64 @llvm.smin.i64(i64 %a, i64 8)25 %retval.0 = xor i64 %1, 826 ret i64 %retval.027}28 29; Test for DAGCombiner optimization: fold (xor (smax(x, C), C)) -> select (x > C), xor (x, C), 030define i64 @test_smax_neg_one(i64 %a) {31; CHECK-LABEL: test_smax_neg_one:32; CHECK: // %bb.0:33; CHECK-NEXT: mvn x8, x034; CHECK-NEXT: bic x0, x8, x0, asr #6335; CHECK-NEXT: ret36 %1 = tail call i64 @llvm.smax.i64(i64 %a, i64 -1)37 %retval.0 = xor i64 %1, -138 ret i64 %retval.039}40 41define i64 @test_smax_constant(i64 %a) {42; CHECK-LABEL: test_smax_constant:43; CHECK: // %bb.0:44; CHECK-NEXT: eor x8, x0, #0x845; CHECK-NEXT: cmp x0, #846; CHECK-NEXT: csel x0, x8, xzr, gt47; CHECK-NEXT: ret48 %1 = tail call i64 @llvm.smax.i64(i64 %a, i64 8)49 %retval.0 = xor i64 %1, 850 ret i64 %retval.051}52 53define i64 @test_umin_neg_one(i64 %a) {54; CHECK-LABEL: test_umin_neg_one:55; CHECK: // %bb.0:56; CHECK-NEXT: mvn x0, x057; CHECK-NEXT: ret58 %1 = tail call i64 @llvm.umin.i64(i64 %a, i64 -1)59 %retval.0 = xor i64 %1, -160 ret i64 %retval.061}62 63define i64 @test_umin_constant(i64 %a) {64; CHECK-LABEL: test_umin_constant:65; CHECK: // %bb.0:66; CHECK-NEXT: eor x8, x0, #0x867; CHECK-NEXT: cmp x0, #868; CHECK-NEXT: csel x0, x8, xzr, lo69; CHECK-NEXT: ret70 %1 = tail call i64 @llvm.umin.i64(i64 %a, i64 8)71 %retval.0 = xor i64 %1, 872 ret i64 %retval.073}74 75define i64 @test_umax_neg_one(i64 %a) {76; CHECK-LABEL: test_umax_neg_one:77; CHECK: // %bb.0:78; CHECK-NEXT: mov x0, xzr79; CHECK-NEXT: ret80 %1 = tail call i64 @llvm.umax.i64(i64 %a, i64 -1)81 %retval.0 = xor i64 %1, -182 ret i64 %retval.083}84 85define i64 @test_umax_constant(i64 %a) {86; CHECK-LABEL: test_umax_constant:87; CHECK: // %bb.0:88; CHECK-NEXT: eor x8, x0, #0x889; CHECK-NEXT: cmp x0, #890; CHECK-NEXT: csel x0, x8, xzr, hi91; CHECK-NEXT: ret92 %1 = tail call i64 @llvm.umax.i64(i64 %a, i64 8)93 %retval.0 = xor i64 %1, 894 ret i64 %retval.095}96 97; Test vector cases98define <4 x i32> @test_smin_vector_neg_one(<4 x i32> %a) {99; CHECK-LABEL: test_smin_vector_neg_one:100; CHECK: // %bb.0:101; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff102; CHECK-NEXT: cmgt v1.4s, v1.4s, v0.4s103; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b104; CHECK-NEXT: ret105 %1 = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)106 %retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>107 ret <4 x i32> %retval.0108}109 110define <4 x i32> @test_smin_vector_constant(<4 x i32> %a) {111; CHECK-LABEL: test_smin_vector_constant:112; CHECK: // %bb.0:113; CHECK-NEXT: movi v1.4s, #8114; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s115; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b116; CHECK-NEXT: ret117 %1 = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)118 %retval.0 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>119 ret <4 x i32> %retval.0120}121 122define <4 x i32> @test_smax_vector_neg_one(<4 x i32> %a) {123; CHECK-LABEL: test_smax_vector_neg_one:124; CHECK: // %bb.0:125; CHECK-NEXT: cmge v1.4s, v0.4s, #0126; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b127; CHECK-NEXT: ret128 %1 = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)129 %retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>130 ret <4 x i32> %retval.0131}132 133define <4 x i32> @test_smax_vector_constant(<4 x i32> %a) {134; CHECK-LABEL: test_smax_vector_constant:135; CHECK: // %bb.0:136; CHECK-NEXT: movi v1.4s, #8137; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s138; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b139; CHECK-NEXT: ret140 %1 = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)141 %retval.0 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>142 ret <4 x i32> %retval.0143}144 145define <4 x i32> @test_umin_vector_neg_one(<4 x i32> %a) {146; CHECK-LABEL: test_umin_vector_neg_one:147; CHECK: // %bb.0:148; CHECK-NEXT: mvn v0.16b, v0.16b149; CHECK-NEXT: ret150 %1 = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)151 %retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>152 ret <4 x i32> %retval.0153}154 155define <4 x i32> @test_umin_vector_constant(<4 x i32> %a) {156; CHECK-LABEL: test_umin_vector_constant:157; CHECK: // %bb.0:158; CHECK-NEXT: movi v1.4s, #8159; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s160; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b161; CHECK-NEXT: ret162 %1 = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)163 %retval.0 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>164 ret <4 x i32> %retval.0165}166 167define <4 x i32> @test_umax_vector_neg_one(<4 x i32> %a) {168; CHECK-LABEL: test_umax_vector_neg_one:169; CHECK: // %bb.0:170; CHECK-NEXT: movi v0.2d, #0000000000000000171; CHECK-NEXT: ret172 %1 = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)173 %retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>174 ret <4 x i32> %retval.0175}176 177define <4 x i32> @test_umax_vector_constant(<4 x i32> %a) {178; CHECK-LABEL: test_umax_vector_constant:179; CHECK: // %bb.0:180; CHECK-NEXT: movi v1.4s, #8181; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s182; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b183; CHECK-NEXT: ret184 %1 = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)185 %retval.0 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>186 ret <4 x i32> %retval.0187}188 189declare i64 @llvm.smin.i64(i64, i64)190declare i64 @llvm.smax.i64(i64, i64)191declare i64 @llvm.umin.i64(i64, i64)192declare i64 @llvm.umax.i64(i64, i64)193declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)194declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)195declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)196declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>)197