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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s3 4define i32 @PR39657(ptr %p, i64 %x) {5; CHECK-LABEL: PR39657:6; CHECK: // %bb.0:7; CHECK-NEXT: mvn x8, x18; CHECK-NEXT: ldr w0, [x0, x8, lsl #2]9; CHECK-NEXT: ret10 %sh = shl i64 %x, 211 %mul = xor i64 %sh, -412 %add.ptr = getelementptr inbounds i8, ptr %p, i64 %mul13 %load = load i32, ptr %add.ptr, align 414 ret i32 %load15}16 17define i32 @add_of_not(i32 %x, i32 %y) {18; CHECK-LABEL: add_of_not:19; CHECK: // %bb.0:20; CHECK-NEXT: mvn w8, w121; CHECK-NEXT: add w0, w8, w022; CHECK-NEXT: ret23 %t0 = sub i32 %x, %y24 %r = add i32 %t0, -125 ret i32 %r26}27 28define i32 @add_of_not_decrement(i32 %x, i32 %y) {29; CHECK-LABEL: add_of_not_decrement:30; CHECK: // %bb.0:31; CHECK-NEXT: mvn w8, w132; CHECK-NEXT: add w0, w8, w033; CHECK-NEXT: ret34 %t0 = sub i32 %x, %y35 %r = sub i32 %t0, 136 ret i32 %r37}38 39define <4 x i32> @vec_add_of_not(<4 x i32> %x, <4 x i32> %y) {40; CHECK-LABEL: vec_add_of_not:41; CHECK: // %bb.0:42; CHECK-NEXT: mvn v1.16b, v1.16b43; CHECK-NEXT: add v0.4s, v1.4s, v0.4s44; CHECK-NEXT: ret45 %t0 = sub <4 x i32> %x, %y46 %r = add <4 x i32> %t0, <i32 -1, i32 -1, i32 -1, i32 -1>47 ret <4 x i32> %r48}49 50define <4 x i32> @vec_add_of_not_decrement(<4 x i32> %x, <4 x i32> %y) {51; CHECK-LABEL: vec_add_of_not_decrement:52; CHECK: // %bb.0:53; CHECK-NEXT: mvn v1.16b, v1.16b54; CHECK-NEXT: add v0.4s, v0.4s, v1.4s55; CHECK-NEXT: ret56 %t0 = sub <4 x i32> %x, %y57 %r = sub <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>58 ret <4 x i32> %r59}60 61define <4 x i32> @vec_add_of_not_with_undef(<4 x i32> %x, <4 x i32> %y) {62; CHECK-LABEL: vec_add_of_not_with_undef:63; CHECK: // %bb.0:64; CHECK-NEXT: mvn v1.16b, v1.16b65; CHECK-NEXT: add v0.4s, v1.4s, v0.4s66; CHECK-NEXT: ret67 %t0 = sub <4 x i32> %x, %y68 %r = add <4 x i32> %t0, <i32 -1, i32 undef, i32 -1, i32 -1>69 ret <4 x i32> %r70}71 72define <4 x i32> @vec_add_of_not_with_undef_decrement(<4 x i32> %x, <4 x i32> %y) {73; CHECK-LABEL: vec_add_of_not_with_undef_decrement:74; CHECK: // %bb.0:75; CHECK-NEXT: mvn v1.16b, v1.16b76; CHECK-NEXT: add v0.4s, v0.4s, v1.4s77; CHECK-NEXT: ret78 %t0 = sub <4 x i32> %x, %y79 %r = sub <4 x i32> %t0, <i32 1, i32 undef, i32 1, i32 1>80 ret <4 x i32> %r81}82