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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mattr=+sve2 < %s | FileCheck %s -check-prefixes=CHECK,SVE3; RUN: llc -mattr=+sve2p2 < %s | FileCheck %s -check-prefix CHECK-2p24; RUN: llc -mattr=+sve,+sme2p2 < %s | FileCheck %s -check-prefix CHECK-2p25 6; RUN: llc -mattr=+sme2 -force-streaming < %s | FileCheck %s -check-prefixes=CHECK,STREAMING-SVE7; RUN: llc -mattr=+sme2p2 -force-streaming < %s | FileCheck %s -check-prefix CHECK-2p28; RUN: llc -mattr=+sme,+sve2p2 -force-streaming < %s | FileCheck %s -check-prefix CHECK-2p29 10target triple = "aarch64-linux"11 12define <vscale x 4 x float> @test_svcvtlt_f32_f16_x_1(<vscale x 4 x i1> %pg, <vscale x 8 x half> %x) {13; CHECK-LABEL: test_svcvtlt_f32_f16_x_1:14; CHECK: // %bb.0: // %entry15; CHECK-NEXT: fcvtlt z0.s, p0/m, z0.h16; CHECK-NEXT: ret17;18; CHECK-2p2-LABEL: test_svcvtlt_f32_f16_x_1:19; CHECK-2p2: // %bb.0: // %entry20; CHECK-2p2-NEXT: fcvtlt z0.s, p0/z, z0.h21; CHECK-2p2-NEXT: ret22entry:23 %0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> poison, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)24 ret <vscale x 4 x float> %025}26 27define <vscale x 4 x float> @test_svcvtlt_f32_f16_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 8 x half> %x) {28; CHECK-LABEL: test_svcvtlt_f32_f16_x_2:29; CHECK: // %bb.0: // %entry30; CHECK-NEXT: fcvtlt z0.s, p0/m, z1.h31; CHECK-NEXT: ret32;33; CHECK-2p2-LABEL: test_svcvtlt_f32_f16_x_2:34; CHECK-2p2: // %bb.0: // %entry35; CHECK-2p2-NEXT: fcvtlt z0.s, p0/z, z1.h36; CHECK-2p2-NEXT: ret37entry:38 %0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> poison, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)39 ret <vscale x 4 x float> %040}41 42define <vscale x 4 x float> @test_svcvtlt_f32_f16_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 8 x half> %x) {43; SVE-LABEL: test_svcvtlt_f32_f16_z:44; SVE: // %bb.0: // %entry45; SVE-NEXT: movi v0.2d, #000000000000000046; SVE-NEXT: fcvtlt z0.s, p0/m, z1.h47; SVE-NEXT: ret48;49; CHECK-2p2-LABEL: test_svcvtlt_f32_f16_z:50; CHECK-2p2: // %bb.0: // %entry51; CHECK-2p2-NEXT: fcvtlt z0.s, p0/z, z1.h52; CHECK-2p2-NEXT: ret53;54; STREAMING-SVE-LABEL: test_svcvtlt_f32_f16_z:55; STREAMING-SVE: // %bb.0: // %entry56; STREAMING-SVE-NEXT: mov z0.s, #0 // =0x057; STREAMING-SVE-NEXT: fcvtlt z0.s, p0/m, z1.h58; STREAMING-SVE-NEXT: ret59entry:60 %0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)61 ret <vscale x 4 x float> %062}63 64define <vscale x 2 x double> @test_svcvtlt_f64_f32_x_1(<vscale x 2 x i1> %pg, <vscale x 4 x float> %x) {65; CHECK-LABEL: test_svcvtlt_f64_f32_x_1:66; CHECK: // %bb.0: // %entry67; CHECK-NEXT: fcvtlt z0.d, p0/m, z0.s68; CHECK-NEXT: ret69;70; CHECK-2p2-LABEL: test_svcvtlt_f64_f32_x_1:71; CHECK-2p2: // %bb.0: // %entry72; CHECK-2p2-NEXT: fcvtlt z0.d, p0/z, z0.s73; CHECK-2p2-NEXT: ret74entry:75 %0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> poison, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)76 ret <vscale x 2 x double> %077}78 79define <vscale x 2 x double> @test_svcvtlt_f64_f32_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 4 x float> %x) {80; CHECK-LABEL: test_svcvtlt_f64_f32_x_2:81; CHECK: // %bb.0: // %entry82; CHECK-NEXT: fcvtlt z0.d, p0/m, z1.s83; CHECK-NEXT: ret84;85; CHECK-2p2-LABEL: test_svcvtlt_f64_f32_x_2:86; CHECK-2p2: // %bb.0: // %entry87; CHECK-2p2-NEXT: fcvtlt z0.d, p0/z, z1.s88; CHECK-2p2-NEXT: ret89entry:90 %0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> poison, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)91 ret <vscale x 2 x double> %092}93 94define <vscale x 2 x double> @test_svcvtlt_f64_f32_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 4 x float> %x) {95; SVE-LABEL: test_svcvtlt_f64_f32_z:96; SVE: // %bb.0: // %entry97; SVE-NEXT: movi v0.2d, #000000000000000098; SVE-NEXT: fcvtlt z0.d, p0/m, z1.s99; SVE-NEXT: ret100;101; CHECK-2p2-LABEL: test_svcvtlt_f64_f32_z:102; CHECK-2p2: // %bb.0: // %entry103; CHECK-2p2-NEXT: fcvtlt z0.d, p0/z, z1.s104; CHECK-2p2-NEXT: ret105;106; STREAMING-SVE-LABEL: test_svcvtlt_f64_f32_z:107; STREAMING-SVE: // %bb.0: // %entry108; STREAMING-SVE-NEXT: mov z0.d, #0 // =0x0109; STREAMING-SVE-NEXT: fcvtlt z0.d, p0/m, z1.s110; STREAMING-SVE-NEXT: ret111entry:112 %0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)113 ret <vscale x 2 x double> %0114}115 116define <vscale x 4 x float> @test_svcvtx_f32_f64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x double> %x) {117; CHECK-LABEL: test_svcvtx_f32_f64_x_1:118; CHECK: // %bb.0: // %entry119; CHECK-NEXT: fcvtx z0.s, p0/m, z0.d120; CHECK-NEXT: ret121;122; CHECK-2p2-LABEL: test_svcvtx_f32_f64_x_1:123; CHECK-2p2: // %bb.0: // %entry124; CHECK-2p2-NEXT: fcvtx z0.s, p0/z, z0.d125; CHECK-2p2-NEXT: ret126entry:127 %0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)128 ret <vscale x 4 x float> %0129}130 131define <vscale x 4 x float> @test_svcvtx_f32_f64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {132; CHECK-LABEL: test_svcvtx_f32_f64_x_2:133; CHECK: // %bb.0: // %entry134; CHECK-NEXT: fcvtx z0.s, p0/m, z1.d135; CHECK-NEXT: ret136;137; CHECK-2p2-LABEL: test_svcvtx_f32_f64_x_2:138; CHECK-2p2: // %bb.0: // %entry139; CHECK-2p2-NEXT: fcvtx z0.s, p0/z, z1.d140; CHECK-2p2-NEXT: ret141entry:142 %0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)143 ret <vscale x 4 x float> %0144}145 146define <vscale x 4 x float> @test_svcvtx_f32_f64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {147; SVE-LABEL: test_svcvtx_f32_f64_z:148; SVE: // %bb.0: // %entry149; SVE-NEXT: movi v0.2d, #0000000000000000150; SVE-NEXT: fcvtx z0.s, p0/m, z1.d151; SVE-NEXT: ret152;153; CHECK-2p2-LABEL: test_svcvtx_f32_f64_z:154; CHECK-2p2: // %bb.0: // %entry155; CHECK-2p2-NEXT: fcvtx z0.s, p0/z, z1.d156; CHECK-2p2-NEXT: ret157;158; STREAMING-SVE-LABEL: test_svcvtx_f32_f64_z:159; STREAMING-SVE: // %bb.0: // %entry160; STREAMING-SVE-NEXT: mov z0.s, #0 // =0x0161; STREAMING-SVE-NEXT: fcvtx z0.s, p0/m, z1.d162; STREAMING-SVE-NEXT: ret163entry:164 %0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)165 ret <vscale x 4 x float> %0166}167 168define <vscale x 4 x float> @test_svcvtlt_f32_f16_ptrue_u(double %z0, <vscale x 8 x half> %x) {169; CHECK-LABEL: test_svcvtlt_f32_f16_ptrue_u:170; CHECK: // %bb.0: // %entry171; CHECK-NEXT: ptrue p0.s172; CHECK-NEXT: fcvtlt z0.s, p0/m, z1.h173; CHECK-NEXT: ret174;175; CHECK-2p2-LABEL: test_svcvtlt_f32_f16_ptrue_u:176; CHECK-2p2: // %bb.0: // %entry177; CHECK-2p2-NEXT: ptrue p0.s178; CHECK-2p2-NEXT: fcvtlt z0.s, p0/z, z1.h179; CHECK-2p2-NEXT: ret180entry:181 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)182 %0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> poison, <vscale x 4 x i1> %pg, <vscale x 8 x half> %x)183 ret <vscale x 4 x float> %0184}185 186define <vscale x 4 x float> @test_svcvtlt_f32_f16_ptrue(double %z0, <vscale x 4 x float> %x, <vscale x 8 x half> %y) {187; CHECK-LABEL: test_svcvtlt_f32_f16_ptrue:188; CHECK: // %bb.0: // %entry189; CHECK-NEXT: mov z0.d, z1.d190; CHECK-NEXT: ptrue p0.s191; CHECK-NEXT: fcvtlt z0.s, p0/m, z2.h192; CHECK-NEXT: ret193;194; CHECK-2p2-LABEL: test_svcvtlt_f32_f16_ptrue:195; CHECK-2p2: // %bb.0: // %entry196; CHECK-2p2-NEXT: ptrue p0.s197; CHECK-2p2-NEXT: fcvtlt z0.s, p0/z, z2.h198; CHECK-2p2-NEXT: ret199entry:200 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)201 %0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> %x, <vscale x 4 x i1> %pg, <vscale x 8 x half> %y)202 ret <vscale x 4 x float> %0203}204 205define <vscale x 2 x double> @test_svcvtlt_f64_f32_ptrue_u(double %z0, <vscale x 4 x float> %x) {206; CHECK-LABEL: test_svcvtlt_f64_f32_ptrue_u:207; CHECK: // %bb.0: // %entry208; CHECK-NEXT: ptrue p0.d209; CHECK-NEXT: fcvtlt z0.d, p0/m, z1.s210; CHECK-NEXT: ret211;212; CHECK-2p2-LABEL: test_svcvtlt_f64_f32_ptrue_u:213; CHECK-2p2: // %bb.0: // %entry214; CHECK-2p2-NEXT: ptrue p0.d215; CHECK-2p2-NEXT: fcvtlt z0.d, p0/z, z1.s216; CHECK-2p2-NEXT: ret217entry:218 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)219 %0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> poison, <vscale x 2 x i1> %pg, <vscale x 4 x float> %x)220 ret <vscale x 2 x double> %0221}222 223define <vscale x 2 x double> @test_svcvtlt_f64_f32_ptrue(double %z0, <vscale x 2 x double> %x, <vscale x 4 x float> %y) {224; CHECK-LABEL: test_svcvtlt_f64_f32_ptrue:225; CHECK: // %bb.0: // %entry226; CHECK-NEXT: mov z0.d, z1.d227; CHECK-NEXT: ptrue p0.d228; CHECK-NEXT: fcvtlt z0.d, p0/m, z2.s229; CHECK-NEXT: ret230;231; CHECK-2p2-LABEL: test_svcvtlt_f64_f32_ptrue:232; CHECK-2p2: // %bb.0: // %entry233; CHECK-2p2-NEXT: ptrue p0.d234; CHECK-2p2-NEXT: fcvtlt z0.d, p0/z, z2.s235; CHECK-2p2-NEXT: ret236entry:237 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)238 %0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> %x, <vscale x 2 x i1> %pg, <vscale x 4 x float> %y)239 ret <vscale x 2 x double> %0240}241 242define <vscale x 4 x float> @test_svcvtx_f32_f64_ptrue_u(double %z0, <vscale x 2 x double> %x) {243; CHECK-LABEL: test_svcvtx_f32_f64_ptrue_u:244; CHECK: // %bb.0: // %entry245; CHECK-NEXT: ptrue p0.d246; CHECK-NEXT: fcvtx z0.s, p0/m, z1.d247; CHECK-NEXT: ret248;249; CHECK-2p2-LABEL: test_svcvtx_f32_f64_ptrue_u:250; CHECK-2p2: // %bb.0: // %entry251; CHECK-2p2-NEXT: ptrue p0.d252; CHECK-2p2-NEXT: fcvtx z0.s, p0/z, z1.d253; CHECK-2p2-NEXT: ret254entry:255 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)256 %0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)257 ret <vscale x 4 x float> %0258}259 260define <vscale x 4 x float> @test_svcvtx_f32_f64_ptrue(double %z0, <vscale x 4 x float> %x, <vscale x 2 x double> %y) {261; CHECK-LABEL: test_svcvtx_f32_f64_ptrue:262; CHECK: // %bb.0: // %entry263; CHECK-NEXT: mov z0.d, z1.d264; CHECK-NEXT: ptrue p0.d265; CHECK-NEXT: fcvtx z0.s, p0/m, z2.d266; CHECK-NEXT: ret267;268; CHECK-2p2-LABEL: test_svcvtx_f32_f64_ptrue:269; CHECK-2p2: // %bb.0: // %entry270; CHECK-2p2-NEXT: ptrue p0.d271; CHECK-2p2-NEXT: fcvtx z0.s, p0/z, z2.d272; CHECK-2p2-NEXT: ret273entry:274 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)275 %0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> %x, <vscale x 2 x i1> %pg, <vscale x 2 x double> %y)276 ret <vscale x 4 x float> %0277}278