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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-none-eabi -o - %s | FileCheck %s3 4define <2 x i64> @v2i64_02(<4 x i32> %a, <4 x i32> %b) {5; CHECK-LABEL: v2i64_02:6; CHECK: // %bb.0:7; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #88; CHECK-NEXT: zip1 v0.2s, v0.2s, v1.2s9; CHECK-NEXT: ushll v0.2d, v0.2s, #010; CHECK-NEXT: ret11 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <2 x i32> <i32 0, i32 2>12 %d = zext <2 x i32> %c to <2 x i64>13 ret <2 x i64> %d14}15 16define <2 x i64> @v2i64_13(<4 x i32> %a, <4 x i32> %b) {17; CHECK-LABEL: v2i64_13:18; CHECK: // %bb.0:19; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #820; CHECK-NEXT: zip2 v0.2s, v0.2s, v1.2s21; CHECK-NEXT: ushll v0.2d, v0.2s, #022; CHECK-NEXT: ret23 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <2 x i32> <i32 1, i32 3>24 %d = zext <2 x i32> %c to <2 x i64>25 ret <2 x i64> %d26}27 28define <2 x i64> @v2i64_04812(<4 x i32> %a, <4 x i32> %b) {29; CHECK-LABEL: v2i64_04812:30; CHECK: // %bb.0:31; CHECK-NEXT: zip1 v0.2s, v0.2s, v1.2s32; CHECK-NEXT: ushll v0.2d, v0.2s, #033; CHECK-NEXT: ret34 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <2 x i32> <i32 0, i32 4>35 %d = zext <2 x i32> %c to <2 x i64>36 ret <2 x i64> %d37}38 39define <2 x i64> @v2i64_15913(<4 x i32> %a, <4 x i32> %b) {40; CHECK-LABEL: v2i64_15913:41; CHECK: // %bb.0:42; CHECK-NEXT: zip2 v0.2s, v0.2s, v1.2s43; CHECK-NEXT: ushll v0.2d, v0.2s, #044; CHECK-NEXT: ret45 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <2 x i32> <i32 1, i32 5>46 %d = zext <2 x i32> %c to <2 x i64>47 ret <2 x i64> %d48}49 50define <2 x i64> @v2i64_261014(<4 x i32> %a, <4 x i32> %b) {51; CHECK-LABEL: v2i64_261014:52; CHECK: // %bb.0:53; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #854; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #855; CHECK-NEXT: zip1 v0.2s, v0.2s, v1.2s56; CHECK-NEXT: ushll v0.2d, v0.2s, #057; CHECK-NEXT: ret58 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <2 x i32> <i32 2, i32 6>59 %d = zext <2 x i32> %c to <2 x i64>60 ret <2 x i64> %d61}62 63define <2 x i64> @v2i64_37(<4 x i32> %a, <4 x i32> %b) {64; CHECK-LABEL: v2i64_37:65; CHECK: // %bb.0:66; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #867; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #868; CHECK-NEXT: zip2 v0.2s, v0.2s, v1.2s69; CHECK-NEXT: ushll v0.2d, v0.2s, #070; CHECK-NEXT: ret71 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <2 x i32> <i32 3, i32 7>72 %d = zext <2 x i32> %c to <2 x i64>73 ret <2 x i64> %d74}75 76define <4 x i64> @v2i64_i16_04812(<16 x i16> %a) {77; CHECK-LABEL: v2i64_i16_04812:78; CHECK: // %bb.0:79; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff80; CHECK-NEXT: uzp1 v0.4s, v0.4s, v1.4s81; CHECK-NEXT: and v0.16b, v0.16b, v2.16b82; CHECK-NEXT: ushll2 v1.2d, v0.4s, #083; CHECK-NEXT: ushll v0.2d, v0.2s, #084; CHECK-NEXT: ret85 %s1 = shufflevector <16 x i16> %a, <16 x i16> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>86 %z1 = zext <4 x i16> %s1 to <4 x i64>87 ret <4 x i64> %z188}89 90define <4 x i64> @v2i64_i16_15913(<16 x i16> %a) {91; CHECK-LABEL: v2i64_i16_15913:92; CHECK: // %bb.0:93; CHECK-NEXT: movi v2.2d, #0x0000000000ffff94; CHECK-NEXT: ushr v0.2d, v0.2d, #1695; CHECK-NEXT: ushr v1.2d, v1.2d, #1696; CHECK-NEXT: and v0.16b, v0.16b, v2.16b97; CHECK-NEXT: and v1.16b, v1.16b, v2.16b98; CHECK-NEXT: ret99 %s1 = shufflevector <16 x i16> %a, <16 x i16> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>100 %z1 = zext <4 x i16> %s1 to <4 x i64>101 ret <4 x i64> %z1102}103 104define <4 x i64> @v2i64_i16_261014(<16 x i16> %a) {105; CHECK-LABEL: v2i64_i16_261014:106; CHECK: // %bb.0:107; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff108; CHECK-NEXT: uzp2 v0.4s, v0.4s, v1.4s109; CHECK-NEXT: and v0.16b, v0.16b, v2.16b110; CHECK-NEXT: ushll2 v1.2d, v0.4s, #0111; CHECK-NEXT: ushll v0.2d, v0.2s, #0112; CHECK-NEXT: ret113 %s1 = shufflevector <16 x i16> %a, <16 x i16> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>114 %z1 = zext <4 x i16> %s1 to <4 x i64>115 ret <4 x i64> %z1116}117 118define <4 x i64> @v2i64_i16_371115(<16 x i16> %a) {119; CHECK-LABEL: v2i64_i16_371115:120; CHECK: // %bb.0:121; CHECK-NEXT: ushr v0.2d, v0.2d, #48122; CHECK-NEXT: ushr v1.2d, v1.2d, #48123; CHECK-NEXT: ret124 %s1 = shufflevector <16 x i16> %a, <16 x i16> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>125 %z1 = zext <4 x i16> %s1 to <4 x i64>126 ret <4 x i64> %z1127}128 129 130define <4 x i32> @v4i32_0246(<8 x i16> %a, <8 x i16> %b) {131; CHECK-LABEL: v4i32_0246:132; CHECK: // %bb.0:133; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff134; CHECK-NEXT: and v0.16b, v0.16b, v1.16b135; CHECK-NEXT: ret136 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>137 %d = zext <4 x i16> %c to <4 x i32>138 ret <4 x i32> %d139}140 141define <4 x i32> @v4i32_1357(<8 x i16> %a, <8 x i16> %b) {142; CHECK-LABEL: v4i32_1357:143; CHECK: // %bb.0:144; CHECK-NEXT: ushr v0.4s, v0.4s, #16145; CHECK-NEXT: ret146 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>147 %d = zext <4 x i16> %c to <4 x i32>148 ret <4 x i32> %d149}150 151define <4 x i32> @v4i32_04812(<8 x i16> %a, <8 x i16> %b) {152; CHECK-LABEL: v4i32_04812:153; CHECK: // %bb.0:154; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff155; CHECK-NEXT: uzp1 v0.4s, v0.4s, v1.4s156; CHECK-NEXT: and v0.16b, v0.16b, v2.16b157; CHECK-NEXT: ret158 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <4 x i32> <i32 0, i32 4, i32 8, i32 12>159 %d = zext <4 x i16> %c to <4 x i32>160 ret <4 x i32> %d161}162 163define <4 x i32> @v4i32_15913(<8 x i16> %a, <8 x i16> %b) {164; CHECK-LABEL: v4i32_15913:165; CHECK: // %bb.0:166; CHECK-NEXT: uzp1 v0.4s, v0.4s, v1.4s167; CHECK-NEXT: ushr v0.4s, v0.4s, #16168; CHECK-NEXT: ret169 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <4 x i32> <i32 1, i32 5, i32 9, i32 13>170 %d = zext <4 x i16> %c to <4 x i32>171 ret <4 x i32> %d172}173 174define <4 x i32> @v4i32_261014(<8 x i16> %a, <8 x i16> %b) {175; CHECK-LABEL: v4i32_261014:176; CHECK: // %bb.0:177; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff178; CHECK-NEXT: uzp2 v0.4s, v0.4s, v1.4s179; CHECK-NEXT: and v0.16b, v0.16b, v2.16b180; CHECK-NEXT: ret181 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <4 x i32> <i32 2, i32 6, i32 10, i32 14>182 %d = zext <4 x i16> %c to <4 x i32>183 ret <4 x i32> %d184}185 186define <4 x i32> @v4i32_371115(<8 x i16> %a, <8 x i16> %b) {187; CHECK-LABEL: v4i32_371115:188; CHECK: // %bb.0:189; CHECK-NEXT: uzp2 v0.4s, v0.4s, v1.4s190; CHECK-NEXT: ushr v0.4s, v0.4s, #16191; CHECK-NEXT: ret192 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <4 x i32> <i32 3, i32 7, i32 11, i32 15>193 %d = zext <4 x i16> %c to <4 x i32>194 ret <4 x i32> %d195}196 197 198define <8 x i16> @v8i16_0246(<16 x i8> %a, <16 x i8> %b) {199; CHECK-LABEL: v8i16_0246:200; CHECK: // %bb.0:201; CHECK-NEXT: bic v0.8h, #255, lsl #8202; CHECK-NEXT: ret203 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>204 %d = zext <8 x i8> %c to <8 x i16>205 ret <8 x i16> %d206}207 208define <8 x i16> @v8i16_1357(<16 x i8> %a, <16 x i8> %b) {209; CHECK-LABEL: v8i16_1357:210; CHECK: // %bb.0:211; CHECK-NEXT: ushr v0.8h, v0.8h, #8212; CHECK-NEXT: ret213 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>214 %d = zext <8 x i8> %c to <8 x i16>215 ret <8 x i16> %d216}217 218define <8 x i16> @v8i16_04812(<16 x i8> %a, <16 x i8> %b) {219; CHECK-LABEL: v8i16_04812:220; CHECK: // %bb.0:221; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h222; CHECK-NEXT: bic v0.8h, #255, lsl #8223; CHECK-NEXT: ret224 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>225 %d = zext <8 x i8> %c to <8 x i16>226 ret <8 x i16> %d227}228 229define <8 x i16> @v8i16_15913(<16 x i8> %a, <16 x i8> %b) {230; CHECK-LABEL: v8i16_15913:231; CHECK: // %bb.0:232; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h233; CHECK-NEXT: ushr v0.8h, v0.8h, #8234; CHECK-NEXT: ret235 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>236 %d = zext <8 x i8> %c to <8 x i16>237 ret <8 x i16> %d238}239 240define <8 x i16> @v8i16_261014(<16 x i8> %a, <16 x i8> %b) {241; CHECK-LABEL: v8i16_261014:242; CHECK: // %bb.0:243; CHECK-NEXT: uzp2 v0.8h, v0.8h, v1.8h244; CHECK-NEXT: bic v0.8h, #255, lsl #8245; CHECK-NEXT: ret246 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>247 %d = zext <8 x i8> %c to <8 x i16>248 ret <8 x i16> %d249}250 251define <8 x i16> @v8i16_371115(<16 x i8> %a, <16 x i8> %b) {252; CHECK-LABEL: v8i16_371115:253; CHECK: // %bb.0:254; CHECK-NEXT: uzp2 v0.8h, v0.8h, v1.8h255; CHECK-NEXT: ushr v0.8h, v0.8h, #8256; CHECK-NEXT: ret257 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>258 %d = zext <8 x i8> %c to <8 x i16>259 ret <8 x i16> %d260}261 262 263define <8 x i32> @v8i32_0246(<16 x i8> %a, <16 x i8> %b) {264; CHECK-LABEL: v8i32_0246:265; CHECK: // %bb.0:266; CHECK-NEXT: bic v0.8h, #255, lsl #8267; CHECK-NEXT: ushll2 v1.4s, v0.8h, #0268; CHECK-NEXT: ushll v0.4s, v0.4h, #0269; CHECK-NEXT: ret270 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>271 %d = zext <8 x i8> %c to <8 x i32>272 ret <8 x i32> %d273}274 275define <8 x i32> @v8i32_1357(<16 x i8> %a, <16 x i8> %b) {276; CHECK-LABEL: v8i32_1357:277; CHECK: // %bb.0:278; CHECK-NEXT: ushr v0.8h, v0.8h, #8279; CHECK-NEXT: ushll2 v1.4s, v0.8h, #0280; CHECK-NEXT: ushll v0.4s, v0.4h, #0281; CHECK-NEXT: ret282 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>283 %d = zext <8 x i8> %c to <8 x i32>284 ret <8 x i32> %d285}286 287define <8 x i32> @v8i32_04812(<16 x i8> %a, <16 x i8> %b) {288; CHECK-LABEL: v8i32_04812:289; CHECK: // %bb.0:290; CHECK-NEXT: movi v2.2d, #0x0000ff000000ff291; CHECK-NEXT: and v0.16b, v0.16b, v2.16b292; CHECK-NEXT: and v1.16b, v1.16b, v2.16b293; CHECK-NEXT: ret294 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>295 %d = zext <8 x i8> %c to <8 x i32>296 ret <8 x i32> %d297}298 299define <8 x i32> @v8i32_15913(<16 x i8> %a, <16 x i8> %b) {300; CHECK-LABEL: v8i32_15913:301; CHECK: // %bb.0:302; CHECK-NEXT: movi v2.2d, #0x0000ff000000ff303; CHECK-NEXT: ushr v0.4s, v0.4s, #8304; CHECK-NEXT: ushr v1.4s, v1.4s, #8305; CHECK-NEXT: and v0.16b, v0.16b, v2.16b306; CHECK-NEXT: and v1.16b, v1.16b, v2.16b307; CHECK-NEXT: ret308 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>309 %d = zext <8 x i8> %c to <8 x i32>310 ret <8 x i32> %d311}312 313define <8 x i32> @v8i32_261014(<16 x i8> %a, <16 x i8> %b) {314; CHECK-LABEL: v8i32_261014:315; CHECK: // %bb.0:316; CHECK-NEXT: ushr v0.4s, v0.4s, #16317; CHECK-NEXT: ushr v1.4s, v1.4s, #16318; CHECK-NEXT: bic v0.4s, #255, lsl #8319; CHECK-NEXT: bic v1.4s, #255, lsl #8320; CHECK-NEXT: ret321 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>322 %d = zext <8 x i8> %c to <8 x i32>323 ret <8 x i32> %d324}325 326define <8 x i32> @v8i32_371115(<16 x i8> %a, <16 x i8> %b) {327; CHECK-LABEL: v8i32_371115:328; CHECK: // %bb.0:329; CHECK-NEXT: ushr v0.4s, v0.4s, #24330; CHECK-NEXT: ushr v1.4s, v1.4s, #24331; CHECK-NEXT: ret332 %c = shufflevector <16 x i8> %a, <16 x i8> %b, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>333 %d = zext <8 x i8> %c to <8 x i32>334 ret <8 x i32> %d335}336 337 338define <8 x i64> @zext_add(<32 x i16> %l) {339; CHECK-LABEL: zext_add:340; CHECK: // %bb.0:341; CHECK-NEXT: movi v4.2d, #0x00ffff0000ffff342; CHECK-NEXT: uzp1 v5.4s, v0.4s, v1.4s343; CHECK-NEXT: uzp2 v0.4s, v0.4s, v1.4s344; CHECK-NEXT: uzp1 v1.4s, v2.4s, v3.4s345; CHECK-NEXT: uzp2 v2.4s, v2.4s, v3.4s346; CHECK-NEXT: and v3.16b, v5.16b, v4.16b347; CHECK-NEXT: and v6.16b, v0.16b, v4.16b348; CHECK-NEXT: and v7.16b, v1.16b, v4.16b349; CHECK-NEXT: and v4.16b, v2.16b, v4.16b350; CHECK-NEXT: usra v3.4s, v5.4s, #16351; CHECK-NEXT: usra v6.4s, v0.4s, #16352; CHECK-NEXT: usra v7.4s, v1.4s, #16353; CHECK-NEXT: usra v4.4s, v2.4s, #16354; CHECK-NEXT: uaddl v0.2d, v3.2s, v6.2s355; CHECK-NEXT: uaddl2 v1.2d, v3.4s, v6.4s356; CHECK-NEXT: uaddl2 v3.2d, v7.4s, v4.4s357; CHECK-NEXT: uaddl v2.2d, v7.2s, v4.2s358; CHECK-NEXT: ret359 %s1 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>360 %z1 = zext <8 x i16> %s1 to <8 x i64>361 %s2 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>362 %z2 = zext <8 x i16> %s2 to <8 x i64>363 %s3 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>364 %z3 = zext <8 x i16> %s3 to <8 x i64>365 %s4 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>366 %z4 = zext <8 x i16> %s4 to <8 x i64>367 %a = add <8 x i64> %z1, %z2368 %b = add <8 x i64> %z3, %z4369 %c = add <8 x i64> %a, %b370 ret <8 x i64> %c371}372 373define <8 x i64> @zext_load_add(ptr %p) {374; CHECK-LABEL: zext_load_add:375; CHECK: // %bb.0:376; CHECK-NEXT: ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x0]377; CHECK-NEXT: uaddl v4.4s, v0.4h, v1.4h378; CHECK-NEXT: uaddl v5.4s, v2.4h, v3.4h379; CHECK-NEXT: uaddl2 v6.4s, v0.8h, v1.8h380; CHECK-NEXT: uaddl2 v2.4s, v2.8h, v3.8h381; CHECK-NEXT: uaddl v0.2d, v4.2s, v5.2s382; CHECK-NEXT: uaddl2 v1.2d, v4.4s, v5.4s383; CHECK-NEXT: uaddl2 v3.2d, v6.4s, v2.4s384; CHECK-NEXT: uaddl v2.2d, v6.2s, v2.2s385; CHECK-NEXT: ret386 %l = load <32 x i16>, ptr %p387 %s1 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>388 %z1 = zext <8 x i16> %s1 to <8 x i64>389 %s2 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>390 %z2 = zext <8 x i16> %s2 to <8 x i64>391 %s3 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>392 %z3 = zext <8 x i16> %s3 to <8 x i64>393 %s4 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>394 %z4 = zext <8 x i16> %s4 to <8 x i64>395 %a = add <8 x i64> %z1, %z2396 %b = add <8 x i64> %z3, %z4397 %c = add <8 x i64> %a, %b398 ret <8 x i64> %c399}400 401define <8 x double> @uitofp_fadd(<32 x i16> %l) {402; CHECK-LABEL: uitofp_fadd:403; CHECK: // %bb.0:404; CHECK-NEXT: movi v4.2d, #0x0000000000ffff405; CHECK-NEXT: ushr v5.2d, v0.2d, #16406; CHECK-NEXT: ushr v6.2d, v1.2d, #16407; CHECK-NEXT: ushr v7.2d, v2.2d, #16408; CHECK-NEXT: ushr v17.2d, v3.2d, #16409; CHECK-NEXT: ushr v20.2d, v0.2d, #32410; CHECK-NEXT: ushr v22.2d, v1.2d, #32411; CHECK-NEXT: ushr v23.2d, v2.2d, #32412; CHECK-NEXT: ushr v24.2d, v3.2d, #32413; CHECK-NEXT: and v16.16b, v0.16b, v4.16b414; CHECK-NEXT: and v18.16b, v1.16b, v4.16b415; CHECK-NEXT: and v19.16b, v2.16b, v4.16b416; CHECK-NEXT: and v21.16b, v3.16b, v4.16b417; CHECK-NEXT: and v5.16b, v5.16b, v4.16b418; CHECK-NEXT: and v6.16b, v6.16b, v4.16b419; CHECK-NEXT: and v7.16b, v7.16b, v4.16b420; CHECK-NEXT: and v17.16b, v17.16b, v4.16b421; CHECK-NEXT: and v20.16b, v20.16b, v4.16b422; CHECK-NEXT: and v22.16b, v22.16b, v4.16b423; CHECK-NEXT: and v23.16b, v23.16b, v4.16b424; CHECK-NEXT: and v4.16b, v24.16b, v4.16b425; CHECK-NEXT: ushr v0.2d, v0.2d, #48426; CHECK-NEXT: ushr v1.2d, v1.2d, #48427; CHECK-NEXT: ushr v2.2d, v2.2d, #48428; CHECK-NEXT: ushr v3.2d, v3.2d, #48429; CHECK-NEXT: ucvtf v16.2d, v16.2d430; CHECK-NEXT: ucvtf v18.2d, v18.2d431; CHECK-NEXT: ucvtf v19.2d, v19.2d432; CHECK-NEXT: ucvtf v21.2d, v21.2d433; CHECK-NEXT: ucvtf v5.2d, v5.2d434; CHECK-NEXT: ucvtf v6.2d, v6.2d435; CHECK-NEXT: ucvtf v7.2d, v7.2d436; CHECK-NEXT: ucvtf v17.2d, v17.2d437; CHECK-NEXT: ucvtf v20.2d, v20.2d438; CHECK-NEXT: ucvtf v22.2d, v22.2d439; CHECK-NEXT: ucvtf v23.2d, v23.2d440; CHECK-NEXT: ucvtf v4.2d, v4.2d441; CHECK-NEXT: ucvtf v0.2d, v0.2d442; CHECK-NEXT: ucvtf v1.2d, v1.2d443; CHECK-NEXT: ucvtf v2.2d, v2.2d444; CHECK-NEXT: ucvtf v3.2d, v3.2d445; CHECK-NEXT: fadd v5.2d, v16.2d, v5.2d446; CHECK-NEXT: fadd v17.2d, v21.2d, v17.2d447; CHECK-NEXT: fadd v7.2d, v19.2d, v7.2d448; CHECK-NEXT: fadd v6.2d, v18.2d, v6.2d449; CHECK-NEXT: fadd v0.2d, v20.2d, v0.2d450; CHECK-NEXT: fadd v1.2d, v22.2d, v1.2d451; CHECK-NEXT: fadd v3.2d, v4.2d, v3.2d452; CHECK-NEXT: fadd v2.2d, v23.2d, v2.2d453; CHECK-NEXT: fadd v0.2d, v5.2d, v0.2d454; CHECK-NEXT: fadd v1.2d, v6.2d, v1.2d455; CHECK-NEXT: fadd v2.2d, v7.2d, v2.2d456; CHECK-NEXT: fadd v3.2d, v17.2d, v3.2d457; CHECK-NEXT: ret458 %s1 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>459 %z1 = uitofp <8 x i16> %s1 to <8 x double>460 %s2 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>461 %z2 = uitofp <8 x i16> %s2 to <8 x double>462 %s3 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>463 %z3 = uitofp <8 x i16> %s3 to <8 x double>464 %s4 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>465 %z4 = uitofp <8 x i16> %s4 to <8 x double>466 %a = fadd <8 x double> %z1, %z2467 %b = fadd <8 x double> %z3, %z4468 %c = fadd <8 x double> %a, %b469 ret <8 x double> %c470}471 472define <8 x double> @uitofp_load_fadd(ptr %p) {473; CHECK-LABEL: uitofp_load_fadd:474; CHECK: // %bb.0:475; CHECK-NEXT: ldp q1, q2, [x0]476; CHECK-NEXT: movi v0.2d, #0x0000000000ffff477; CHECK-NEXT: ldp q3, q4, [x0, #32]478; CHECK-NEXT: ushr v5.2d, v1.2d, #16479; CHECK-NEXT: ushr v6.2d, v2.2d, #16480; CHECK-NEXT: ushr v20.2d, v1.2d, #32481; CHECK-NEXT: ushr v7.2d, v3.2d, #16482; CHECK-NEXT: ushr v17.2d, v4.2d, #16483; CHECK-NEXT: ushr v22.2d, v2.2d, #32484; CHECK-NEXT: ushr v23.2d, v3.2d, #32485; CHECK-NEXT: ushr v24.2d, v4.2d, #32486; CHECK-NEXT: and v16.16b, v1.16b, v0.16b487; CHECK-NEXT: and v18.16b, v2.16b, v0.16b488; CHECK-NEXT: and v19.16b, v3.16b, v0.16b489; CHECK-NEXT: and v21.16b, v4.16b, v0.16b490; CHECK-NEXT: and v5.16b, v5.16b, v0.16b491; CHECK-NEXT: and v6.16b, v6.16b, v0.16b492; CHECK-NEXT: and v7.16b, v7.16b, v0.16b493; CHECK-NEXT: and v17.16b, v17.16b, v0.16b494; CHECK-NEXT: and v20.16b, v20.16b, v0.16b495; CHECK-NEXT: and v22.16b, v22.16b, v0.16b496; CHECK-NEXT: and v23.16b, v23.16b, v0.16b497; CHECK-NEXT: and v0.16b, v24.16b, v0.16b498; CHECK-NEXT: ushr v1.2d, v1.2d, #48499; CHECK-NEXT: ushr v2.2d, v2.2d, #48500; CHECK-NEXT: ushr v3.2d, v3.2d, #48501; CHECK-NEXT: ushr v4.2d, v4.2d, #48502; CHECK-NEXT: ucvtf v16.2d, v16.2d503; CHECK-NEXT: ucvtf v18.2d, v18.2d504; CHECK-NEXT: ucvtf v19.2d, v19.2d505; CHECK-NEXT: ucvtf v21.2d, v21.2d506; CHECK-NEXT: ucvtf v5.2d, v5.2d507; CHECK-NEXT: ucvtf v6.2d, v6.2d508; CHECK-NEXT: ucvtf v7.2d, v7.2d509; CHECK-NEXT: ucvtf v17.2d, v17.2d510; CHECK-NEXT: ucvtf v20.2d, v20.2d511; CHECK-NEXT: ucvtf v22.2d, v22.2d512; CHECK-NEXT: ucvtf v23.2d, v23.2d513; CHECK-NEXT: ucvtf v0.2d, v0.2d514; CHECK-NEXT: ucvtf v1.2d, v1.2d515; CHECK-NEXT: ucvtf v2.2d, v2.2d516; CHECK-NEXT: ucvtf v3.2d, v3.2d517; CHECK-NEXT: ucvtf v4.2d, v4.2d518; CHECK-NEXT: fadd v6.2d, v18.2d, v6.2d519; CHECK-NEXT: fadd v5.2d, v16.2d, v5.2d520; CHECK-NEXT: fadd v17.2d, v21.2d, v17.2d521; CHECK-NEXT: fadd v7.2d, v19.2d, v7.2d522; CHECK-NEXT: fadd v1.2d, v20.2d, v1.2d523; CHECK-NEXT: fadd v3.2d, v23.2d, v3.2d524; CHECK-NEXT: fadd v2.2d, v22.2d, v2.2d525; CHECK-NEXT: fadd v4.2d, v0.2d, v4.2d526; CHECK-NEXT: fadd v0.2d, v5.2d, v1.2d527; CHECK-NEXT: fadd v1.2d, v6.2d, v2.2d528; CHECK-NEXT: fadd v2.2d, v7.2d, v3.2d529; CHECK-NEXT: fadd v3.2d, v17.2d, v4.2d530; CHECK-NEXT: ret531 %l = load <32 x i16>, ptr %p532 %s1 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>533 %z1 = uitofp <8 x i16> %s1 to <8 x double>534 %s2 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>535 %z2 = uitofp <8 x i16> %s2 to <8 x double>536 %s3 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>537 %z3 = uitofp <8 x i16> %s3 to <8 x double>538 %s4 = shufflevector <32 x i16> %l, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>539 %z4 = uitofp <8 x i16> %s4 to <8 x double>540 %a = fadd <8 x double> %z1, %z2541 %b = fadd <8 x double> %z3, %z4542 %c = fadd <8 x double> %a, %b543 ret <8 x double> %c544}545 546define <4 x i32> @isUndefDeInterleave_b0(<8 x i16> %a, <8 x i16> %b) {547; CHECK-LABEL: isUndefDeInterleave_b0:548; CHECK: // %bb.0:549; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff550; CHECK-NEXT: uzp1 v0.4s, v0.4s, v0.4s551; CHECK-NEXT: and v0.16b, v0.16b, v1.16b552; CHECK-NEXT: ret553 %2 = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 poison, i32 poison, i32 0, i32 4, i32 poison, i32 poison, i32 poison, i32 poison>554 %s2 = shufflevector <8 x i16> %2, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>555 %3 = zext <4 x i16> %s2 to <4 x i32>556 ret <4 x i32> %3557}558 559define <4 x i32> @isUndefDeInterleave_b1(<8 x i16> %a) {560; CHECK-LABEL: isUndefDeInterleave_b1:561; CHECK: // %bb.0:562; CHECK-NEXT: uzp1 v0.4s, v0.4s, v0.4s563; CHECK-NEXT: ushr v0.4s, v0.4s, #16564; CHECK-NEXT: ret565 %2 = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 poison, i32 poison, i32 1, i32 5, i32 poison, i32 poison, i32 poison, i32 poison>566 %s2 = shufflevector <8 x i16> %2, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>567 %3 = zext <4 x i16> %s2 to <4 x i32>568 ret <4 x i32> %3569}570 571define <4 x i32> @isUndefDeInterleave_b2(<8 x i16> %a) {572; CHECK-LABEL: isUndefDeInterleave_b2:573; CHECK: // %bb.0:574; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff575; CHECK-NEXT: uzp2 v0.4s, v0.4s, v0.4s576; CHECK-NEXT: and v0.16b, v0.16b, v1.16b577; CHECK-NEXT: ret578 %2 = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 poison, i32 poison, i32 2, i32 6, i32 poison, i32 poison, i32 poison, i32 poison>579 %s2 = shufflevector <8 x i16> %2, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>580 %3 = zext <4 x i16> %s2 to <4 x i32>581 ret <4 x i32> %3582}583 584define <4 x i32> @isUndefDeInterleave_b3(<8 x i16> %a) {585; CHECK-LABEL: isUndefDeInterleave_b3:586; CHECK: // %bb.0:587; CHECK-NEXT: uzp2 v0.4s, v0.4s, v0.4s588; CHECK-NEXT: ushr v0.4s, v0.4s, #16589; CHECK-NEXT: ret590 %2 = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 poison, i32 poison, i32 3, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>591 %s2 = shufflevector <8 x i16> %2, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>592 %3 = zext <4 x i16> %s2 to <4 x i32>593 ret <4 x i32> %3594}595 596define <4 x i32> @isUndefDeInterleave_t0(<8 x i16> %a, <8 x i16> %b) {597; CHECK-LABEL: isUndefDeInterleave_t0:598; CHECK: // %bb.0:599; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff600; CHECK-NEXT: uzp1 v0.4s, v0.4s, v0.4s601; CHECK-NEXT: and v0.16b, v0.16b, v1.16b602; CHECK-NEXT: ret603 %2 = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 4>604 %s2 = shufflevector <8 x i16> %2, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>605 %3 = zext <4 x i16> %s2 to <4 x i32>606 ret <4 x i32> %3607}608 609define <4 x i32> @isUndefDeInterleave_t1(<8 x i16> %a) {610; CHECK-LABEL: isUndefDeInterleave_t1:611; CHECK: // %bb.0:612; CHECK-NEXT: uzp1 v0.4s, v0.4s, v0.4s613; CHECK-NEXT: ushr v0.4s, v0.4s, #16614; CHECK-NEXT: ret615 %2 = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 1, i32 5>616 %s2 = shufflevector <8 x i16> %2, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>617 %3 = zext <4 x i16> %s2 to <4 x i32>618 ret <4 x i32> %3619}620 621define <4 x i32> @isUndefDeInterleave_t2(<8 x i16> %a) {622; CHECK-LABEL: isUndefDeInterleave_t2:623; CHECK: // %bb.0:624; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff625; CHECK-NEXT: uzp2 v0.4s, v0.4s, v0.4s626; CHECK-NEXT: and v0.16b, v0.16b, v1.16b627; CHECK-NEXT: ret628 %2 = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 2, i32 6>629 %s2 = shufflevector <8 x i16> %2, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>630 %3 = zext <4 x i16> %s2 to <4 x i32>631 ret <4 x i32> %3632}633 634define <4 x i32> @isUndefDeInterleave_t3(<8 x i16> %a) {635; CHECK-LABEL: isUndefDeInterleave_t3:636; CHECK: // %bb.0:637; CHECK-NEXT: uzp2 v0.4s, v0.4s, v0.4s638; CHECK-NEXT: ushr v0.4s, v0.4s, #16639; CHECK-NEXT: ret640 %2 = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 3, i32 7>641 %s2 = shufflevector <8 x i16> %2, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>642 %3 = zext <4 x i16> %s2 to <4 x i32>643 ret <4 x i32> %3644}645 646define <4 x i32> @isUndefDeInterleave_b0_bad(<8 x i16> %a, <8 x i16> %b) {647; CHECK-LABEL: isUndefDeInterleave_b0_bad:648; CHECK: // %bb.0:649; CHECK-NEXT: adrp x8, .LCPI40_0650; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI40_0]651; CHECK-NEXT: tbl v0.16b, { v0.16b }, v1.16b652; CHECK-NEXT: ushll v0.4s, v0.4h, #0653; CHECK-NEXT: ret654 %2 = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 4, i32 4, i32 0, i32 4, i32 poison, i32 poison, i32 poison, i32 poison>655 %s2 = shufflevector <8 x i16> %2, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>656 %3 = zext <4 x i16> %s2 to <4 x i32>657 ret <4 x i32> %3658}659 660define <4 x i32> @isUndefDeInterleave_t1_bad(<8 x i16> %a) {661; CHECK-LABEL: isUndefDeInterleave_t1_bad:662; CHECK: // %bb.0:663; CHECK-NEXT: adrp x8, .LCPI41_0664; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI41_0]665; CHECK-NEXT: tbl v0.16b, { v0.16b }, v1.16b666; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0667; CHECK-NEXT: ret668 %2 = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 4, i32 4, i32 1, i32 5>669 %s2 = shufflevector <8 x i16> %2, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>670 %3 = zext <4 x i16> %s2 to <4 x i32>671 ret <4 x i32> %3672}673 674define i16 @undeftop(<8 x i16> %0) {675; CHECK-LABEL: undeftop:676; CHECK: // %bb.0:677; CHECK-NEXT: add v0.8h, v0.8h, v0.8h678; CHECK-NEXT: umov w0, v0.h[4]679; CHECK-NEXT: ret680 %2 = shufflevector <8 x i16> %0, <8 x i16> zeroinitializer, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 9, i32 7, i32 5, i32 3>681 %3 = zext <8 x i16> %2 to <8 x i64>682 %new0 = add <8 x i64> %3, %3683 %last = trunc <8 x i64> %new0 to <8 x i16>684 %4 = extractelement <8 x i16> %last, i32 0685 ret i16 %4686}687