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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; CHECK-GI: warning: Instruction selection used fallback path for zext_v16i10_v16i166 7define i16 @zext_i8_to_i16(i8 %a) {8; CHECK-LABEL: zext_i8_to_i16:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: and w0, w0, #0xff11; CHECK-NEXT: ret12entry:13 %c = zext i8 %a to i1614 ret i16 %c15}16 17define i32 @zext_i8_to_i32(i8 %a) {18; CHECK-LABEL: zext_i8_to_i32:19; CHECK: // %bb.0: // %entry20; CHECK-NEXT: and w0, w0, #0xff21; CHECK-NEXT: ret22entry:23 %c = zext i8 %a to i3224 ret i32 %c25}26 27define i64 @zext_i8_to_i64(i8 %a) {28; CHECK-LABEL: zext_i8_to_i64:29; CHECK: // %bb.0: // %entry30; CHECK-NEXT: // kill: def $w0 killed $w0 def $x031; CHECK-NEXT: and x0, x0, #0xff32; CHECK-NEXT: ret33entry:34 %c = zext i8 %a to i6435 ret i64 %c36}37 38define i10 @zext_i8_to_i10(i8 %a) {39; CHECK-LABEL: zext_i8_to_i10:40; CHECK: // %bb.0: // %entry41; CHECK-NEXT: and w0, w0, #0xff42; CHECK-NEXT: ret43entry:44 %c = zext i8 %a to i1045 ret i10 %c46}47 48define i32 @zext_i16_to_i32(i16 %a) {49; CHECK-LABEL: zext_i16_to_i32:50; CHECK: // %bb.0: // %entry51; CHECK-NEXT: and w0, w0, #0xffff52; CHECK-NEXT: ret53entry:54 %c = zext i16 %a to i3255 ret i32 %c56}57 58define i64 @zext_i16_to_i64(i16 %a) {59; CHECK-LABEL: zext_i16_to_i64:60; CHECK: // %bb.0: // %entry61; CHECK-NEXT: // kill: def $w0 killed $w0 def $x062; CHECK-NEXT: and x0, x0, #0xffff63; CHECK-NEXT: ret64entry:65 %c = zext i16 %a to i6466 ret i64 %c67}68 69define i64 @zext_i32_to_i64(i32 %a) {70; CHECK-LABEL: zext_i32_to_i64:71; CHECK: // %bb.0: // %entry72; CHECK-NEXT: mov w0, w073; CHECK-NEXT: ret74entry:75 %c = zext i32 %a to i6476 ret i64 %c77}78 79define i16 @zext_i10_to_i16(i10 %a) {80; CHECK-LABEL: zext_i10_to_i16:81; CHECK: // %bb.0: // %entry82; CHECK-NEXT: and w0, w0, #0x3ff83; CHECK-NEXT: ret84entry:85 %c = zext i10 %a to i1686 ret i16 %c87}88 89define i32 @zext_i10_to_i32(i10 %a) {90; CHECK-LABEL: zext_i10_to_i32:91; CHECK: // %bb.0: // %entry92; CHECK-NEXT: and w0, w0, #0x3ff93; CHECK-NEXT: ret94entry:95 %c = zext i10 %a to i3296 ret i32 %c97}98 99define i64 @zext_i10_to_i64(i10 %a) {100; CHECK-LABEL: zext_i10_to_i64:101; CHECK: // %bb.0: // %entry102; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0103; CHECK-NEXT: and x0, x0, #0x3ff104; CHECK-NEXT: ret105entry:106 %c = zext i10 %a to i64107 ret i64 %c108}109 110define <2 x i16> @zext_v2i8_v2i16(<2 x i8> %a) {111; CHECK-LABEL: zext_v2i8_v2i16:112; CHECK: // %bb.0: // %entry113; CHECK-NEXT: movi d1, #0x0000ff000000ff114; CHECK-NEXT: and v0.8b, v0.8b, v1.8b115; CHECK-NEXT: ret116entry:117 %c = zext <2 x i8> %a to <2 x i16>118 ret <2 x i16> %c119}120 121define <2 x i32> @zext_v2i8_v2i32(<2 x i8> %a) {122; CHECK-LABEL: zext_v2i8_v2i32:123; CHECK: // %bb.0: // %entry124; CHECK-NEXT: movi d1, #0x0000ff000000ff125; CHECK-NEXT: and v0.8b, v0.8b, v1.8b126; CHECK-NEXT: ret127entry:128 %c = zext <2 x i8> %a to <2 x i32>129 ret <2 x i32> %c130}131 132define <2 x i64> @zext_v2i8_v2i64(<2 x i8> %a) {133; CHECK-SD-LABEL: zext_v2i8_v2i64:134; CHECK-SD: // %bb.0: // %entry135; CHECK-SD-NEXT: movi d1, #0x0000ff000000ff136; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b137; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0138; CHECK-SD-NEXT: ret139;140; CHECK-GI-LABEL: zext_v2i8_v2i64:141; CHECK-GI: // %bb.0: // %entry142; CHECK-GI-NEXT: movi v1.2d, #0x000000000000ff143; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0144; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b145; CHECK-GI-NEXT: ret146entry:147 %c = zext <2 x i8> %a to <2 x i64>148 ret <2 x i64> %c149}150 151define <2 x i32> @zext_v2i16_v2i32(<2 x i16> %a) {152; CHECK-LABEL: zext_v2i16_v2i32:153; CHECK: // %bb.0: // %entry154; CHECK-NEXT: movi d1, #0x00ffff0000ffff155; CHECK-NEXT: and v0.8b, v0.8b, v1.8b156; CHECK-NEXT: ret157entry:158 %c = zext <2 x i16> %a to <2 x i32>159 ret <2 x i32> %c160}161 162define <2 x i64> @zext_v2i16_v2i64(<2 x i16> %a) {163; CHECK-SD-LABEL: zext_v2i16_v2i64:164; CHECK-SD: // %bb.0: // %entry165; CHECK-SD-NEXT: movi d1, #0x00ffff0000ffff166; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b167; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0168; CHECK-SD-NEXT: ret169;170; CHECK-GI-LABEL: zext_v2i16_v2i64:171; CHECK-GI: // %bb.0: // %entry172; CHECK-GI-NEXT: movi v1.2d, #0x0000000000ffff173; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0174; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b175; CHECK-GI-NEXT: ret176entry:177 %c = zext <2 x i16> %a to <2 x i64>178 ret <2 x i64> %c179}180 181define <2 x i64> @zext_v2i32_v2i64(<2 x i32> %a) {182; CHECK-LABEL: zext_v2i32_v2i64:183; CHECK: // %bb.0: // %entry184; CHECK-NEXT: ushll v0.2d, v0.2s, #0185; CHECK-NEXT: ret186entry:187 %c = zext <2 x i32> %a to <2 x i64>188 ret <2 x i64> %c189}190 191define <2 x i16> @zext_v2i10_v2i16(<2 x i10> %a) {192; CHECK-LABEL: zext_v2i10_v2i16:193; CHECK: // %bb.0: // %entry194; CHECK-NEXT: movi v1.2s, #3, msl #8195; CHECK-NEXT: and v0.8b, v0.8b, v1.8b196; CHECK-NEXT: ret197entry:198 %c = zext <2 x i10> %a to <2 x i16>199 ret <2 x i16> %c200}201 202define <2 x i32> @zext_v2i10_v2i32(<2 x i10> %a) {203; CHECK-LABEL: zext_v2i10_v2i32:204; CHECK: // %bb.0: // %entry205; CHECK-NEXT: movi v1.2s, #3, msl #8206; CHECK-NEXT: and v0.8b, v0.8b, v1.8b207; CHECK-NEXT: ret208entry:209 %c = zext <2 x i10> %a to <2 x i32>210 ret <2 x i32> %c211}212 213define <2 x i64> @zext_v2i10_v2i64(<2 x i10> %a) {214; CHECK-SD-LABEL: zext_v2i10_v2i64:215; CHECK-SD: // %bb.0: // %entry216; CHECK-SD-NEXT: movi v1.2s, #3, msl #8217; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b218; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0219; CHECK-SD-NEXT: ret220;221; CHECK-GI-LABEL: zext_v2i10_v2i64:222; CHECK-GI: // %bb.0: // %entry223; CHECK-GI-NEXT: adrp x8, .LCPI18_0224; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0225; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI18_0]226; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b227; CHECK-GI-NEXT: ret228entry:229 %c = zext <2 x i10> %a to <2 x i64>230 ret <2 x i64> %c231}232 233define <3 x i16> @zext_v3i8_v3i16(<3 x i8> %a) {234; CHECK-SD-LABEL: zext_v3i8_v3i16:235; CHECK-SD: // %bb.0: // %entry236; CHECK-SD-NEXT: fmov s0, w0237; CHECK-SD-NEXT: mov v0.h[1], w1238; CHECK-SD-NEXT: mov v0.h[2], w2239; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8240; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0241; CHECK-SD-NEXT: ret242;243; CHECK-GI-LABEL: zext_v3i8_v3i16:244; CHECK-GI: // %bb.0: // %entry245; CHECK-GI-NEXT: and w8, w0, #0xff246; CHECK-GI-NEXT: and w9, w1, #0xff247; CHECK-GI-NEXT: fmov s0, w8248; CHECK-GI-NEXT: and w8, w2, #0xff249; CHECK-GI-NEXT: mov v0.h[1], w9250; CHECK-GI-NEXT: mov v0.h[2], w8251; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0252; CHECK-GI-NEXT: ret253entry:254 %c = zext <3 x i8> %a to <3 x i16>255 ret <3 x i16> %c256}257 258define <3 x i32> @zext_v3i8_v3i32(<3 x i8> %a) {259; CHECK-SD-LABEL: zext_v3i8_v3i32:260; CHECK-SD: // %bb.0: // %entry261; CHECK-SD-NEXT: fmov s0, w0262; CHECK-SD-NEXT: movi v1.2d, #0x0000ff000000ff263; CHECK-SD-NEXT: mov v0.h[1], w1264; CHECK-SD-NEXT: mov v0.h[2], w2265; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0266; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b267; CHECK-SD-NEXT: ret268;269; CHECK-GI-LABEL: zext_v3i8_v3i32:270; CHECK-GI: // %bb.0: // %entry271; CHECK-GI-NEXT: and w8, w0, #0xff272; CHECK-GI-NEXT: and w9, w1, #0xff273; CHECK-GI-NEXT: fmov s0, w8274; CHECK-GI-NEXT: and w8, w2, #0xff275; CHECK-GI-NEXT: mov v0.s[1], w9276; CHECK-GI-NEXT: mov v0.s[2], w8277; CHECK-GI-NEXT: ret278entry:279 %c = zext <3 x i8> %a to <3 x i32>280 ret <3 x i32> %c281}282 283define <3 x i64> @zext_v3i8_v3i64(<3 x i8> %a) {284; CHECK-SD-LABEL: zext_v3i8_v3i64:285; CHECK-SD: // %bb.0: // %entry286; CHECK-SD-NEXT: fmov s0, w0287; CHECK-SD-NEXT: movi v1.2d, #0x000000000000ff288; CHECK-SD-NEXT: fmov s3, w2289; CHECK-SD-NEXT: movi v2.2d, #0000000000000000290; CHECK-SD-NEXT: mov v0.s[1], w1291; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0292; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b293; CHECK-SD-NEXT: ushll v1.2d, v3.2s, #0294; CHECK-SD-NEXT: mov v2.b[0], v1.b[0]295; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8296; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0297; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1298; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2299; CHECK-SD-NEXT: ret300;301; CHECK-GI-LABEL: zext_v3i8_v3i64:302; CHECK-GI: // %bb.0: // %entry303; CHECK-GI-NEXT: // kill: def $w0 killed $w0 def $x0304; CHECK-GI-NEXT: // kill: def $w1 killed $w1 def $x1305; CHECK-GI-NEXT: // kill: def $w2 killed $w2 def $x2306; CHECK-GI-NEXT: and x8, x0, #0xff307; CHECK-GI-NEXT: and x9, x1, #0xff308; CHECK-GI-NEXT: and x10, x2, #0xff309; CHECK-GI-NEXT: fmov d0, x8310; CHECK-GI-NEXT: fmov d1, x9311; CHECK-GI-NEXT: fmov d2, x10312; CHECK-GI-NEXT: ret313entry:314 %c = zext <3 x i8> %a to <3 x i64>315 ret <3 x i64> %c316}317 318define <3 x i32> @zext_v3i16_v3i32(<3 x i16> %a) {319; CHECK-SD-LABEL: zext_v3i16_v3i32:320; CHECK-SD: // %bb.0: // %entry321; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0322; CHECK-SD-NEXT: ret323;324; CHECK-GI-LABEL: zext_v3i16_v3i32:325; CHECK-GI: // %bb.0: // %entry326; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0327; CHECK-GI-NEXT: umov w8, v0.h[0]328; CHECK-GI-NEXT: umov w9, v0.h[1]329; CHECK-GI-NEXT: fmov s1, w8330; CHECK-GI-NEXT: umov w8, v0.h[2]331; CHECK-GI-NEXT: mov v1.s[1], w9332; CHECK-GI-NEXT: mov v1.s[2], w8333; CHECK-GI-NEXT: mov v0.16b, v1.16b334; CHECK-GI-NEXT: ret335entry:336 %c = zext <3 x i16> %a to <3 x i32>337 ret <3 x i32> %c338}339 340define <3 x i64> @zext_v3i16_v3i64(<3 x i16> %a) {341; CHECK-SD-LABEL: zext_v3i16_v3i64:342; CHECK-SD: // %bb.0: // %entry343; CHECK-SD-NEXT: ushll v2.4s, v0.4h, #0344; CHECK-SD-NEXT: ushll v0.2d, v2.2s, #0345; CHECK-SD-NEXT: ushll2 v2.2d, v2.4s, #0346; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2347; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8348; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0349; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1350; CHECK-SD-NEXT: ret351;352; CHECK-GI-LABEL: zext_v3i16_v3i64:353; CHECK-GI: // %bb.0: // %entry354; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0355; CHECK-GI-NEXT: umov w8, v0.h[0]356; CHECK-GI-NEXT: umov w9, v0.h[1]357; CHECK-GI-NEXT: umov w10, v0.h[2]358; CHECK-GI-NEXT: fmov d0, x8359; CHECK-GI-NEXT: fmov d1, x9360; CHECK-GI-NEXT: fmov d2, x10361; CHECK-GI-NEXT: ret362entry:363 %c = zext <3 x i16> %a to <3 x i64>364 ret <3 x i64> %c365}366 367define <3 x i64> @zext_v3i32_v3i64(<3 x i32> %a) {368; CHECK-SD-LABEL: zext_v3i32_v3i64:369; CHECK-SD: // %bb.0: // %entry370; CHECK-SD-NEXT: ushll v3.2d, v0.2s, #0371; CHECK-SD-NEXT: ushll2 v2.2d, v0.4s, #0372; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2373; CHECK-SD-NEXT: fmov d0, d3374; CHECK-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8375; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1376; CHECK-SD-NEXT: ret377;378; CHECK-GI-LABEL: zext_v3i32_v3i64:379; CHECK-GI: // %bb.0: // %entry380; CHECK-GI-NEXT: mov w8, v0.s[0]381; CHECK-GI-NEXT: mov w9, v0.s[1]382; CHECK-GI-NEXT: mov w10, v0.s[2]383; CHECK-GI-NEXT: fmov d0, x8384; CHECK-GI-NEXT: fmov d1, x9385; CHECK-GI-NEXT: fmov d2, x10386; CHECK-GI-NEXT: ret387entry:388 %c = zext <3 x i32> %a to <3 x i64>389 ret <3 x i64> %c390}391 392define <3 x i16> @zext_v3i10_v3i16(<3 x i10> %a) {393; CHECK-SD-LABEL: zext_v3i10_v3i16:394; CHECK-SD: // %bb.0: // %entry395; CHECK-SD-NEXT: fmov s0, w0396; CHECK-SD-NEXT: mov v0.h[1], w1397; CHECK-SD-NEXT: mov v0.h[2], w2398; CHECK-SD-NEXT: bic v0.4h, #252, lsl #8399; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0400; CHECK-SD-NEXT: ret401;402; CHECK-GI-LABEL: zext_v3i10_v3i16:403; CHECK-GI: // %bb.0: // %entry404; CHECK-GI-NEXT: and w8, w0, #0x3ff405; CHECK-GI-NEXT: and w9, w1, #0x3ff406; CHECK-GI-NEXT: fmov s0, w8407; CHECK-GI-NEXT: and w8, w2, #0x3ff408; CHECK-GI-NEXT: mov v0.h[1], w9409; CHECK-GI-NEXT: mov v0.h[2], w8410; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0411; CHECK-GI-NEXT: ret412entry:413 %c = zext <3 x i10> %a to <3 x i16>414 ret <3 x i16> %c415}416 417define <3 x i32> @zext_v3i10_v3i32(<3 x i10> %a) {418; CHECK-SD-LABEL: zext_v3i10_v3i32:419; CHECK-SD: // %bb.0: // %entry420; CHECK-SD-NEXT: fmov s0, w0421; CHECK-SD-NEXT: movi v1.4s, #3, msl #8422; CHECK-SD-NEXT: mov v0.h[1], w1423; CHECK-SD-NEXT: mov v0.h[2], w2424; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0425; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b426; CHECK-SD-NEXT: ret427;428; CHECK-GI-LABEL: zext_v3i10_v3i32:429; CHECK-GI: // %bb.0: // %entry430; CHECK-GI-NEXT: and w8, w0, #0x3ff431; CHECK-GI-NEXT: and w9, w1, #0x3ff432; CHECK-GI-NEXT: fmov s0, w8433; CHECK-GI-NEXT: and w8, w2, #0x3ff434; CHECK-GI-NEXT: mov v0.s[1], w9435; CHECK-GI-NEXT: mov v0.s[2], w8436; CHECK-GI-NEXT: ret437entry:438 %c = zext <3 x i10> %a to <3 x i32>439 ret <3 x i32> %c440}441 442define <3 x i64> @zext_v3i10_v3i64(<3 x i10> %a) {443; CHECK-SD-LABEL: zext_v3i10_v3i64:444; CHECK-SD: // %bb.0: // %entry445; CHECK-SD-NEXT: fmov s0, w0446; CHECK-SD-NEXT: fmov s1, w2447; CHECK-SD-NEXT: mov w8, #1023 // =0x3ff448; CHECK-SD-NEXT: dup v2.2d, x8449; CHECK-SD-NEXT: mov v0.s[1], w1450; CHECK-SD-NEXT: zip1 v3.2s, v1.2s, v1.2s451; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0452; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b453; CHECK-SD-NEXT: and v2.8b, v3.8b, v2.8b454; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8455; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0456; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1457; CHECK-SD-NEXT: ret458;459; CHECK-GI-LABEL: zext_v3i10_v3i64:460; CHECK-GI: // %bb.0: // %entry461; CHECK-GI-NEXT: // kill: def $w0 killed $w0 def $x0462; CHECK-GI-NEXT: // kill: def $w1 killed $w1 def $x1463; CHECK-GI-NEXT: // kill: def $w2 killed $w2 def $x2464; CHECK-GI-NEXT: and x8, x0, #0x3ff465; CHECK-GI-NEXT: and x9, x1, #0x3ff466; CHECK-GI-NEXT: and x10, x2, #0x3ff467; CHECK-GI-NEXT: fmov d0, x8468; CHECK-GI-NEXT: fmov d1, x9469; CHECK-GI-NEXT: fmov d2, x10470; CHECK-GI-NEXT: ret471entry:472 %c = zext <3 x i10> %a to <3 x i64>473 ret <3 x i64> %c474}475 476define <4 x i16> @zext_v4i8_v4i16(<4 x i8> %a) {477; CHECK-SD-LABEL: zext_v4i8_v4i16:478; CHECK-SD: // %bb.0: // %entry479; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8480; CHECK-SD-NEXT: ret481;482; CHECK-GI-LABEL: zext_v4i8_v4i16:483; CHECK-GI: // %bb.0: // %entry484; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff485; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b486; CHECK-GI-NEXT: ret487entry:488 %c = zext <4 x i8> %a to <4 x i16>489 ret <4 x i16> %c490}491 492define <4 x i32> @zext_v4i8_v4i32(<4 x i8> %a) {493; CHECK-SD-LABEL: zext_v4i8_v4i32:494; CHECK-SD: // %bb.0: // %entry495; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8496; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0497; CHECK-SD-NEXT: ret498;499; CHECK-GI-LABEL: zext_v4i8_v4i32:500; CHECK-GI: // %bb.0: // %entry501; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff502; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0503; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b504; CHECK-GI-NEXT: ret505entry:506 %c = zext <4 x i8> %a to <4 x i32>507 ret <4 x i32> %c508}509 510define <4 x i64> @zext_v4i8_v4i64(<4 x i8> %a) {511; CHECK-SD-LABEL: zext_v4i8_v4i64:512; CHECK-SD: // %bb.0: // %entry513; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8514; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0515; CHECK-SD-NEXT: ushll2 v1.2d, v0.4s, #0516; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0517; CHECK-SD-NEXT: ret518;519; CHECK-GI-LABEL: zext_v4i8_v4i64:520; CHECK-GI: // %bb.0: // %entry521; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0522; CHECK-GI-NEXT: movi v1.2d, #0x000000000000ff523; CHECK-GI-NEXT: ushll v2.2d, v0.2s, #0524; CHECK-GI-NEXT: ushll2 v3.2d, v0.4s, #0525; CHECK-GI-NEXT: and v0.16b, v2.16b, v1.16b526; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b527; CHECK-GI-NEXT: ret528entry:529 %c = zext <4 x i8> %a to <4 x i64>530 ret <4 x i64> %c531}532 533define <4 x i32> @zext_v4i16_v4i32(<4 x i16> %a) {534; CHECK-LABEL: zext_v4i16_v4i32:535; CHECK: // %bb.0: // %entry536; CHECK-NEXT: ushll v0.4s, v0.4h, #0537; CHECK-NEXT: ret538entry:539 %c = zext <4 x i16> %a to <4 x i32>540 ret <4 x i32> %c541}542 543define <4 x i64> @zext_v4i16_v4i64(<4 x i16> %a) {544; CHECK-SD-LABEL: zext_v4i16_v4i64:545; CHECK-SD: // %bb.0: // %entry546; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0547; CHECK-SD-NEXT: ushll2 v1.2d, v0.4s, #0548; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0549; CHECK-SD-NEXT: ret550;551; CHECK-GI-LABEL: zext_v4i16_v4i64:552; CHECK-GI: // %bb.0: // %entry553; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0554; CHECK-GI-NEXT: ushll v0.2d, v1.2s, #0555; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #0556; CHECK-GI-NEXT: ret557entry:558 %c = zext <4 x i16> %a to <4 x i64>559 ret <4 x i64> %c560}561 562define <4 x i64> @zext_v4i32_v4i64(<4 x i32> %a) {563; CHECK-SD-LABEL: zext_v4i32_v4i64:564; CHECK-SD: // %bb.0: // %entry565; CHECK-SD-NEXT: ushll2 v1.2d, v0.4s, #0566; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0567; CHECK-SD-NEXT: ret568;569; CHECK-GI-LABEL: zext_v4i32_v4i64:570; CHECK-GI: // %bb.0: // %entry571; CHECK-GI-NEXT: ushll v2.2d, v0.2s, #0572; CHECK-GI-NEXT: ushll2 v1.2d, v0.4s, #0573; CHECK-GI-NEXT: mov v0.16b, v2.16b574; CHECK-GI-NEXT: ret575entry:576 %c = zext <4 x i32> %a to <4 x i64>577 ret <4 x i64> %c578}579 580define <4 x i16> @zext_v4i10_v4i16(<4 x i10> %a) {581; CHECK-SD-LABEL: zext_v4i10_v4i16:582; CHECK-SD: // %bb.0: // %entry583; CHECK-SD-NEXT: bic v0.4h, #252, lsl #8584; CHECK-SD-NEXT: ret585;586; CHECK-GI-LABEL: zext_v4i10_v4i16:587; CHECK-GI: // %bb.0: // %entry588; CHECK-GI-NEXT: mvni v1.4h, #252, lsl #8589; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b590; CHECK-GI-NEXT: ret591entry:592 %c = zext <4 x i10> %a to <4 x i16>593 ret <4 x i16> %c594}595 596define <4 x i32> @zext_v4i10_v4i32(<4 x i10> %a) {597; CHECK-SD-LABEL: zext_v4i10_v4i32:598; CHECK-SD: // %bb.0: // %entry599; CHECK-SD-NEXT: bic v0.4h, #252, lsl #8600; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0601; CHECK-SD-NEXT: ret602;603; CHECK-GI-LABEL: zext_v4i10_v4i32:604; CHECK-GI: // %bb.0: // %entry605; CHECK-GI-NEXT: movi v1.4s, #3, msl #8606; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0607; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b608; CHECK-GI-NEXT: ret609entry:610 %c = zext <4 x i10> %a to <4 x i32>611 ret <4 x i32> %c612}613 614define <4 x i64> @zext_v4i10_v4i64(<4 x i10> %a) {615; CHECK-SD-LABEL: zext_v4i10_v4i64:616; CHECK-SD: // %bb.0: // %entry617; CHECK-SD-NEXT: bic v0.4h, #252, lsl #8618; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0619; CHECK-SD-NEXT: ushll2 v1.2d, v0.4s, #0620; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0621; CHECK-SD-NEXT: ret622;623; CHECK-GI-LABEL: zext_v4i10_v4i64:624; CHECK-GI: // %bb.0: // %entry625; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0626; CHECK-GI-NEXT: adrp x8, .LCPI36_0627; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI36_0]628; CHECK-GI-NEXT: ushll v1.2d, v0.2s, #0629; CHECK-GI-NEXT: ushll2 v2.2d, v0.4s, #0630; CHECK-GI-NEXT: and v0.16b, v1.16b, v3.16b631; CHECK-GI-NEXT: and v1.16b, v2.16b, v3.16b632; CHECK-GI-NEXT: ret633entry:634 %c = zext <4 x i10> %a to <4 x i64>635 ret <4 x i64> %c636}637 638define <8 x i16> @zext_v8i8_v8i16(<8 x i8> %a) {639; CHECK-LABEL: zext_v8i8_v8i16:640; CHECK: // %bb.0: // %entry641; CHECK-NEXT: ushll v0.8h, v0.8b, #0642; CHECK-NEXT: ret643entry:644 %c = zext <8 x i8> %a to <8 x i16>645 ret <8 x i16> %c646}647 648define <8 x i32> @zext_v8i8_v8i32(<8 x i8> %a) {649; CHECK-SD-LABEL: zext_v8i8_v8i32:650; CHECK-SD: // %bb.0: // %entry651; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0652; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0653; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0654; CHECK-SD-NEXT: ret655;656; CHECK-GI-LABEL: zext_v8i8_v8i32:657; CHECK-GI: // %bb.0: // %entry658; CHECK-GI-NEXT: ushll v1.8h, v0.8b, #0659; CHECK-GI-NEXT: ushll v0.4s, v1.4h, #0660; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0661; CHECK-GI-NEXT: ret662entry:663 %c = zext <8 x i8> %a to <8 x i32>664 ret <8 x i32> %c665}666 667define <8 x i64> @zext_v8i8_v8i64(<8 x i8> %a) {668; CHECK-SD-LABEL: zext_v8i8_v8i64:669; CHECK-SD: // %bb.0: // %entry670; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0671; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0672; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0673; CHECK-SD-NEXT: ushll v0.2d, v1.2s, #0674; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0675; CHECK-SD-NEXT: ushll2 v1.2d, v1.4s, #0676; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0677; CHECK-SD-NEXT: ret678;679; CHECK-GI-LABEL: zext_v8i8_v8i64:680; CHECK-GI: // %bb.0: // %entry681; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0682; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0683; CHECK-GI-NEXT: ushll2 v3.4s, v0.8h, #0684; CHECK-GI-NEXT: ushll v0.2d, v1.2s, #0685; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #0686; CHECK-GI-NEXT: ushll v2.2d, v3.2s, #0687; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #0688; CHECK-GI-NEXT: ret689entry:690 %c = zext <8 x i8> %a to <8 x i64>691 ret <8 x i64> %c692}693 694define <8 x i32> @zext_v8i16_v8i32(<8 x i16> %a) {695; CHECK-SD-LABEL: zext_v8i16_v8i32:696; CHECK-SD: // %bb.0: // %entry697; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0698; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0699; CHECK-SD-NEXT: ret700;701; CHECK-GI-LABEL: zext_v8i16_v8i32:702; CHECK-GI: // %bb.0: // %entry703; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0704; CHECK-GI-NEXT: ushll2 v1.4s, v0.8h, #0705; CHECK-GI-NEXT: mov v0.16b, v2.16b706; CHECK-GI-NEXT: ret707entry:708 %c = zext <8 x i16> %a to <8 x i32>709 ret <8 x i32> %c710}711 712define <8 x i64> @zext_v8i16_v8i64(<8 x i16> %a) {713; CHECK-SD-LABEL: zext_v8i16_v8i64:714; CHECK-SD: // %bb.0: // %entry715; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0716; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0717; CHECK-SD-NEXT: ushll v0.2d, v1.2s, #0718; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0719; CHECK-SD-NEXT: ushll2 v1.2d, v1.4s, #0720; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0721; CHECK-SD-NEXT: ret722;723; CHECK-GI-LABEL: zext_v8i16_v8i64:724; CHECK-GI: // %bb.0: // %entry725; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0726; CHECK-GI-NEXT: ushll2 v3.4s, v0.8h, #0727; CHECK-GI-NEXT: ushll v0.2d, v1.2s, #0728; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #0729; CHECK-GI-NEXT: ushll v2.2d, v3.2s, #0730; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #0731; CHECK-GI-NEXT: ret732entry:733 %c = zext <8 x i16> %a to <8 x i64>734 ret <8 x i64> %c735}736 737define <8 x i64> @zext_v8i32_v8i64(<8 x i32> %a) {738; CHECK-SD-LABEL: zext_v8i32_v8i64:739; CHECK-SD: // %bb.0: // %entry740; CHECK-SD-NEXT: ushll v5.2d, v0.2s, #0741; CHECK-SD-NEXT: ushll2 v4.2d, v0.4s, #0742; CHECK-SD-NEXT: ushll2 v3.2d, v1.4s, #0743; CHECK-SD-NEXT: ushll v2.2d, v1.2s, #0744; CHECK-SD-NEXT: mov v0.16b, v5.16b745; CHECK-SD-NEXT: mov v1.16b, v4.16b746; CHECK-SD-NEXT: ret747;748; CHECK-GI-LABEL: zext_v8i32_v8i64:749; CHECK-GI: // %bb.0: // %entry750; CHECK-GI-NEXT: ushll v4.2d, v0.2s, #0751; CHECK-GI-NEXT: ushll2 v5.2d, v0.4s, #0752; CHECK-GI-NEXT: ushll v2.2d, v1.2s, #0753; CHECK-GI-NEXT: ushll2 v3.2d, v1.4s, #0754; CHECK-GI-NEXT: mov v0.16b, v4.16b755; CHECK-GI-NEXT: mov v1.16b, v5.16b756; CHECK-GI-NEXT: ret757entry:758 %c = zext <8 x i32> %a to <8 x i64>759 ret <8 x i64> %c760}761 762define <8 x i16> @zext_v8i10_v8i16(<8 x i10> %a) {763; CHECK-SD-LABEL: zext_v8i10_v8i16:764; CHECK-SD: // %bb.0: // %entry765; CHECK-SD-NEXT: bic v0.8h, #252, lsl #8766; CHECK-SD-NEXT: ret767;768; CHECK-GI-LABEL: zext_v8i10_v8i16:769; CHECK-GI: // %bb.0: // %entry770; CHECK-GI-NEXT: mvni v1.8h, #252, lsl #8771; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b772; CHECK-GI-NEXT: ret773entry:774 %c = zext <8 x i10> %a to <8 x i16>775 ret <8 x i16> %c776}777 778define <8 x i32> @zext_v8i10_v8i32(<8 x i10> %a) {779; CHECK-SD-LABEL: zext_v8i10_v8i32:780; CHECK-SD: // %bb.0: // %entry781; CHECK-SD-NEXT: bic v0.8h, #252, lsl #8782; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0783; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0784; CHECK-SD-NEXT: ret785;786; CHECK-GI-LABEL: zext_v8i10_v8i32:787; CHECK-GI: // %bb.0: // %entry788; CHECK-GI-NEXT: movi v1.4s, #3, msl #8789; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0790; CHECK-GI-NEXT: ushll2 v3.4s, v0.8h, #0791; CHECK-GI-NEXT: and v0.16b, v2.16b, v1.16b792; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b793; CHECK-GI-NEXT: ret794entry:795 %c = zext <8 x i10> %a to <8 x i32>796 ret <8 x i32> %c797}798 799define <8 x i64> @zext_v8i10_v8i64(<8 x i10> %a) {800; CHECK-SD-LABEL: zext_v8i10_v8i64:801; CHECK-SD: // %bb.0: // %entry802; CHECK-SD-NEXT: bic v0.8h, #252, lsl #8803; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0804; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0805; CHECK-SD-NEXT: ushll v0.2d, v1.2s, #0806; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0807; CHECK-SD-NEXT: ushll2 v1.2d, v1.4s, #0808; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0809; CHECK-SD-NEXT: ret810;811; CHECK-GI-LABEL: zext_v8i10_v8i64:812; CHECK-GI: // %bb.0: // %entry813; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0814; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0815; CHECK-GI-NEXT: adrp x8, .LCPI45_0816; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI45_0]817; CHECK-GI-NEXT: ushll v2.2d, v1.2s, #0818; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #0819; CHECK-GI-NEXT: ushll v4.2d, v0.2s, #0820; CHECK-GI-NEXT: ushll2 v5.2d, v0.4s, #0821; CHECK-GI-NEXT: and v0.16b, v2.16b, v3.16b822; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b823; CHECK-GI-NEXT: and v2.16b, v4.16b, v3.16b824; CHECK-GI-NEXT: and v3.16b, v5.16b, v3.16b825; CHECK-GI-NEXT: ret826entry:827 %c = zext <8 x i10> %a to <8 x i64>828 ret <8 x i64> %c829}830 831define <16 x i16> @zext_v16i8_v16i16(<16 x i8> %a) {832; CHECK-SD-LABEL: zext_v16i8_v16i16:833; CHECK-SD: // %bb.0: // %entry834; CHECK-SD-NEXT: ushll2 v1.8h, v0.16b, #0835; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0836; CHECK-SD-NEXT: ret837;838; CHECK-GI-LABEL: zext_v16i8_v16i16:839; CHECK-GI: // %bb.0: // %entry840; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0841; CHECK-GI-NEXT: ushll2 v1.8h, v0.16b, #0842; CHECK-GI-NEXT: mov v0.16b, v2.16b843; CHECK-GI-NEXT: ret844entry:845 %c = zext <16 x i8> %a to <16 x i16>846 ret <16 x i16> %c847}848 849define <16 x i32> @zext_v16i8_v16i32(<16 x i8> %a) {850; CHECK-SD-LABEL: zext_v16i8_v16i32:851; CHECK-SD: // %bb.0: // %entry852; CHECK-SD-NEXT: ushll v1.8h, v0.8b, #0853; CHECK-SD-NEXT: ushll2 v2.8h, v0.16b, #0854; CHECK-SD-NEXT: ushll v0.4s, v1.4h, #0855; CHECK-SD-NEXT: ushll2 v3.4s, v2.8h, #0856; CHECK-SD-NEXT: ushll2 v1.4s, v1.8h, #0857; CHECK-SD-NEXT: ushll v2.4s, v2.4h, #0858; CHECK-SD-NEXT: ret859;860; CHECK-GI-LABEL: zext_v16i8_v16i32:861; CHECK-GI: // %bb.0: // %entry862; CHECK-GI-NEXT: ushll v1.8h, v0.8b, #0863; CHECK-GI-NEXT: ushll2 v3.8h, v0.16b, #0864; CHECK-GI-NEXT: ushll v0.4s, v1.4h, #0865; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0866; CHECK-GI-NEXT: ushll v2.4s, v3.4h, #0867; CHECK-GI-NEXT: ushll2 v3.4s, v3.8h, #0868; CHECK-GI-NEXT: ret869entry:870 %c = zext <16 x i8> %a to <16 x i32>871 ret <16 x i32> %c872}873 874define <16 x i64> @zext_v16i8_v16i64(<16 x i8> %a) {875; CHECK-SD-LABEL: zext_v16i8_v16i64:876; CHECK-SD: // %bb.0: // %entry877; CHECK-SD-NEXT: ushll v1.8h, v0.8b, #0878; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #0879; CHECK-SD-NEXT: ushll v2.4s, v1.4h, #0880; CHECK-SD-NEXT: ushll2 v4.4s, v1.8h, #0881; CHECK-SD-NEXT: ushll v5.4s, v0.4h, #0882; CHECK-SD-NEXT: ushll2 v6.4s, v0.8h, #0883; CHECK-SD-NEXT: ushll2 v1.2d, v2.4s, #0884; CHECK-SD-NEXT: ushll v0.2d, v2.2s, #0885; CHECK-SD-NEXT: ushll2 v3.2d, v4.4s, #0886; CHECK-SD-NEXT: ushll v2.2d, v4.2s, #0887; CHECK-SD-NEXT: ushll v4.2d, v5.2s, #0888; CHECK-SD-NEXT: ushll2 v7.2d, v6.4s, #0889; CHECK-SD-NEXT: ushll2 v5.2d, v5.4s, #0890; CHECK-SD-NEXT: ushll v6.2d, v6.2s, #0891; CHECK-SD-NEXT: ret892;893; CHECK-GI-LABEL: zext_v16i8_v16i64:894; CHECK-GI: // %bb.0: // %entry895; CHECK-GI-NEXT: ushll v1.8h, v0.8b, #0896; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0897; CHECK-GI-NEXT: ushll v2.4s, v1.4h, #0898; CHECK-GI-NEXT: ushll2 v3.4s, v1.8h, #0899; CHECK-GI-NEXT: ushll v5.4s, v0.4h, #0900; CHECK-GI-NEXT: ushll2 v7.4s, v0.8h, #0901; CHECK-GI-NEXT: ushll v0.2d, v2.2s, #0902; CHECK-GI-NEXT: ushll2 v1.2d, v2.4s, #0903; CHECK-GI-NEXT: ushll v2.2d, v3.2s, #0904; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #0905; CHECK-GI-NEXT: ushll v4.2d, v5.2s, #0906; CHECK-GI-NEXT: ushll2 v5.2d, v5.4s, #0907; CHECK-GI-NEXT: ushll v6.2d, v7.2s, #0908; CHECK-GI-NEXT: ushll2 v7.2d, v7.4s, #0909; CHECK-GI-NEXT: ret910entry:911 %c = zext <16 x i8> %a to <16 x i64>912 ret <16 x i64> %c913}914 915define <16 x i32> @zext_v16i16_v16i32(<16 x i16> %a) {916; CHECK-SD-LABEL: zext_v16i16_v16i32:917; CHECK-SD: // %bb.0: // %entry918; CHECK-SD-NEXT: ushll v5.4s, v0.4h, #0919; CHECK-SD-NEXT: ushll2 v4.4s, v0.8h, #0920; CHECK-SD-NEXT: ushll2 v3.4s, v1.8h, #0921; CHECK-SD-NEXT: ushll v2.4s, v1.4h, #0922; CHECK-SD-NEXT: mov v0.16b, v5.16b923; CHECK-SD-NEXT: mov v1.16b, v4.16b924; CHECK-SD-NEXT: ret925;926; CHECK-GI-LABEL: zext_v16i16_v16i32:927; CHECK-GI: // %bb.0: // %entry928; CHECK-GI-NEXT: ushll v4.4s, v0.4h, #0929; CHECK-GI-NEXT: ushll2 v5.4s, v0.8h, #0930; CHECK-GI-NEXT: ushll v2.4s, v1.4h, #0931; CHECK-GI-NEXT: ushll2 v3.4s, v1.8h, #0932; CHECK-GI-NEXT: mov v0.16b, v4.16b933; CHECK-GI-NEXT: mov v1.16b, v5.16b934; CHECK-GI-NEXT: ret935entry:936 %c = zext <16 x i16> %a to <16 x i32>937 ret <16 x i32> %c938}939 940define <16 x i64> @zext_v16i16_v16i64(<16 x i16> %a) {941; CHECK-SD-LABEL: zext_v16i16_v16i64:942; CHECK-SD: // %bb.0: // %entry943; CHECK-SD-NEXT: ushll v2.4s, v0.4h, #0944; CHECK-SD-NEXT: ushll2 v4.4s, v0.8h, #0945; CHECK-SD-NEXT: ushll v5.4s, v1.4h, #0946; CHECK-SD-NEXT: ushll2 v6.4s, v1.8h, #0947; CHECK-SD-NEXT: ushll2 v1.2d, v2.4s, #0948; CHECK-SD-NEXT: ushll v0.2d, v2.2s, #0949; CHECK-SD-NEXT: ushll2 v3.2d, v4.4s, #0950; CHECK-SD-NEXT: ushll v2.2d, v4.2s, #0951; CHECK-SD-NEXT: ushll v4.2d, v5.2s, #0952; CHECK-SD-NEXT: ushll2 v7.2d, v6.4s, #0953; CHECK-SD-NEXT: ushll2 v5.2d, v5.4s, #0954; CHECK-SD-NEXT: ushll v6.2d, v6.2s, #0955; CHECK-SD-NEXT: ret956;957; CHECK-GI-LABEL: zext_v16i16_v16i64:958; CHECK-GI: // %bb.0: // %entry959; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0960; CHECK-GI-NEXT: ushll2 v3.4s, v0.8h, #0961; CHECK-GI-NEXT: ushll v5.4s, v1.4h, #0962; CHECK-GI-NEXT: ushll2 v7.4s, v1.8h, #0963; CHECK-GI-NEXT: ushll v0.2d, v2.2s, #0964; CHECK-GI-NEXT: ushll2 v1.2d, v2.4s, #0965; CHECK-GI-NEXT: ushll v2.2d, v3.2s, #0966; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #0967; CHECK-GI-NEXT: ushll v4.2d, v5.2s, #0968; CHECK-GI-NEXT: ushll2 v5.2d, v5.4s, #0969; CHECK-GI-NEXT: ushll v6.2d, v7.2s, #0970; CHECK-GI-NEXT: ushll2 v7.2d, v7.4s, #0971; CHECK-GI-NEXT: ret972entry:973 %c = zext <16 x i16> %a to <16 x i64>974 ret <16 x i64> %c975}976 977define <16 x i64> @zext_v16i32_v16i64(<16 x i32> %a) {978; CHECK-SD-LABEL: zext_v16i32_v16i64:979; CHECK-SD: // %bb.0: // %entry980; CHECK-SD-NEXT: ushll2 v17.2d, v0.4s, #0981; CHECK-SD-NEXT: ushll2 v16.2d, v1.4s, #0982; CHECK-SD-NEXT: ushll v18.2d, v1.2s, #0983; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0984; CHECK-SD-NEXT: ushll v4.2d, v2.2s, #0985; CHECK-SD-NEXT: ushll2 v5.2d, v2.4s, #0986; CHECK-SD-NEXT: ushll2 v7.2d, v3.4s, #0987; CHECK-SD-NEXT: ushll v6.2d, v3.2s, #0988; CHECK-SD-NEXT: mov v1.16b, v17.16b989; CHECK-SD-NEXT: mov v2.16b, v18.16b990; CHECK-SD-NEXT: mov v3.16b, v16.16b991; CHECK-SD-NEXT: ret992;993; CHECK-GI-LABEL: zext_v16i32_v16i64:994; CHECK-GI: // %bb.0: // %entry995; CHECK-GI-NEXT: ushll v16.2d, v0.2s, #0996; CHECK-GI-NEXT: ushll2 v17.2d, v0.4s, #0997; CHECK-GI-NEXT: ushll v18.2d, v1.2s, #0998; CHECK-GI-NEXT: ushll2 v19.2d, v1.4s, #0999; CHECK-GI-NEXT: ushll v4.2d, v2.2s, #01000; CHECK-GI-NEXT: ushll2 v5.2d, v2.4s, #01001; CHECK-GI-NEXT: ushll v6.2d, v3.2s, #01002; CHECK-GI-NEXT: ushll2 v7.2d, v3.4s, #01003; CHECK-GI-NEXT: mov v0.16b, v16.16b1004; CHECK-GI-NEXT: mov v1.16b, v17.16b1005; CHECK-GI-NEXT: mov v2.16b, v18.16b1006; CHECK-GI-NEXT: mov v3.16b, v19.16b1007; CHECK-GI-NEXT: ret1008entry:1009 %c = zext <16 x i32> %a to <16 x i64>1010 ret <16 x i64> %c1011}1012 1013define <16 x i16> @zext_v16i10_v16i16(<16 x i10> %a) {1014; CHECK-LABEL: zext_v16i10_v16i16:1015; CHECK: // %bb.0: // %entry1016; CHECK-NEXT: ldr w8, [sp]1017; CHECK-NEXT: fmov s0, w01018; CHECK-NEXT: ldr w9, [sp, #8]1019; CHECK-NEXT: fmov s1, w81020; CHECK-NEXT: ldr w8, [sp, #16]1021; CHECK-NEXT: mov v0.h[1], w11022; CHECK-NEXT: mov v1.h[1], w91023; CHECK-NEXT: mov v0.h[2], w21024; CHECK-NEXT: mov v1.h[2], w81025; CHECK-NEXT: ldr w8, [sp, #24]1026; CHECK-NEXT: mov v0.h[3], w31027; CHECK-NEXT: mov v1.h[3], w81028; CHECK-NEXT: ldr w8, [sp, #32]1029; CHECK-NEXT: mov v0.h[4], w41030; CHECK-NEXT: mov v1.h[4], w81031; CHECK-NEXT: ldr w8, [sp, #40]1032; CHECK-NEXT: mov v0.h[5], w51033; CHECK-NEXT: mov v1.h[5], w81034; CHECK-NEXT: ldr w8, [sp, #48]1035; CHECK-NEXT: mov v0.h[6], w61036; CHECK-NEXT: mov v1.h[6], w81037; CHECK-NEXT: ldr w8, [sp, #56]1038; CHECK-NEXT: mov v0.h[7], w71039; CHECK-NEXT: mov v1.h[7], w81040; CHECK-NEXT: bic v0.8h, #252, lsl #81041; CHECK-NEXT: bic v1.8h, #252, lsl #81042; CHECK-NEXT: ret1043entry:1044 %c = zext <16 x i10> %a to <16 x i16>1045 ret <16 x i16> %c1046}1047 1048define <16 x i32> @zext_v16i10_v16i32(<16 x i10> %a) {1049; CHECK-SD-LABEL: zext_v16i10_v16i32:1050; CHECK-SD: // %bb.0: // %entry1051; CHECK-SD-NEXT: ldr w8, [sp, #32]1052; CHECK-SD-NEXT: ldr w9, [sp]1053; CHECK-SD-NEXT: fmov s0, w01054; CHECK-SD-NEXT: fmov s1, w41055; CHECK-SD-NEXT: ldr w10, [sp, #40]1056; CHECK-SD-NEXT: ldr w11, [sp, #8]1057; CHECK-SD-NEXT: fmov s2, w91058; CHECK-SD-NEXT: fmov s3, w81059; CHECK-SD-NEXT: ldr w8, [sp, #48]1060; CHECK-SD-NEXT: mov v0.h[1], w11061; CHECK-SD-NEXT: ldr w9, [sp, #16]1062; CHECK-SD-NEXT: movi v4.4s, #3, msl #81063; CHECK-SD-NEXT: mov v1.h[1], w51064; CHECK-SD-NEXT: mov v2.h[1], w111065; CHECK-SD-NEXT: mov v3.h[1], w101066; CHECK-SD-NEXT: mov v0.h[2], w21067; CHECK-SD-NEXT: mov v1.h[2], w61068; CHECK-SD-NEXT: mov v2.h[2], w91069; CHECK-SD-NEXT: mov v3.h[2], w81070; CHECK-SD-NEXT: ldr w8, [sp, #56]1071; CHECK-SD-NEXT: ldr w9, [sp, #24]1072; CHECK-SD-NEXT: mov v0.h[3], w31073; CHECK-SD-NEXT: mov v1.h[3], w71074; CHECK-SD-NEXT: mov v2.h[3], w91075; CHECK-SD-NEXT: mov v3.h[3], w81076; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #01077; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #01078; CHECK-SD-NEXT: ushll v2.4s, v2.4h, #01079; CHECK-SD-NEXT: ushll v3.4s, v3.4h, #01080; CHECK-SD-NEXT: and v0.16b, v0.16b, v4.16b1081; CHECK-SD-NEXT: and v1.16b, v1.16b, v4.16b1082; CHECK-SD-NEXT: and v2.16b, v2.16b, v4.16b1083; CHECK-SD-NEXT: and v3.16b, v3.16b, v4.16b1084; CHECK-SD-NEXT: ret1085;1086; CHECK-GI-LABEL: zext_v16i10_v16i32:1087; CHECK-GI: // %bb.0: // %entry1088; CHECK-GI-NEXT: ldr w8, [sp]1089; CHECK-GI-NEXT: ldr w9, [sp, #32]1090; CHECK-GI-NEXT: fmov s0, w01091; CHECK-GI-NEXT: fmov s1, w41092; CHECK-GI-NEXT: ldr w10, [sp, #8]1093; CHECK-GI-NEXT: ldr w11, [sp, #40]1094; CHECK-GI-NEXT: fmov s2, w81095; CHECK-GI-NEXT: fmov s3, w91096; CHECK-GI-NEXT: ldr w8, [sp, #16]1097; CHECK-GI-NEXT: mov v0.h[1], w11098; CHECK-GI-NEXT: ldr w9, [sp, #48]1099; CHECK-GI-NEXT: movi v4.4s, #3, msl #81100; CHECK-GI-NEXT: mov v1.h[1], w51101; CHECK-GI-NEXT: mov v2.h[1], w101102; CHECK-GI-NEXT: mov v3.h[1], w111103; CHECK-GI-NEXT: mov v0.h[2], w21104; CHECK-GI-NEXT: mov v1.h[2], w61105; CHECK-GI-NEXT: mov v2.h[2], w81106; CHECK-GI-NEXT: mov v3.h[2], w91107; CHECK-GI-NEXT: ldr w8, [sp, #24]1108; CHECK-GI-NEXT: ldr w9, [sp, #56]1109; CHECK-GI-NEXT: mov v0.h[3], w31110; CHECK-GI-NEXT: mov v1.h[3], w71111; CHECK-GI-NEXT: mov v2.h[3], w81112; CHECK-GI-NEXT: mov v3.h[3], w91113; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #01114; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #01115; CHECK-GI-NEXT: ushll v2.4s, v2.4h, #01116; CHECK-GI-NEXT: ushll v3.4s, v3.4h, #01117; CHECK-GI-NEXT: and v0.16b, v0.16b, v4.16b1118; CHECK-GI-NEXT: and v1.16b, v1.16b, v4.16b1119; CHECK-GI-NEXT: and v2.16b, v2.16b, v4.16b1120; CHECK-GI-NEXT: and v3.16b, v3.16b, v4.16b1121; CHECK-GI-NEXT: ret1122entry:1123 %c = zext <16 x i10> %a to <16 x i32>1124 ret <16 x i32> %c1125}1126 1127define <16 x i64> @zext_v16i10_v16i64(<16 x i10> %a) {1128; CHECK-SD-LABEL: zext_v16i10_v16i64:1129; CHECK-SD: // %bb.0: // %entry1130; CHECK-SD-NEXT: fmov s0, w21131; CHECK-SD-NEXT: fmov s1, w01132; CHECK-SD-NEXT: ldr s2, [sp]1133; CHECK-SD-NEXT: fmov s3, w41134; CHECK-SD-NEXT: fmov s4, w61135; CHECK-SD-NEXT: add x9, sp, #81136; CHECK-SD-NEXT: ldr s5, [sp, #16]1137; CHECK-SD-NEXT: ldr s6, [sp, #32]1138; CHECK-SD-NEXT: ldr s7, [sp, #48]1139; CHECK-SD-NEXT: mov v1.s[1], w11140; CHECK-SD-NEXT: mov v0.s[1], w31141; CHECK-SD-NEXT: ld1 { v2.s }[1], [x9]1142; CHECK-SD-NEXT: mov v3.s[1], w51143; CHECK-SD-NEXT: mov v4.s[1], w71144; CHECK-SD-NEXT: add x9, sp, #241145; CHECK-SD-NEXT: add x10, sp, #401146; CHECK-SD-NEXT: add x11, sp, #561147; CHECK-SD-NEXT: ld1 { v5.s }[1], [x9]1148; CHECK-SD-NEXT: ld1 { v6.s }[1], [x10]1149; CHECK-SD-NEXT: ld1 { v7.s }[1], [x11]1150; CHECK-SD-NEXT: mov w8, #1023 // =0x3ff1151; CHECK-SD-NEXT: ushll v1.2d, v1.2s, #01152; CHECK-SD-NEXT: dup v16.2d, x81153; CHECK-SD-NEXT: ushll v17.2d, v0.2s, #01154; CHECK-SD-NEXT: ushll v3.2d, v3.2s, #01155; CHECK-SD-NEXT: ushll v4.2d, v4.2s, #01156; CHECK-SD-NEXT: ushll v18.2d, v2.2s, #01157; CHECK-SD-NEXT: ushll v5.2d, v5.2s, #01158; CHECK-SD-NEXT: ushll v6.2d, v6.2s, #01159; CHECK-SD-NEXT: ushll v7.2d, v7.2s, #01160; CHECK-SD-NEXT: and v0.16b, v1.16b, v16.16b1161; CHECK-SD-NEXT: and v1.16b, v17.16b, v16.16b1162; CHECK-SD-NEXT: and v2.16b, v3.16b, v16.16b1163; CHECK-SD-NEXT: and v3.16b, v4.16b, v16.16b1164; CHECK-SD-NEXT: and v4.16b, v18.16b, v16.16b1165; CHECK-SD-NEXT: and v5.16b, v5.16b, v16.16b1166; CHECK-SD-NEXT: and v6.16b, v6.16b, v16.16b1167; CHECK-SD-NEXT: and v7.16b, v7.16b, v16.16b1168; CHECK-SD-NEXT: ret1169;1170; CHECK-GI-LABEL: zext_v16i10_v16i64:1171; CHECK-GI: // %bb.0: // %entry1172; CHECK-GI-NEXT: fmov s16, w01173; CHECK-GI-NEXT: fmov s17, w21174; CHECK-GI-NEXT: ldr s1, [sp]1175; CHECK-GI-NEXT: fmov s18, w41176; CHECK-GI-NEXT: fmov s19, w61177; CHECK-GI-NEXT: ldr s3, [sp, #8]1178; CHECK-GI-NEXT: ldr s0, [sp, #16]1179; CHECK-GI-NEXT: ldr s4, [sp, #24]1180; CHECK-GI-NEXT: ldr s2, [sp, #32]1181; CHECK-GI-NEXT: ldr s5, [sp, #40]1182; CHECK-GI-NEXT: ldr s6, [sp, #48]1183; CHECK-GI-NEXT: ldr s7, [sp, #56]1184; CHECK-GI-NEXT: mov v16.s[1], w11185; CHECK-GI-NEXT: mov v17.s[1], w31186; CHECK-GI-NEXT: mov v18.s[1], w51187; CHECK-GI-NEXT: mov v19.s[1], w71188; CHECK-GI-NEXT: mov v1.s[1], v3.s[0]1189; CHECK-GI-NEXT: mov v0.s[1], v4.s[0]1190; CHECK-GI-NEXT: mov v2.s[1], v5.s[0]1191; CHECK-GI-NEXT: mov v6.s[1], v7.s[0]1192; CHECK-GI-NEXT: adrp x8, .LCPI54_01193; CHECK-GI-NEXT: ushll v3.2d, v16.2s, #01194; CHECK-GI-NEXT: ushll v4.2d, v17.2s, #01195; CHECK-GI-NEXT: ushll v5.2d, v18.2s, #01196; CHECK-GI-NEXT: ushll v7.2d, v19.2s, #01197; CHECK-GI-NEXT: ushll v16.2d, v1.2s, #01198; CHECK-GI-NEXT: ushll v18.2d, v0.2s, #01199; CHECK-GI-NEXT: ushll v19.2d, v2.2s, #01200; CHECK-GI-NEXT: ushll v20.2d, v6.2s, #01201; CHECK-GI-NEXT: ldr q17, [x8, :lo12:.LCPI54_0]1202; CHECK-GI-NEXT: and v0.16b, v3.16b, v17.16b1203; CHECK-GI-NEXT: and v1.16b, v4.16b, v17.16b1204; CHECK-GI-NEXT: and v2.16b, v5.16b, v17.16b1205; CHECK-GI-NEXT: and v3.16b, v7.16b, v17.16b1206; CHECK-GI-NEXT: and v4.16b, v16.16b, v17.16b1207; CHECK-GI-NEXT: and v5.16b, v18.16b, v17.16b1208; CHECK-GI-NEXT: and v6.16b, v19.16b, v17.16b1209; CHECK-GI-NEXT: and v7.16b, v20.16b, v17.16b1210; CHECK-GI-NEXT: ret1211entry:1212 %c = zext <16 x i10> %a to <16 x i64>1213 ret <16 x i64> %c1214}1215 1216define <2 x i128> @zext_v2i64_v2i128(<2 x i64> %a) {1217; CHECK-SD-LABEL: zext_v2i64_v2i128:1218; CHECK-SD: // %bb.0: // %entry1219; CHECK-SD-NEXT: mov x2, v0.d[1]1220; CHECK-SD-NEXT: fmov x0, d01221; CHECK-SD-NEXT: mov x1, xzr1222; CHECK-SD-NEXT: mov x3, xzr1223; CHECK-SD-NEXT: ret1224;1225; CHECK-GI-LABEL: zext_v2i64_v2i128:1226; CHECK-GI: // %bb.0: // %entry1227; CHECK-GI-NEXT: mov d1, v0.d[1]1228; CHECK-GI-NEXT: fmov x0, d01229; CHECK-GI-NEXT: mov x1, xzr1230; CHECK-GI-NEXT: mov x3, xzr1231; CHECK-GI-NEXT: fmov x2, d11232; CHECK-GI-NEXT: ret1233entry:1234 %c = zext <2 x i64> %a to <2 x i128>1235 ret <2 x i128> %c1236}1237