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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck -check-prefix=GFX7 %s3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s6; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s7 8define <2 x i16> @v_add_v2i16(<2 x i16> %a, <2 x i16> %b) {9; GFX7-LABEL: v_add_v2i16:10; GFX7: ; %bb.0:11; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v213; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v314; GFX7-NEXT: s_setpc_b64 s[30:31]15;16; GFX9-LABEL: v_add_v2i16:17; GFX9: ; %bb.0:18; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)19; GFX9-NEXT: v_pk_add_u16 v0, v0, v120; GFX9-NEXT: s_setpc_b64 s[30:31]21;22; GFX8-LABEL: v_add_v2i16:23; GFX8: ; %bb.0:24; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)25; GFX8-NEXT: v_add_u16_e32 v2, v0, v126; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_127; GFX8-NEXT: v_or_b32_e32 v0, v2, v028; GFX8-NEXT: s_setpc_b64 s[30:31]29;30; GFX10-LABEL: v_add_v2i16:31; GFX10: ; %bb.0:32; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; GFX10-NEXT: v_pk_add_u16 v0, v0, v134; GFX10-NEXT: s_setpc_b64 s[30:31]35 %add = add <2 x i16> %a, %b36 ret <2 x i16> %add37}38 39define <2 x i16> @v_add_v2i16_fneg_lhs(<2 x half> %a, <2 x i16> %b) {40; GFX7-LABEL: v_add_v2i16_fneg_lhs:41; GFX7: ; %bb.0:42; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)43; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v144; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v045; GFX7-NEXT: v_or_b32_e32 v0, v1, v046; GFX7-NEXT: v_xor_b32_e32 v0, 0x80008000, v047; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v048; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v249; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v350; GFX7-NEXT: s_setpc_b64 s[30:31]51;52; GFX9-LABEL: v_add_v2i16_fneg_lhs:53; GFX9: ; %bb.0:54; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)55; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[1,0] neg_hi:[1,0]56; GFX9-NEXT: s_setpc_b64 s[30:31]57;58; GFX8-LABEL: v_add_v2i16_fneg_lhs:59; GFX8: ; %bb.0:60; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)61; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v062; GFX8-NEXT: v_add_u16_e32 v2, v0, v163; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_164; GFX8-NEXT: v_or_b32_e32 v0, v2, v065; GFX8-NEXT: s_setpc_b64 s[30:31]66;67; GFX10-LABEL: v_add_v2i16_fneg_lhs:68; GFX10: ; %bb.0:69; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)70; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[1,0] neg_hi:[1,0]71; GFX10-NEXT: s_setpc_b64 s[30:31]72 %neg.a = fneg <2 x half> %a73 %cast.neg.a = bitcast <2 x half> %neg.a to <2 x i16>74 %add = add <2 x i16> %cast.neg.a, %b75 ret <2 x i16> %add76}77 78define <2 x i16> @v_add_v2i16_fneg_rhs(<2 x i16> %a, <2 x half> %b) {79; GFX7-LABEL: v_add_v2i16_fneg_rhs:80; GFX7: ; %bb.0:81; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)82; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v383; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v284; GFX7-NEXT: v_or_b32_e32 v2, v3, v285; GFX7-NEXT: v_xor_b32_e32 v2, 0x80008000, v286; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v287; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v288; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v389; GFX7-NEXT: s_setpc_b64 s[30:31]90;91; GFX9-LABEL: v_add_v2i16_fneg_rhs:92; GFX9: ; %bb.0:93; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)94; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]95; GFX9-NEXT: s_setpc_b64 s[30:31]96;97; GFX8-LABEL: v_add_v2i16_fneg_rhs:98; GFX8: ; %bb.0:99; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)100; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1101; GFX8-NEXT: v_add_u16_e32 v2, v0, v1102; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1103; GFX8-NEXT: v_or_b32_e32 v0, v2, v0104; GFX8-NEXT: s_setpc_b64 s[30:31]105;106; GFX10-LABEL: v_add_v2i16_fneg_rhs:107; GFX10: ; %bb.0:108; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)109; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]110; GFX10-NEXT: s_setpc_b64 s[30:31]111 %neg.b = fneg <2 x half> %b112 %cast.neg.b = bitcast <2 x half> %neg.b to <2 x i16>113 %add = add <2 x i16> %a, %cast.neg.b114 ret <2 x i16> %add115}116 117define <2 x i16> @v_add_v2i16_fneg_lhs_fneg_rhs(<2 x half> %a, <2 x half> %b) {118; GFX7-LABEL: v_add_v2i16_fneg_lhs_fneg_rhs:119; GFX7: ; %bb.0:120; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)121; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1122; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0123; GFX7-NEXT: v_or_b32_e32 v0, v1, v0124; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v3125; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2126; GFX7-NEXT: v_or_b32_e32 v1, v1, v2127; GFX7-NEXT: v_xor_b32_e32 v0, 0x80008000, v0128; GFX7-NEXT: v_xor_b32_e32 v1, 0x80008000, v1129; GFX7-NEXT: v_lshrrev_b32_e32 v2, 16, v0130; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v1131; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1132; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v3133; GFX7-NEXT: s_setpc_b64 s[30:31]134;135; GFX9-LABEL: v_add_v2i16_fneg_lhs_fneg_rhs:136; GFX9: ; %bb.0:137; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)138; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[1,1] neg_hi:[1,1]139; GFX9-NEXT: s_setpc_b64 s[30:31]140;141; GFX8-LABEL: v_add_v2i16_fneg_lhs_fneg_rhs:142; GFX8: ; %bb.0:143; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)144; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0145; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1146; GFX8-NEXT: v_add_u16_e32 v2, v0, v1147; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1148; GFX8-NEXT: v_or_b32_e32 v0, v2, v0149; GFX8-NEXT: s_setpc_b64 s[30:31]150;151; GFX10-LABEL: v_add_v2i16_fneg_lhs_fneg_rhs:152; GFX10: ; %bb.0:153; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)154; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[1,1] neg_hi:[1,1]155; GFX10-NEXT: s_setpc_b64 s[30:31]156 %neg.a = fneg <2 x half> %a157 %neg.b = fneg <2 x half> %b158 %cast.neg.a = bitcast <2 x half> %neg.a to <2 x i16>159 %cast.neg.b = bitcast <2 x half> %neg.b to <2 x i16>160 %add = add <2 x i16> %cast.neg.a, %cast.neg.b161 ret <2 x i16> %add162}163 164define <2 x i16> @v_add_v2i16_neg_inline_imm_splat(<2 x i16> %a) {165; GFX7-LABEL: v_add_v2i16_neg_inline_imm_splat:166; GFX7: ; %bb.0:167; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)168; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc0, v0169; GFX7-NEXT: v_add_i32_e32 v1, vcc, 0xffffffc0, v1170; GFX7-NEXT: s_setpc_b64 s[30:31]171;172; GFX9-LABEL: v_add_v2i16_neg_inline_imm_splat:173; GFX9: ; %bb.0:174; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)175; GFX9-NEXT: v_pk_sub_u16 v0, v0, 64 op_sel_hi:[1,0]176; GFX9-NEXT: s_setpc_b64 s[30:31]177;178; GFX8-LABEL: v_add_v2i16_neg_inline_imm_splat:179; GFX8: ; %bb.0:180; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)181; GFX8-NEXT: v_not_b32_e32 v1, 63182; GFX8-NEXT: v_add_u16_e32 v2, 0xffc0, v0183; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD184; GFX8-NEXT: v_or_b32_e32 v0, v2, v0185; GFX8-NEXT: s_setpc_b64 s[30:31]186;187; GFX10-LABEL: v_add_v2i16_neg_inline_imm_splat:188; GFX10: ; %bb.0:189; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)190; GFX10-NEXT: v_pk_sub_u16 v0, v0, 64 op_sel_hi:[1,0]191; GFX10-NEXT: s_setpc_b64 s[30:31]192 %add = add <2 x i16> %a, <i16 -64, i16 -64>193 ret <2 x i16> %add194}195 196define <2 x i16> @v_add_v2i16_neg_inline_imm_lo(<2 x i16> %a) {197; GFX7-LABEL: v_add_v2i16_neg_inline_imm_lo:198; GFX7: ; %bb.0:199; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)200; GFX7-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc0, v0201; GFX7-NEXT: v_add_i32_e32 v1, vcc, 4, v1202; GFX7-NEXT: s_setpc_b64 s[30:31]203;204; GFX9-LABEL: v_add_v2i16_neg_inline_imm_lo:205; GFX9: ; %bb.0:206; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)207; GFX9-NEXT: v_mov_b32_e32 v1, 0x4ffc0208; GFX9-NEXT: v_pk_add_u16 v0, v0, v1209; GFX9-NEXT: s_setpc_b64 s[30:31]210;211; GFX8-LABEL: v_add_v2i16_neg_inline_imm_lo:212; GFX8: ; %bb.0:213; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)214; GFX8-NEXT: v_mov_b32_e32 v2, 4215; GFX8-NEXT: v_add_u16_e32 v1, 0xffc0, v0216; GFX8-NEXT: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD217; GFX8-NEXT: v_or_b32_e32 v0, v1, v0218; GFX8-NEXT: s_setpc_b64 s[30:31]219;220; GFX10-LABEL: v_add_v2i16_neg_inline_imm_lo:221; GFX10: ; %bb.0:222; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)223; GFX10-NEXT: v_pk_add_u16 v0, 0x4ffc0, v0224; GFX10-NEXT: s_setpc_b64 s[30:31]225 %add = add <2 x i16> %a, <i16 -64, i16 4>226 ret <2 x i16> %add227}228 229define <2 x i16> @v_add_v2i16_neg_inline_imm_hi(<2 x i16> %a) {230; GFX7-LABEL: v_add_v2i16_neg_inline_imm_hi:231; GFX7: ; %bb.0:232; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)233; GFX7-NEXT: v_add_i32_e32 v0, vcc, 4, v0234; GFX7-NEXT: v_add_i32_e32 v1, vcc, 0xffffffc0, v1235; GFX7-NEXT: s_setpc_b64 s[30:31]236;237; GFX9-LABEL: v_add_v2i16_neg_inline_imm_hi:238; GFX9: ; %bb.0:239; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)240; GFX9-NEXT: v_mov_b32_e32 v1, 0xffc00004241; GFX9-NEXT: v_pk_add_u16 v0, v0, v1242; GFX9-NEXT: s_setpc_b64 s[30:31]243;244; GFX8-LABEL: v_add_v2i16_neg_inline_imm_hi:245; GFX8: ; %bb.0:246; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)247; GFX8-NEXT: v_not_b32_e32 v1, 63248; GFX8-NEXT: v_add_u16_e32 v2, 4, v0249; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD250; GFX8-NEXT: v_or_b32_e32 v0, v2, v0251; GFX8-NEXT: s_setpc_b64 s[30:31]252;253; GFX10-LABEL: v_add_v2i16_neg_inline_imm_hi:254; GFX10: ; %bb.0:255; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)256; GFX10-NEXT: v_pk_add_u16 v0, 0xffc00004, v0257; GFX10-NEXT: s_setpc_b64 s[30:31]258 %add = add <2 x i16> %a, <i16 4, i16 -64>259 ret <2 x i16> %add260}261 262define amdgpu_ps i32 @s_add_v2i16_neg_inline_imm_splat(<2 x i16> inreg %a) {263; GFX7-LABEL: s_add_v2i16_neg_inline_imm_splat:264; GFX7: ; %bb.0:265; GFX7-NEXT: s_sub_i32 s1, s1, 64266; GFX7-NEXT: s_sub_i32 s0, s0, 64267; GFX7-NEXT: s_and_b32 s1, s1, 0xffff268; GFX7-NEXT: s_and_b32 s0, s0, 0xffff269; GFX7-NEXT: s_lshl_b32 s1, s1, 16270; GFX7-NEXT: s_or_b32 s0, s0, s1271; GFX7-NEXT: ; return to shader part epilog272;273; GFX9-LABEL: s_add_v2i16_neg_inline_imm_splat:274; GFX9: ; %bb.0:275; GFX9-NEXT: s_lshr_b32 s1, s0, 16276; GFX9-NEXT: s_add_i32 s0, s0, 0xffc0ffc0277; GFX9-NEXT: s_add_i32 s1, s1, 0xffc0278; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1279; GFX9-NEXT: ; return to shader part epilog280;281; GFX8-LABEL: s_add_v2i16_neg_inline_imm_splat:282; GFX8: ; %bb.0:283; GFX8-NEXT: s_lshr_b32 s1, s0, 16284; GFX8-NEXT: s_add_i32 s1, s1, 0xffc0285; GFX8-NEXT: s_add_i32 s0, s0, 0xffc0286; GFX8-NEXT: s_and_b32 s1, 0xffff, s1287; GFX8-NEXT: s_and_b32 s0, 0xffff, s0288; GFX8-NEXT: s_lshl_b32 s1, s1, 16289; GFX8-NEXT: s_or_b32 s0, s0, s1290; GFX8-NEXT: ; return to shader part epilog291;292; GFX10-LABEL: s_add_v2i16_neg_inline_imm_splat:293; GFX10: ; %bb.0:294; GFX10-NEXT: s_lshr_b32 s1, s0, 16295; GFX10-NEXT: s_add_i32 s0, s0, 0xffc0ffc0296; GFX10-NEXT: s_add_i32 s1, s1, 0xffc0297; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1298; GFX10-NEXT: ; return to shader part epilog299 %add = add <2 x i16> %a, <i16 -64, i16 -64>300 %cast = bitcast <2 x i16> %add to i32301 ret i32 %cast302}303 304define amdgpu_ps i32 @s_add_v2i16_neg_inline_imm_lo(<2 x i16> inreg %a) {305; GFX7-LABEL: s_add_v2i16_neg_inline_imm_lo:306; GFX7: ; %bb.0:307; GFX7-NEXT: s_add_i32 s1, s1, 4308; GFX7-NEXT: s_sub_i32 s0, s0, 64309; GFX7-NEXT: s_and_b32 s1, s1, 0xffff310; GFX7-NEXT: s_and_b32 s0, s0, 0xffff311; GFX7-NEXT: s_lshl_b32 s1, s1, 16312; GFX7-NEXT: s_or_b32 s0, s0, s1313; GFX7-NEXT: ; return to shader part epilog314;315; GFX9-LABEL: s_add_v2i16_neg_inline_imm_lo:316; GFX9: ; %bb.0:317; GFX9-NEXT: s_lshr_b32 s1, s0, 16318; GFX9-NEXT: s_add_i32 s0, s0, 0x4ffc0319; GFX9-NEXT: s_add_i32 s1, s1, 4320; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1321; GFX9-NEXT: ; return to shader part epilog322;323; GFX8-LABEL: s_add_v2i16_neg_inline_imm_lo:324; GFX8: ; %bb.0:325; GFX8-NEXT: s_lshr_b32 s1, s0, 16326; GFX8-NEXT: s_add_i32 s1, s1, 4327; GFX8-NEXT: s_add_i32 s0, s0, 0xffc0328; GFX8-NEXT: s_and_b32 s1, 0xffff, s1329; GFX8-NEXT: s_and_b32 s0, 0xffff, s0330; GFX8-NEXT: s_lshl_b32 s1, s1, 16331; GFX8-NEXT: s_or_b32 s0, s0, s1332; GFX8-NEXT: ; return to shader part epilog333;334; GFX10-LABEL: s_add_v2i16_neg_inline_imm_lo:335; GFX10: ; %bb.0:336; GFX10-NEXT: s_lshr_b32 s1, s0, 16337; GFX10-NEXT: s_add_i32 s0, s0, 0x4ffc0338; GFX10-NEXT: s_add_i32 s1, s1, 4339; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1340; GFX10-NEXT: ; return to shader part epilog341 %add = add <2 x i16> %a, <i16 -64, i16 4>342 %cast = bitcast <2 x i16> %add to i32343 ret i32 %cast344}345 346define amdgpu_ps i32 @s_add_v2i16_neg_inline_imm_hi(<2 x i16> inreg %a) {347; GFX7-LABEL: s_add_v2i16_neg_inline_imm_hi:348; GFX7: ; %bb.0:349; GFX7-NEXT: s_sub_i32 s1, s1, 64350; GFX7-NEXT: s_add_i32 s0, s0, 4351; GFX7-NEXT: s_and_b32 s1, s1, 0xffff352; GFX7-NEXT: s_and_b32 s0, s0, 0xffff353; GFX7-NEXT: s_lshl_b32 s1, s1, 16354; GFX7-NEXT: s_or_b32 s0, s0, s1355; GFX7-NEXT: ; return to shader part epilog356;357; GFX9-LABEL: s_add_v2i16_neg_inline_imm_hi:358; GFX9: ; %bb.0:359; GFX9-NEXT: s_lshr_b32 s1, s0, 16360; GFX9-NEXT: s_add_i32 s0, s0, 0xffc00004361; GFX9-NEXT: s_add_i32 s1, s1, 0xffc0362; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1363; GFX9-NEXT: ; return to shader part epilog364;365; GFX8-LABEL: s_add_v2i16_neg_inline_imm_hi:366; GFX8: ; %bb.0:367; GFX8-NEXT: s_lshr_b32 s1, s0, 16368; GFX8-NEXT: s_add_i32 s1, s1, 0xffc0369; GFX8-NEXT: s_add_i32 s0, s0, 4370; GFX8-NEXT: s_and_b32 s1, 0xffff, s1371; GFX8-NEXT: s_and_b32 s0, 0xffff, s0372; GFX8-NEXT: s_lshl_b32 s1, s1, 16373; GFX8-NEXT: s_or_b32 s0, s0, s1374; GFX8-NEXT: ; return to shader part epilog375;376; GFX10-LABEL: s_add_v2i16_neg_inline_imm_hi:377; GFX10: ; %bb.0:378; GFX10-NEXT: s_lshr_b32 s1, s0, 16379; GFX10-NEXT: s_add_i32 s0, s0, 0xffc00004380; GFX10-NEXT: s_add_i32 s1, s1, 0xffc0381; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1382; GFX10-NEXT: ; return to shader part epilog383 %add = add <2 x i16> %a, <i16 4, i16 -64>384 %cast = bitcast <2 x i16> %add to i32385 ret i32 %cast386}387 388define amdgpu_ps i32 @s_add_v2i16(<2 x i16> inreg %a, <2 x i16> inreg %b) {389; GFX7-LABEL: s_add_v2i16:390; GFX7: ; %bb.0:391; GFX7-NEXT: s_add_i32 s1, s1, s3392; GFX7-NEXT: s_add_i32 s0, s0, s2393; GFX7-NEXT: s_and_b32 s1, s1, 0xffff394; GFX7-NEXT: s_and_b32 s0, s0, 0xffff395; GFX7-NEXT: s_lshl_b32 s1, s1, 16396; GFX7-NEXT: s_or_b32 s0, s0, s1397; GFX7-NEXT: ; return to shader part epilog398;399; GFX9-LABEL: s_add_v2i16:400; GFX9: ; %bb.0:401; GFX9-NEXT: s_lshr_b32 s2, s0, 16402; GFX9-NEXT: s_lshr_b32 s3, s1, 16403; GFX9-NEXT: s_add_i32 s0, s0, s1404; GFX9-NEXT: s_add_i32 s2, s2, s3405; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2406; GFX9-NEXT: ; return to shader part epilog407;408; GFX8-LABEL: s_add_v2i16:409; GFX8: ; %bb.0:410; GFX8-NEXT: s_lshr_b32 s2, s0, 16411; GFX8-NEXT: s_lshr_b32 s3, s1, 16412; GFX8-NEXT: s_add_i32 s2, s2, s3413; GFX8-NEXT: s_add_i32 s0, s0, s1414; GFX8-NEXT: s_and_b32 s1, 0xffff, s2415; GFX8-NEXT: s_and_b32 s0, 0xffff, s0416; GFX8-NEXT: s_lshl_b32 s1, s1, 16417; GFX8-NEXT: s_or_b32 s0, s0, s1418; GFX8-NEXT: ; return to shader part epilog419;420; GFX10-LABEL: s_add_v2i16:421; GFX10: ; %bb.0:422; GFX10-NEXT: s_lshr_b32 s2, s0, 16423; GFX10-NEXT: s_lshr_b32 s3, s1, 16424; GFX10-NEXT: s_add_i32 s0, s0, s1425; GFX10-NEXT: s_add_i32 s2, s2, s3426; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2427; GFX10-NEXT: ; return to shader part epilog428 %add = add <2 x i16> %a, %b429 %cast = bitcast <2 x i16> %add to i32430 ret i32 %cast431}432 433define amdgpu_ps i32 @s_add_v2i16_fneg_lhs(<2 x half> inreg %a, <2 x i16> inreg %b) {434; GFX7-LABEL: s_add_v2i16_fneg_lhs:435; GFX7: ; %bb.0:436; GFX7-NEXT: s_lshl_b32 s1, s1, 16437; GFX7-NEXT: s_and_b32 s0, s0, 0xffff438; GFX7-NEXT: s_or_b32 s0, s1, s0439; GFX7-NEXT: s_xor_b32 s0, s0, 0x80008000440; GFX7-NEXT: s_lshr_b32 s1, s0, 16441; GFX7-NEXT: s_add_i32 s1, s1, s3442; GFX7-NEXT: s_add_i32 s0, s0, s2443; GFX7-NEXT: s_and_b32 s1, s1, 0xffff444; GFX7-NEXT: s_and_b32 s0, s0, 0xffff445; GFX7-NEXT: s_lshl_b32 s1, s1, 16446; GFX7-NEXT: s_or_b32 s0, s0, s1447; GFX7-NEXT: ; return to shader part epilog448;449; GFX9-LABEL: s_add_v2i16_fneg_lhs:450; GFX9: ; %bb.0:451; GFX9-NEXT: s_xor_b32 s0, s0, 0x80008000452; GFX9-NEXT: s_lshr_b32 s2, s0, 16453; GFX9-NEXT: s_lshr_b32 s3, s1, 16454; GFX9-NEXT: s_add_i32 s0, s0, s1455; GFX9-NEXT: s_add_i32 s2, s2, s3456; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2457; GFX9-NEXT: ; return to shader part epilog458;459; GFX8-LABEL: s_add_v2i16_fneg_lhs:460; GFX8: ; %bb.0:461; GFX8-NEXT: s_xor_b32 s0, s0, 0x80008000462; GFX8-NEXT: s_lshr_b32 s2, s0, 16463; GFX8-NEXT: s_lshr_b32 s3, s1, 16464; GFX8-NEXT: s_add_i32 s2, s2, s3465; GFX8-NEXT: s_add_i32 s0, s0, s1466; GFX8-NEXT: s_and_b32 s1, 0xffff, s2467; GFX8-NEXT: s_and_b32 s0, 0xffff, s0468; GFX8-NEXT: s_lshl_b32 s1, s1, 16469; GFX8-NEXT: s_or_b32 s0, s0, s1470; GFX8-NEXT: ; return to shader part epilog471;472; GFX10-LABEL: s_add_v2i16_fneg_lhs:473; GFX10: ; %bb.0:474; GFX10-NEXT: s_xor_b32 s0, s0, 0x80008000475; GFX10-NEXT: s_lshr_b32 s3, s1, 16476; GFX10-NEXT: s_lshr_b32 s2, s0, 16477; GFX10-NEXT: s_add_i32 s0, s0, s1478; GFX10-NEXT: s_add_i32 s2, s2, s3479; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2480; GFX10-NEXT: ; return to shader part epilog481 %neg.a = fneg <2 x half> %a482 %cast.neg.a = bitcast <2 x half> %neg.a to <2 x i16>483 %add = add <2 x i16> %cast.neg.a, %b484 %cast = bitcast <2 x i16> %add to i32485 ret i32 %cast486}487 488define amdgpu_ps i32 @s_add_v2i16_fneg_rhs(<2 x i16> inreg %a, <2 x half> inreg %b) {489; GFX7-LABEL: s_add_v2i16_fneg_rhs:490; GFX7: ; %bb.0:491; GFX7-NEXT: s_lshl_b32 s3, s3, 16492; GFX7-NEXT: s_and_b32 s2, s2, 0xffff493; GFX7-NEXT: s_or_b32 s2, s3, s2494; GFX7-NEXT: s_xor_b32 s2, s2, 0x80008000495; GFX7-NEXT: s_lshr_b32 s3, s2, 16496; GFX7-NEXT: s_add_i32 s1, s1, s3497; GFX7-NEXT: s_add_i32 s0, s0, s2498; GFX7-NEXT: s_and_b32 s1, s1, 0xffff499; GFX7-NEXT: s_and_b32 s0, s0, 0xffff500; GFX7-NEXT: s_lshl_b32 s1, s1, 16501; GFX7-NEXT: s_or_b32 s0, s0, s1502; GFX7-NEXT: ; return to shader part epilog503;504; GFX9-LABEL: s_add_v2i16_fneg_rhs:505; GFX9: ; %bb.0:506; GFX9-NEXT: s_xor_b32 s1, s1, 0x80008000507; GFX9-NEXT: s_lshr_b32 s2, s0, 16508; GFX9-NEXT: s_lshr_b32 s3, s1, 16509; GFX9-NEXT: s_add_i32 s0, s0, s1510; GFX9-NEXT: s_add_i32 s2, s2, s3511; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2512; GFX9-NEXT: ; return to shader part epilog513;514; GFX8-LABEL: s_add_v2i16_fneg_rhs:515; GFX8: ; %bb.0:516; GFX8-NEXT: s_xor_b32 s1, s1, 0x80008000517; GFX8-NEXT: s_lshr_b32 s2, s0, 16518; GFX8-NEXT: s_lshr_b32 s3, s1, 16519; GFX8-NEXT: s_add_i32 s2, s2, s3520; GFX8-NEXT: s_add_i32 s0, s0, s1521; GFX8-NEXT: s_and_b32 s1, 0xffff, s2522; GFX8-NEXT: s_and_b32 s0, 0xffff, s0523; GFX8-NEXT: s_lshl_b32 s1, s1, 16524; GFX8-NEXT: s_or_b32 s0, s0, s1525; GFX8-NEXT: ; return to shader part epilog526;527; GFX10-LABEL: s_add_v2i16_fneg_rhs:528; GFX10: ; %bb.0:529; GFX10-NEXT: s_xor_b32 s1, s1, 0x80008000530; GFX10-NEXT: s_lshr_b32 s2, s0, 16531; GFX10-NEXT: s_lshr_b32 s3, s1, 16532; GFX10-NEXT: s_add_i32 s0, s0, s1533; GFX10-NEXT: s_add_i32 s2, s2, s3534; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2535; GFX10-NEXT: ; return to shader part epilog536 %neg.b = fneg <2 x half> %b537 %cast.neg.b = bitcast <2 x half> %neg.b to <2 x i16>538 %add = add <2 x i16> %a, %cast.neg.b539 %cast = bitcast <2 x i16> %add to i32540 ret i32 %cast541}542 543define amdgpu_ps i32 @s_add_v2i16_fneg_lhs_fneg_rhs(<2 x half> inreg %a, <2 x half> inreg %b) {544; GFX7-LABEL: s_add_v2i16_fneg_lhs_fneg_rhs:545; GFX7: ; %bb.0:546; GFX7-NEXT: s_lshl_b32 s1, s1, 16547; GFX7-NEXT: s_and_b32 s0, s0, 0xffff548; GFX7-NEXT: s_or_b32 s0, s1, s0549; GFX7-NEXT: s_lshl_b32 s1, s3, 16550; GFX7-NEXT: s_and_b32 s2, s2, 0xffff551; GFX7-NEXT: s_or_b32 s1, s1, s2552; GFX7-NEXT: s_xor_b32 s0, s0, 0x80008000553; GFX7-NEXT: s_xor_b32 s1, s1, 0x80008000554; GFX7-NEXT: s_lshr_b32 s2, s0, 16555; GFX7-NEXT: s_lshr_b32 s3, s1, 16556; GFX7-NEXT: s_add_i32 s2, s2, s3557; GFX7-NEXT: s_add_i32 s0, s0, s1558; GFX7-NEXT: s_and_b32 s1, s2, 0xffff559; GFX7-NEXT: s_and_b32 s0, s0, 0xffff560; GFX7-NEXT: s_lshl_b32 s1, s1, 16561; GFX7-NEXT: s_or_b32 s0, s0, s1562; GFX7-NEXT: ; return to shader part epilog563;564; GFX9-LABEL: s_add_v2i16_fneg_lhs_fneg_rhs:565; GFX9: ; %bb.0:566; GFX9-NEXT: s_xor_b32 s0, s0, 0x80008000567; GFX9-NEXT: s_xor_b32 s1, s1, 0x80008000568; GFX9-NEXT: s_lshr_b32 s2, s0, 16569; GFX9-NEXT: s_lshr_b32 s3, s1, 16570; GFX9-NEXT: s_add_i32 s0, s0, s1571; GFX9-NEXT: s_add_i32 s2, s2, s3572; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2573; GFX9-NEXT: ; return to shader part epilog574;575; GFX8-LABEL: s_add_v2i16_fneg_lhs_fneg_rhs:576; GFX8: ; %bb.0:577; GFX8-NEXT: s_xor_b32 s0, s0, 0x80008000578; GFX8-NEXT: s_xor_b32 s1, s1, 0x80008000579; GFX8-NEXT: s_lshr_b32 s2, s0, 16580; GFX8-NEXT: s_lshr_b32 s3, s1, 16581; GFX8-NEXT: s_add_i32 s2, s2, s3582; GFX8-NEXT: s_add_i32 s0, s0, s1583; GFX8-NEXT: s_and_b32 s1, 0xffff, s2584; GFX8-NEXT: s_and_b32 s0, 0xffff, s0585; GFX8-NEXT: s_lshl_b32 s1, s1, 16586; GFX8-NEXT: s_or_b32 s0, s0, s1587; GFX8-NEXT: ; return to shader part epilog588;589; GFX10-LABEL: s_add_v2i16_fneg_lhs_fneg_rhs:590; GFX10: ; %bb.0:591; GFX10-NEXT: s_xor_b32 s0, s0, 0x80008000592; GFX10-NEXT: s_xor_b32 s1, s1, 0x80008000593; GFX10-NEXT: s_lshr_b32 s2, s0, 16594; GFX10-NEXT: s_lshr_b32 s3, s1, 16595; GFX10-NEXT: s_add_i32 s0, s0, s1596; GFX10-NEXT: s_add_i32 s2, s2, s3597; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2598; GFX10-NEXT: ; return to shader part epilog599 %neg.a = fneg <2 x half> %a600 %neg.b = fneg <2 x half> %b601 %cast.neg.a = bitcast <2 x half> %neg.a to <2 x i16>602 %cast.neg.b = bitcast <2 x half> %neg.b to <2 x i16>603 %add = add <2 x i16> %cast.neg.a, %cast.neg.b604 %cast = bitcast <2 x i16> %add to i32605 ret i32 %cast606}607 608define <2 x i16> @add_inline_imm_neg1_0(<2 x i16> %x) {609; GFX7-LABEL: add_inline_imm_neg1_0:610; GFX7: ; %bb.0:611; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)612; GFX7-NEXT: v_add_i32_e32 v0, vcc, -1, v0613; GFX7-NEXT: s_setpc_b64 s[30:31]614;615; GFX9-LABEL: add_inline_imm_neg1_0:616; GFX9: ; %bb.0:617; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)618; GFX9-NEXT: v_pk_sub_u16 v0, v0, 1619; GFX9-NEXT: s_setpc_b64 s[30:31]620;621; GFX8-LABEL: add_inline_imm_neg1_0:622; GFX8: ; %bb.0:623; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)624; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0625; GFX8-NEXT: v_add_u16_e32 v0, -1, v0626; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1627; GFX8-NEXT: v_or_b32_e32 v0, v0, v1628; GFX8-NEXT: s_setpc_b64 s[30:31]629;630; GFX10-LABEL: add_inline_imm_neg1_0:631; GFX10: ; %bb.0:632; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)633; GFX10-NEXT: v_pk_sub_u16 v0, v0, 1634; GFX10-NEXT: s_setpc_b64 s[30:31]635 %y = add <2 x i16> %x, <i16 -1, i16 0>636 ret <2 x i16> %y637}638 639define <2 x i16> @add_inline_imm_1_0(<2 x i16> %x) {640; GFX7-LABEL: add_inline_imm_1_0:641; GFX7: ; %bb.0:642; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)643; GFX7-NEXT: v_add_i32_e32 v0, vcc, 1, v0644; GFX7-NEXT: s_setpc_b64 s[30:31]645;646; GFX9-LABEL: add_inline_imm_1_0:647; GFX9: ; %bb.0:648; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)649; GFX9-NEXT: v_pk_add_u16 v0, v0, 1650; GFX9-NEXT: s_setpc_b64 s[30:31]651;652; GFX8-LABEL: add_inline_imm_1_0:653; GFX8: ; %bb.0:654; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)655; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0656; GFX8-NEXT: v_add_u16_e32 v0, 1, v0657; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1658; GFX8-NEXT: v_or_b32_e32 v0, v0, v1659; GFX8-NEXT: s_setpc_b64 s[30:31]660;661; GFX10-LABEL: add_inline_imm_1_0:662; GFX10: ; %bb.0:663; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)664; GFX10-NEXT: v_pk_add_u16 v0, v0, 1665; GFX10-NEXT: s_setpc_b64 s[30:31]666 %y = add <2 x i16> %x, <i16 1, i16 0>667 ret <2 x i16> %y668}669