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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=fiji < %s | FileCheck -check-prefix=VI %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s4; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s5; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s6 7; ===================================================================================8; V_ADD_LSHL_U329; ===================================================================================10 11define amdgpu_ps float @add_shl(i32 %a, i32 %b, i32 %c) {12; VI-LABEL: add_shl:13; VI: ; %bb.0:14; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v115; VI-NEXT: v_lshlrev_b32_e32 v0, v2, v016; VI-NEXT: ; return to shader part epilog17;18; GFX9-LABEL: add_shl:19; GFX9: ; %bb.0:20; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, v221; GFX9-NEXT: ; return to shader part epilog22;23; GFX10-LABEL: add_shl:24; GFX10: ; %bb.0:25; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, v226; GFX10-NEXT: ; return to shader part epilog27 %x = add i32 %a, %b28 %result = shl i32 %x, %c29 %bc = bitcast i32 %result to float30 ret float %bc31}32 33define amdgpu_ps float @add_shl_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {34; VI-LABEL: add_shl_vgpr_c:35; VI: ; %bb.0:36; VI-NEXT: s_add_i32 s2, s2, s337; VI-NEXT: v_lshlrev_b32_e64 v0, v0, s238; VI-NEXT: ; return to shader part epilog39;40; GFX9-LABEL: add_shl_vgpr_c:41; GFX9: ; %bb.0:42; GFX9-NEXT: s_add_i32 s2, s2, s343; GFX9-NEXT: v_lshlrev_b32_e64 v0, v0, s244; GFX9-NEXT: ; return to shader part epilog45;46; GFX10-LABEL: add_shl_vgpr_c:47; GFX10: ; %bb.0:48; GFX10-NEXT: s_add_i32 s2, s2, s349; GFX10-NEXT: v_lshlrev_b32_e64 v0, v0, s250; GFX10-NEXT: ; return to shader part epilog51 %x = add i32 %a, %b52 %result = shl i32 %x, %c53 %bc = bitcast i32 %result to float54 ret float %bc55}56 57define amdgpu_ps float @add_shl_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {58; VI-LABEL: add_shl_vgpr_ac:59; VI: ; %bb.0:60; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v061; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v062; VI-NEXT: ; return to shader part epilog63;64; GFX9-LABEL: add_shl_vgpr_ac:65; GFX9: ; %bb.0:66; GFX9-NEXT: v_add_lshl_u32 v0, v0, s2, v167; GFX9-NEXT: ; return to shader part epilog68;69; GFX10-LABEL: add_shl_vgpr_ac:70; GFX10: ; %bb.0:71; GFX10-NEXT: v_add_lshl_u32 v0, v0, s2, v172; GFX10-NEXT: ; return to shader part epilog73 %x = add i32 %a, %b74 %result = shl i32 %x, %c75 %bc = bitcast i32 %result to float76 ret float %bc77}78 79define amdgpu_ps float @add_shl_vgpr_const(i32 %a, i32 %b) {80; VI-LABEL: add_shl_vgpr_const:81; VI: ; %bb.0:82; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v183; VI-NEXT: v_lshlrev_b32_e32 v0, 9, v084; VI-NEXT: ; return to shader part epilog85;86; GFX9-LABEL: add_shl_vgpr_const:87; GFX9: ; %bb.0:88; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, 989; GFX9-NEXT: ; return to shader part epilog90;91; GFX10-LABEL: add_shl_vgpr_const:92; GFX10: ; %bb.0:93; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, 994; GFX10-NEXT: ; return to shader part epilog95 %x = add i32 %a, %b96 %result = shl i32 %x, 997 %bc = bitcast i32 %result to float98 ret float %bc99}100 101define amdgpu_ps float @add_shl_vgpr_const_inline_const(i32 %a) {102; VI-LABEL: add_shl_vgpr_const_inline_const:103; VI: ; %bb.0:104; VI-NEXT: v_lshlrev_b32_e32 v0, 9, v0105; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7e800, v0106; VI-NEXT: ; return to shader part epilog107;108; GFX9-LABEL: add_shl_vgpr_const_inline_const:109; GFX9: ; %bb.0:110; GFX9-NEXT: v_mov_b32_e32 v1, 0x7e800111; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1112; GFX9-NEXT: ; return to shader part epilog113;114; GFX10-LABEL: add_shl_vgpr_const_inline_const:115; GFX10: ; %bb.0:116; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x7e800117; GFX10-NEXT: ; return to shader part epilog118 %x = add i32 %a, 1012119 %result = shl i32 %x, 9120 %bc = bitcast i32 %result to float121 ret float %bc122}123 124define amdgpu_ps float @add_shl_vgpr_inline_const_x2(i32 %a) {125; VI-LABEL: add_shl_vgpr_inline_const_x2:126; VI: ; %bb.0:127; VI-NEXT: v_lshlrev_b32_e32 v0, 9, v0128; VI-NEXT: v_add_u32_e32 v0, vcc, 0x600, v0129; VI-NEXT: ; return to shader part epilog130;131; GFX9-LABEL: add_shl_vgpr_inline_const_x2:132; GFX9: ; %bb.0:133; GFX9-NEXT: v_mov_b32_e32 v1, 0x600134; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1135; GFX9-NEXT: ; return to shader part epilog136;137; GFX10-LABEL: add_shl_vgpr_inline_const_x2:138; GFX10: ; %bb.0:139; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x600140; GFX10-NEXT: ; return to shader part epilog141 %x = add i32 %a, 3142 %result = shl i32 %x, 9143 %bc = bitcast i32 %result to float144 ret float %bc145}146