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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11 %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s4 5define amdgpu_kernel void @s_add_u64(ptr addrspace(1) %out, i64 %a, i64 %b) {6; GFX11-LABEL: s_add_u64:7; GFX11: ; %bb.0: ; %entry8; GFX11-NEXT: s_clause 0x19; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2410; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x3411; GFX11-NEXT: v_mov_b32_e32 v2, 012; GFX11-NEXT: s_waitcnt lgkmcnt(0)13; GFX11-NEXT: s_add_u32 s2, s2, s414; GFX11-NEXT: s_addc_u32 s3, s3, s515; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)16; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s317; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]18; GFX11-NEXT: s_endpgm19;20; GFX12-LABEL: s_add_u64:21; GFX12: ; %bb.0: ; %entry22; GFX12-NEXT: s_clause 0x123; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x2424; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x3425; GFX12-NEXT: v_mov_b32_e32 v2, 026; GFX12-NEXT: s_wait_kmcnt 0x027; GFX12-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[4:5]28; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)29; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s330; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]31; GFX12-NEXT: s_endpgm32entry:33 %add = add i64 %a, %b34 store i64 %add, ptr addrspace(1) %out35 ret void36}37 38define amdgpu_ps void @v_add_u64(ptr addrspace(1) %out, i64 %a, i64 %b) {39; GCN-LABEL: v_add_u64:40; GCN: ; %bb.0: ; %entry41; GCN-NEXT: v_add_co_u32 v2, vcc_lo, v2, v442; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)43; GCN-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v5, vcc_lo44; GCN-NEXT: global_store_b64 v[0:1], v[2:3], off45; GCN-NEXT: s_endpgm46entry:47 %add = add i64 %a, %b48 store i64 %add, ptr addrspace(1) %out49 ret void50}51 52define amdgpu_kernel void @s_sub_u64(ptr addrspace(1) %out, i64 %a, i64 %b) {53; GFX11-LABEL: s_sub_u64:54; GFX11: ; %bb.0: ; %entry55; GFX11-NEXT: s_clause 0x156; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2457; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x3458; GFX11-NEXT: v_mov_b32_e32 v2, 059; GFX11-NEXT: s_waitcnt lgkmcnt(0)60; GFX11-NEXT: s_sub_u32 s2, s2, s461; GFX11-NEXT: s_subb_u32 s3, s3, s562; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)63; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s364; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]65; GFX11-NEXT: s_endpgm66;67; GFX12-LABEL: s_sub_u64:68; GFX12: ; %bb.0: ; %entry69; GFX12-NEXT: s_clause 0x170; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x2471; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x3472; GFX12-NEXT: v_mov_b32_e32 v2, 073; GFX12-NEXT: s_wait_kmcnt 0x074; GFX12-NEXT: s_sub_nc_u64 s[2:3], s[2:3], s[4:5]75; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)76; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s377; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]78; GFX12-NEXT: s_endpgm79entry:80 %sub = sub i64 %a, %b81 store i64 %sub, ptr addrspace(1) %out82 ret void83}84 85define amdgpu_ps void @v_sub_u64(ptr addrspace(1) %out, i64 %a, i64 %b) {86; GCN-LABEL: v_sub_u64:87; GCN: ; %bb.0: ; %entry88; GCN-NEXT: v_sub_co_u32 v2, vcc_lo, v2, v489; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)90; GCN-NEXT: v_sub_co_ci_u32_e64 v3, null, v3, v5, vcc_lo91; GCN-NEXT: global_store_b64 v[0:1], v[2:3], off92; GCN-NEXT: s_endpgm93entry:94 %sub = sub i64 %a, %b95 store i64 %sub, ptr addrspace(1) %out96 ret void97}98