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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GFX7 %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GCN,GFX8 %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s6; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16, -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s7; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16, -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s8; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s9 10define amdgpu_ps i16 @s_and_i16(i16 inreg %num, i16 inreg %den) {11; GCN-LABEL: s_and_i16:12; GCN: ; %bb.0:13; GCN-NEXT: s_and_b32 s0, s0, s114; GCN-NEXT: ; return to shader part epilog15;16; GFX10PLUS-LABEL: s_and_i16:17; GFX10PLUS: ; %bb.0:18; GFX10PLUS-NEXT: s_and_b32 s0, s0, s119; GFX10PLUS-NEXT: ; return to shader part epilog20;21; GFX12-LABEL: s_and_i16:22; GFX12: ; %bb.0:23; GFX12-NEXT: s_and_b32 s0, s0, s124; GFX12-NEXT: ; return to shader part epilog25 %result = and i16 %num, %den26 ret i16 %result27}28 29define i16 @v_and_i16(i16 %num, i16 %den) {30; GCN-LABEL: v_and_i16:31; GCN: ; %bb.0:32; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; GCN-NEXT: v_and_b32_e32 v0, v0, v134; GCN-NEXT: s_setpc_b64 s[30:31]35;36; GFX10PLUS-LABEL: v_and_i16:37; GFX10PLUS: ; %bb.0:38; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)39; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v140; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]41;42; GFX12-LABEL: v_and_i16:43; GFX12: ; %bb.0:44; GFX12-NEXT: s_wait_loadcnt_dscnt 0x045; GFX12-NEXT: s_wait_expcnt 0x046; GFX12-NEXT: s_wait_samplecnt 0x047; GFX12-NEXT: s_wait_bvhcnt 0x048; GFX12-NEXT: s_wait_kmcnt 0x049; GFX12-NEXT: v_and_b32_e32 v0, v0, v150; GFX12-NEXT: s_setpc_b64 s[30:31]51 %result = and i16 %num, %den52 ret i16 %result53}54 55define amdgpu_ps zeroext i16 @s_and_i16_zeroext(i16 inreg zeroext %num, i16 inreg zeroext %den) {56; GFX7-LABEL: s_and_i16_zeroext:57; GFX7: ; %bb.0:58; GFX7-NEXT: s_and_b32 s0, s0, s159; GFX7-NEXT: ; return to shader part epilog60;61; GFX8-LABEL: s_and_i16_zeroext:62; GFX8: ; %bb.0:63; GFX8-NEXT: s_and_b32 s0, s0, s164; GFX8-NEXT: s_and_b32 s0, s0, 0xffff65; GFX8-NEXT: ; return to shader part epilog66;67; GFX9-LABEL: s_and_i16_zeroext:68; GFX9: ; %bb.0:69; GFX9-NEXT: s_and_b32 s0, s0, s170; GFX9-NEXT: s_and_b32 s0, s0, 0xffff71; GFX9-NEXT: ; return to shader part epilog72;73; GFX10PLUS-LABEL: s_and_i16_zeroext:74; GFX10PLUS: ; %bb.0:75; GFX10PLUS-NEXT: s_and_b32 s0, s0, s176; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff77; GFX10PLUS-NEXT: ; return to shader part epilog78;79; GFX12-LABEL: s_and_i16_zeroext:80; GFX12: ; %bb.0:81; GFX12-NEXT: s_and_b32 s0, s0, s182; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)83; GFX12-NEXT: s_and_b32 s0, s0, 0xffff84; GFX12-NEXT: ; return to shader part epilog85 %result = and i16 %num, %den86 ret i16 %result87}88 89define zeroext i16 @v_and_i16_zeroext(i16 zeroext %num, i16 zeroext %den) {90; GCN-LABEL: v_and_i16_zeroext:91; GCN: ; %bb.0:92; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)93; GCN-NEXT: v_and_b32_e32 v0, v0, v194; GCN-NEXT: s_setpc_b64 s[30:31]95;96; GFX10PLUS-LABEL: v_and_i16_zeroext:97; GFX10PLUS: ; %bb.0:98; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)99; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v1100; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]101;102; GFX12-LABEL: v_and_i16_zeroext:103; GFX12: ; %bb.0:104; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0105; GFX12-NEXT: s_wait_expcnt 0x0106; GFX12-NEXT: s_wait_samplecnt 0x0107; GFX12-NEXT: s_wait_bvhcnt 0x0108; GFX12-NEXT: s_wait_kmcnt 0x0109; GFX12-NEXT: v_and_b32_e32 v0, v0, v1110; GFX12-NEXT: s_setpc_b64 s[30:31]111 %result = and i16 %num, %den112 ret i16 %result113}114 115define amdgpu_ps signext i16 @s_and_i16_signext(i16 inreg signext %num, i16 inreg signext %den) {116; GFX7-LABEL: s_and_i16_signext:117; GFX7: ; %bb.0:118; GFX7-NEXT: s_and_b32 s0, s0, s1119; GFX7-NEXT: ; return to shader part epilog120;121; GFX8-LABEL: s_and_i16_signext:122; GFX8: ; %bb.0:123; GFX8-NEXT: s_and_b32 s0, s0, s1124; GFX8-NEXT: s_sext_i32_i16 s0, s0125; GFX8-NEXT: ; return to shader part epilog126;127; GFX9-LABEL: s_and_i16_signext:128; GFX9: ; %bb.0:129; GFX9-NEXT: s_and_b32 s0, s0, s1130; GFX9-NEXT: s_sext_i32_i16 s0, s0131; GFX9-NEXT: ; return to shader part epilog132;133; GFX10PLUS-LABEL: s_and_i16_signext:134; GFX10PLUS: ; %bb.0:135; GFX10PLUS-NEXT: s_and_b32 s0, s0, s1136; GFX10PLUS-NEXT: s_sext_i32_i16 s0, s0137; GFX10PLUS-NEXT: ; return to shader part epilog138;139; GFX12-LABEL: s_and_i16_signext:140; GFX12: ; %bb.0:141; GFX12-NEXT: s_and_b32 s0, s0, s1142; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)143; GFX12-NEXT: s_sext_i32_i16 s0, s0144; GFX12-NEXT: ; return to shader part epilog145 %result = and i16 %num, %den146 ret i16 %result147}148 149define signext i16 @v_and_i16_signext(i16 signext %num, i16 signext %den) {150; GCN-LABEL: v_and_i16_signext:151; GCN: ; %bb.0:152; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)153; GCN-NEXT: v_and_b32_e32 v0, v0, v1154; GCN-NEXT: s_setpc_b64 s[30:31]155;156; GFX10PLUS-LABEL: v_and_i16_signext:157; GFX10PLUS: ; %bb.0:158; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)159; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v1160; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]161;162; GFX12-LABEL: v_and_i16_signext:163; GFX12: ; %bb.0:164; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0165; GFX12-NEXT: s_wait_expcnt 0x0166; GFX12-NEXT: s_wait_samplecnt 0x0167; GFX12-NEXT: s_wait_bvhcnt 0x0168; GFX12-NEXT: s_wait_kmcnt 0x0169; GFX12-NEXT: v_and_b32_e32 v0, v0, v1170; GFX12-NEXT: s_setpc_b64 s[30:31]171 %result = and i16 %num, %den172 ret i16 %result173}174 175define amdgpu_ps i32 @s_and_i32(i32 inreg %num, i32 inreg %den) {176; GCN-LABEL: s_and_i32:177; GCN: ; %bb.0:178; GCN-NEXT: s_and_b32 s0, s0, s1179; GCN-NEXT: ; return to shader part epilog180;181; GFX10PLUS-LABEL: s_and_i32:182; GFX10PLUS: ; %bb.0:183; GFX10PLUS-NEXT: s_and_b32 s0, s0, s1184; GFX10PLUS-NEXT: ; return to shader part epilog185;186; GFX12-LABEL: s_and_i32:187; GFX12: ; %bb.0:188; GFX12-NEXT: s_and_b32 s0, s0, s1189; GFX12-NEXT: ; return to shader part epilog190 %result = and i32 %num, %den191 ret i32 %result192}193 194define i32 @v_and_i32(i32 %num, i32 %den) {195; GCN-LABEL: v_and_i32:196; GCN: ; %bb.0:197; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)198; GCN-NEXT: v_and_b32_e32 v0, v0, v1199; GCN-NEXT: s_setpc_b64 s[30:31]200;201; GFX10PLUS-LABEL: v_and_i32:202; GFX10PLUS: ; %bb.0:203; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)204; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v1205; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]206;207; GFX12-LABEL: v_and_i32:208; GFX12: ; %bb.0:209; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0210; GFX12-NEXT: s_wait_expcnt 0x0211; GFX12-NEXT: s_wait_samplecnt 0x0212; GFX12-NEXT: s_wait_bvhcnt 0x0213; GFX12-NEXT: s_wait_kmcnt 0x0214; GFX12-NEXT: v_and_b32_e32 v0, v0, v1215; GFX12-NEXT: s_setpc_b64 s[30:31]216 %result = and i32 %num, %den217 ret i32 %result218}219 220define amdgpu_ps <2 x i32> @s_and_v2i32(<2 x i32> inreg %num, <2 x i32> inreg %den) {221; GCN-LABEL: s_and_v2i32:222; GCN: ; %bb.0:223; GCN-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]224; GCN-NEXT: ; return to shader part epilog225;226; GFX10PLUS-LABEL: s_and_v2i32:227; GFX10PLUS: ; %bb.0:228; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]229; GFX10PLUS-NEXT: ; return to shader part epilog230;231; GFX12-LABEL: s_and_v2i32:232; GFX12: ; %bb.0:233; GFX12-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]234; GFX12-NEXT: ; return to shader part epilog235 %result = and <2 x i32> %num, %den236 ret <2 x i32> %result237}238 239define <2 x i32> @v_and_v2i32(<2 x i32> %num, <2 x i32> %den) {240; GCN-LABEL: v_and_v2i32:241; GCN: ; %bb.0:242; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)243; GCN-NEXT: v_and_b32_e32 v0, v0, v2244; GCN-NEXT: v_and_b32_e32 v1, v1, v3245; GCN-NEXT: s_setpc_b64 s[30:31]246;247; GFX10PLUS-LABEL: v_and_v2i32:248; GFX10PLUS: ; %bb.0:249; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)250; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v2251; GFX10PLUS-NEXT: v_and_b32_e32 v1, v1, v3252; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]253;254; GFX12-LABEL: v_and_v2i32:255; GFX12: ; %bb.0:256; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0257; GFX12-NEXT: s_wait_expcnt 0x0258; GFX12-NEXT: s_wait_samplecnt 0x0259; GFX12-NEXT: s_wait_bvhcnt 0x0260; GFX12-NEXT: s_wait_kmcnt 0x0261; GFX12-NEXT: v_and_b32_e32 v0, v0, v2262; GFX12-NEXT: v_and_b32_e32 v1, v1, v3263; GFX12-NEXT: s_setpc_b64 s[30:31]264 %result = and <2 x i32> %num, %den265 ret <2 x i32> %result266}267 268define amdgpu_cs i33 @s_and_i33(i33 inreg %num, i33 inreg %den) {269; GCN-LABEL: s_and_i33:270; GCN: ; %bb.0:271; GCN-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]272; GCN-NEXT: ; return to shader part epilog273;274; GFX10PLUS-LABEL: s_and_i33:275; GFX10PLUS: ; %bb.0:276; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]277; GFX10PLUS-NEXT: ; return to shader part epilog278;279; GFX12-LABEL: s_and_i33:280; GFX12: ; %bb.0:281; GFX12-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]282; GFX12-NEXT: ; return to shader part epilog283 %result = and i33 %num, %den284 ret i33 %result285}286 287define amdgpu_ps i64 @s_and_i64(i64 inreg %num, i64 inreg %den) {288; GCN-LABEL: s_and_i64:289; GCN: ; %bb.0:290; GCN-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]291; GCN-NEXT: ; return to shader part epilog292;293; GFX10PLUS-LABEL: s_and_i64:294; GFX10PLUS: ; %bb.0:295; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]296; GFX10PLUS-NEXT: ; return to shader part epilog297;298; GFX12-LABEL: s_and_i64:299; GFX12: ; %bb.0:300; GFX12-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]301; GFX12-NEXT: ; return to shader part epilog302 %result = and i64 %num, %den303 ret i64 %result304}305 306define i64 @v_and_i64(i64 %num, i64 %den) {307; GCN-LABEL: v_and_i64:308; GCN: ; %bb.0:309; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)310; GCN-NEXT: v_and_b32_e32 v0, v0, v2311; GCN-NEXT: v_and_b32_e32 v1, v1, v3312; GCN-NEXT: s_setpc_b64 s[30:31]313;314; GFX10PLUS-LABEL: v_and_i64:315; GFX10PLUS: ; %bb.0:316; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)317; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v2318; GFX10PLUS-NEXT: v_and_b32_e32 v1, v1, v3319; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]320;321; GFX12-LABEL: v_and_i64:322; GFX12: ; %bb.0:323; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0324; GFX12-NEXT: s_wait_expcnt 0x0325; GFX12-NEXT: s_wait_samplecnt 0x0326; GFX12-NEXT: s_wait_bvhcnt 0x0327; GFX12-NEXT: s_wait_kmcnt 0x0328; GFX12-NEXT: v_and_b32_e32 v0, v0, v2329; GFX12-NEXT: v_and_b32_e32 v1, v1, v3330; GFX12-NEXT: s_setpc_b64 s[30:31]331 %result = and i64 %num, %den332 ret i64 %result333}334 335define amdgpu_ps <3 x i32> @s_and_i96(i96 inreg %num, i96 inreg %den) {336; GCN-LABEL: s_and_i96:337; GCN: ; %bb.0:338; GCN-NEXT: s_mov_b32 s6, s3339; GCN-NEXT: s_mov_b32 s7, s4340; GCN-NEXT: s_and_b64 s[0:1], s[0:1], s[6:7]341; GCN-NEXT: s_and_b32 s2, s2, s5342; GCN-NEXT: ; return to shader part epilog343;344; GFX10PLUS-LABEL: s_and_i96:345; GFX10PLUS: ; %bb.0:346; GFX10PLUS-NEXT: s_mov_b32 s6, s3347; GFX10PLUS-NEXT: s_mov_b32 s7, s4348; GFX10PLUS-NEXT: s_and_b32 s2, s2, s5349; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[0:1], s[6:7]350; GFX10PLUS-NEXT: ; return to shader part epilog351;352; GFX12-LABEL: s_and_i96:353; GFX12: ; %bb.0:354; GFX12-NEXT: s_mov_b32 s6, s3355; GFX12-NEXT: s_mov_b32 s7, s4356; GFX12-NEXT: s_and_b32 s2, s2, s5357; GFX12-NEXT: s_and_b64 s[0:1], s[0:1], s[6:7]358; GFX12-NEXT: ; return to shader part epilog359 %result = and i96 %num, %den360 %cast = bitcast i96 %result to <3 x i32>361 ret <3 x i32> %cast362}363 364define i96 @v_and_i96(i96 %num, i96 %den) {365; GCN-LABEL: v_and_i96:366; GCN: ; %bb.0:367; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)368; GCN-NEXT: v_and_b32_e32 v0, v0, v3369; GCN-NEXT: v_and_b32_e32 v1, v1, v4370; GCN-NEXT: v_and_b32_e32 v2, v2, v5371; GCN-NEXT: s_setpc_b64 s[30:31]372;373; GFX10PLUS-LABEL: v_and_i96:374; GFX10PLUS: ; %bb.0:375; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)376; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v3377; GFX10PLUS-NEXT: v_and_b32_e32 v1, v1, v4378; GFX10PLUS-NEXT: v_and_b32_e32 v2, v2, v5379; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]380;381; GFX12-LABEL: v_and_i96:382; GFX12: ; %bb.0:383; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0384; GFX12-NEXT: s_wait_expcnt 0x0385; GFX12-NEXT: s_wait_samplecnt 0x0386; GFX12-NEXT: s_wait_bvhcnt 0x0387; GFX12-NEXT: s_wait_kmcnt 0x0388; GFX12-NEXT: v_and_b32_e32 v0, v0, v3389; GFX12-NEXT: v_and_b32_e32 v1, v1, v4390; GFX12-NEXT: v_and_b32_e32 v2, v2, v5391; GFX12-NEXT: s_setpc_b64 s[30:31]392 %result = and i96 %num, %den393 ret i96 %result394}395 396define amdgpu_ps <4 x i32> @s_and_i128(i128 inreg %num, i128 inreg %den) {397; GCN-LABEL: s_and_i128:398; GCN: ; %bb.0:399; GCN-NEXT: s_and_b64 s[0:1], s[0:1], s[4:5]400; GCN-NEXT: s_and_b64 s[2:3], s[2:3], s[6:7]401; GCN-NEXT: ; return to shader part epilog402;403; GFX10PLUS-LABEL: s_and_i128:404; GFX10PLUS: ; %bb.0:405; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[0:1], s[4:5]406; GFX10PLUS-NEXT: s_and_b64 s[2:3], s[2:3], s[6:7]407; GFX10PLUS-NEXT: ; return to shader part epilog408;409; GFX12-LABEL: s_and_i128:410; GFX12: ; %bb.0:411; GFX12-NEXT: s_and_b64 s[0:1], s[0:1], s[4:5]412; GFX12-NEXT: s_and_b64 s[2:3], s[2:3], s[6:7]413; GFX12-NEXT: ; return to shader part epilog414 %result = and i128 %num, %den415 %cast = bitcast i128 %result to <4 x i32>416 ret <4 x i32> %cast417}418 419define i128 @v_and_i128(i128 %num, i128 %den) {420; GCN-LABEL: v_and_i128:421; GCN: ; %bb.0:422; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)423; GCN-NEXT: v_and_b32_e32 v0, v0, v4424; GCN-NEXT: v_and_b32_e32 v1, v1, v5425; GCN-NEXT: v_and_b32_e32 v2, v2, v6426; GCN-NEXT: v_and_b32_e32 v3, v3, v7427; GCN-NEXT: s_setpc_b64 s[30:31]428;429; GFX10PLUS-LABEL: v_and_i128:430; GFX10PLUS: ; %bb.0:431; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)432; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v4433; GFX10PLUS-NEXT: v_and_b32_e32 v1, v1, v5434; GFX10PLUS-NEXT: v_and_b32_e32 v2, v2, v6435; GFX10PLUS-NEXT: v_and_b32_e32 v3, v3, v7436; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]437;438; GFX12-LABEL: v_and_i128:439; GFX12: ; %bb.0:440; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0441; GFX12-NEXT: s_wait_expcnt 0x0442; GFX12-NEXT: s_wait_samplecnt 0x0443; GFX12-NEXT: s_wait_bvhcnt 0x0444; GFX12-NEXT: s_wait_kmcnt 0x0445; GFX12-NEXT: v_and_b32_e32 v0, v0, v4446; GFX12-NEXT: v_and_b32_e32 v1, v1, v5447; GFX12-NEXT: v_and_b32_e32 v2, v2, v6448; GFX12-NEXT: v_and_b32_e32 v3, v3, v7449; GFX12-NEXT: s_setpc_b64 s[30:31]450 %result = and i128 %num, %den451 ret i128 %result452}453 454define amdgpu_ps <8 x i32> @s_and_i256(i256 inreg %num, i256 inreg %den) {455; GCN-LABEL: s_and_i256:456; GCN: ; %bb.0:457; GCN-NEXT: s_and_b64 s[0:1], s[0:1], s[8:9]458; GCN-NEXT: s_and_b64 s[2:3], s[2:3], s[10:11]459; GCN-NEXT: s_and_b64 s[4:5], s[4:5], s[12:13]460; GCN-NEXT: s_and_b64 s[6:7], s[6:7], s[14:15]461; GCN-NEXT: ; return to shader part epilog462;463; GFX10PLUS-LABEL: s_and_i256:464; GFX10PLUS: ; %bb.0:465; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[0:1], s[8:9]466; GFX10PLUS-NEXT: s_and_b64 s[2:3], s[2:3], s[10:11]467; GFX10PLUS-NEXT: s_and_b64 s[4:5], s[4:5], s[12:13]468; GFX10PLUS-NEXT: s_and_b64 s[6:7], s[6:7], s[14:15]469; GFX10PLUS-NEXT: ; return to shader part epilog470;471; GFX12-LABEL: s_and_i256:472; GFX12: ; %bb.0:473; GFX12-NEXT: s_and_b64 s[0:1], s[0:1], s[8:9]474; GFX12-NEXT: s_and_b64 s[2:3], s[2:3], s[10:11]475; GFX12-NEXT: s_and_b64 s[4:5], s[4:5], s[12:13]476; GFX12-NEXT: s_and_b64 s[6:7], s[6:7], s[14:15]477; GFX12-NEXT: ; return to shader part epilog478 %result = and i256 %num, %den479 %cast = bitcast i256 %result to <8 x i32>480 ret <8 x i32> %cast481}482 483define i256 @v_and_i256(i256 %num, i256 %den) {484; GCN-LABEL: v_and_i256:485; GCN: ; %bb.0:486; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)487; GCN-NEXT: v_and_b32_e32 v0, v0, v8488; GCN-NEXT: v_and_b32_e32 v1, v1, v9489; GCN-NEXT: v_and_b32_e32 v2, v2, v10490; GCN-NEXT: v_and_b32_e32 v3, v3, v11491; GCN-NEXT: v_and_b32_e32 v4, v4, v12492; GCN-NEXT: v_and_b32_e32 v5, v5, v13493; GCN-NEXT: v_and_b32_e32 v6, v6, v14494; GCN-NEXT: v_and_b32_e32 v7, v7, v15495; GCN-NEXT: s_setpc_b64 s[30:31]496;497; GFX10PLUS-LABEL: v_and_i256:498; GFX10PLUS: ; %bb.0:499; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)500; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v8501; GFX10PLUS-NEXT: v_and_b32_e32 v1, v1, v9502; GFX10PLUS-NEXT: v_and_b32_e32 v2, v2, v10503; GFX10PLUS-NEXT: v_and_b32_e32 v3, v3, v11504; GFX10PLUS-NEXT: v_and_b32_e32 v4, v4, v12505; GFX10PLUS-NEXT: v_and_b32_e32 v5, v5, v13506; GFX10PLUS-NEXT: v_and_b32_e32 v6, v6, v14507; GFX10PLUS-NEXT: v_and_b32_e32 v7, v7, v15508; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]509;510; GFX12-LABEL: v_and_i256:511; GFX12: ; %bb.0:512; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0513; GFX12-NEXT: s_wait_expcnt 0x0514; GFX12-NEXT: s_wait_samplecnt 0x0515; GFX12-NEXT: s_wait_bvhcnt 0x0516; GFX12-NEXT: s_wait_kmcnt 0x0517; GFX12-NEXT: v_and_b32_e32 v0, v0, v8518; GFX12-NEXT: v_and_b32_e32 v1, v1, v9519; GFX12-NEXT: v_and_b32_e32 v2, v2, v10520; GFX12-NEXT: v_and_b32_e32 v3, v3, v11521; GFX12-NEXT: v_and_b32_e32 v4, v4, v12522; GFX12-NEXT: v_and_b32_e32 v5, v5, v13523; GFX12-NEXT: v_and_b32_e32 v6, v6, v14524; GFX12-NEXT: v_and_b32_e32 v7, v7, v15525; GFX12-NEXT: s_setpc_b64 s[30:31]526 %result = and i256 %num, %den527 ret i256 %result528}529 530define amdgpu_ps void @s_and_u64_zext_with_vregs(ptr addrspace(1) %out, ptr addrspace(1) %in) {531; GFX7-LABEL: s_and_u64_zext_with_vregs:532; GFX7: ; %bb.0:533; GFX7-NEXT: s_mov_b32 s2, 0534; GFX7-NEXT: s_mov_b32 s3, 0xf000535; GFX7-NEXT: s_mov_b64 s[0:1], 0536; GFX7-NEXT: buffer_load_dword v2, v[2:3], s[0:3], 0 addr64537; GFX7-NEXT: v_mov_b32_e32 v3, 0538; GFX7-NEXT: s_waitcnt vmcnt(0)539; GFX7-NEXT: v_and_b32_e32 v2, 0x50, v2540; GFX7-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64541; GFX7-NEXT: s_endpgm542;543; GFX8-LABEL: s_and_u64_zext_with_vregs:544; GFX8: ; %bb.0:545; GFX8-NEXT: flat_load_dword v2, v[2:3]546; GFX8-NEXT: v_mov_b32_e32 v3, 0547; GFX8-NEXT: s_waitcnt vmcnt(0)548; GFX8-NEXT: v_and_b32_e32 v2, 0x50, v2549; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]550; GFX8-NEXT: s_endpgm551;552; GFX9-LABEL: s_and_u64_zext_with_vregs:553; GFX9: ; %bb.0:554; GFX9-NEXT: global_load_dword v2, v[2:3], off555; GFX9-NEXT: v_mov_b32_e32 v3, 0556; GFX9-NEXT: s_waitcnt vmcnt(0)557; GFX9-NEXT: v_and_b32_e32 v2, 0x50, v2558; GFX9-NEXT: global_store_dwordx2 v[0:1], v[2:3], off559; GFX9-NEXT: s_endpgm560;561; GFX10-LABEL: s_and_u64_zext_with_vregs:562; GFX10: ; %bb.0:563; GFX10-NEXT: global_load_dword v2, v[2:3], off564; GFX10-NEXT: v_mov_b32_e32 v3, 0565; GFX10-NEXT: s_waitcnt vmcnt(0)566; GFX10-NEXT: v_and_b32_e32 v2, 0x50, v2567; GFX10-NEXT: global_store_dwordx2 v[0:1], v[2:3], off568; GFX10-NEXT: s_endpgm569;570; GFX11-LABEL: s_and_u64_zext_with_vregs:571; GFX11: ; %bb.0:572; GFX11-NEXT: global_load_b32 v2, v[2:3], off573; GFX11-NEXT: s_waitcnt vmcnt(0)574; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 0x50, v2575; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off576; GFX11-NEXT: s_endpgm577;578; GFX12-LABEL: s_and_u64_zext_with_vregs:579; GFX12: ; %bb.0:580; GFX12-NEXT: global_load_b32 v2, v[2:3], off581; GFX12-NEXT: s_wait_loadcnt 0x0582; GFX12-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 0x50, v2583; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off584; GFX12-NEXT: s_endpgm585 %val = load i32, ptr addrspace(1) %in, align 4586 %ext = zext i32 %val to i64587 %and = and i64 %ext, 80588 store i64 %and, ptr addrspace(1) %out, align 8589 ret void590}591 592define amdgpu_kernel void @s_and_u64_zext_with_sregs(ptr addrspace(1) %out, ptr addrspace(1) %in) {593; GFX7-LABEL: s_and_u64_zext_with_sregs:594; GFX7: ; %bb.0:595; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9596; GFX7-NEXT: s_mov_b32 s5, 0597; GFX7-NEXT: s_waitcnt lgkmcnt(0)598; GFX7-NEXT: s_load_dword s4, s[2:3], 0x0599; GFX7-NEXT: s_mov_b32 s2, -1600; GFX7-NEXT: s_mov_b32 s3, 0xf000601; GFX7-NEXT: s_waitcnt lgkmcnt(0)602; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], 0x50603; GFX7-NEXT: v_mov_b32_e32 v0, s4604; GFX7-NEXT: v_mov_b32_e32 v1, s5605; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0606; GFX7-NEXT: s_endpgm607;608; GFX8-LABEL: s_and_u64_zext_with_sregs:609; GFX8: ; %bb.0:610; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24611; GFX8-NEXT: s_waitcnt lgkmcnt(0)612; GFX8-NEXT: v_mov_b32_e32 v3, s1613; GFX8-NEXT: s_load_dword s2, s[2:3], 0x0614; GFX8-NEXT: s_mov_b32 s3, 0615; GFX8-NEXT: v_mov_b32_e32 v2, s0616; GFX8-NEXT: s_waitcnt lgkmcnt(0)617; GFX8-NEXT: s_and_b64 s[2:3], s[2:3], 0x50618; GFX8-NEXT: v_mov_b32_e32 v0, s2619; GFX8-NEXT: v_mov_b32_e32 v1, s3620; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]621; GFX8-NEXT: s_endpgm622;623; GFX9-LABEL: s_and_u64_zext_with_sregs:624; GFX9: ; %bb.0:625; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24626; GFX9-NEXT: v_mov_b32_e32 v2, 0627; GFX9-NEXT: s_waitcnt lgkmcnt(0)628; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0629; GFX9-NEXT: s_mov_b32 s3, 0630; GFX9-NEXT: s_waitcnt lgkmcnt(0)631; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], 0x50632; GFX9-NEXT: v_mov_b32_e32 v0, s2633; GFX9-NEXT: v_mov_b32_e32 v1, s3634; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]635; GFX9-NEXT: s_endpgm636;637; GFX10-LABEL: s_and_u64_zext_with_sregs:638; GFX10: ; %bb.0:639; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24640; GFX10-NEXT: v_mov_b32_e32 v2, 0641; GFX10-NEXT: s_waitcnt lgkmcnt(0)642; GFX10-NEXT: s_load_dword s2, s[2:3], 0x0643; GFX10-NEXT: s_mov_b32 s3, 0644; GFX10-NEXT: s_waitcnt lgkmcnt(0)645; GFX10-NEXT: s_and_b64 s[2:3], s[2:3], 0x50646; GFX10-NEXT: v_mov_b32_e32 v0, s2647; GFX10-NEXT: v_mov_b32_e32 v1, s3648; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]649; GFX10-NEXT: s_endpgm650;651; GFX11-LABEL: s_and_u64_zext_with_sregs:652; GFX11: ; %bb.0:653; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24654; GFX11-NEXT: v_mov_b32_e32 v2, 0655; GFX11-NEXT: s_waitcnt lgkmcnt(0)656; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0657; GFX11-NEXT: s_mov_b32 s3, 0658; GFX11-NEXT: s_waitcnt lgkmcnt(0)659; GFX11-NEXT: s_and_b64 s[2:3], s[2:3], 0x50660; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3661; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]662; GFX11-NEXT: s_endpgm663;664; GFX12-LABEL: s_and_u64_zext_with_sregs:665; GFX12: ; %bb.0:666; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24667; GFX12-NEXT: v_mov_b32_e32 v2, 0668; GFX12-NEXT: s_wait_kmcnt 0x0669; GFX12-NEXT: s_load_b32 s2, s[2:3], 0x0670; GFX12-NEXT: s_mov_b32 s3, 0671; GFX12-NEXT: s_wait_kmcnt 0x0672; GFX12-NEXT: s_and_b64 s[2:3], s[2:3], 0x50673; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)674; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3675; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]676; GFX12-NEXT: s_endpgm677 %val = load i32, ptr addrspace(1) %in, align 4678 %ext = zext i32 %val to i64679 %and = and i64 %ext, 80680 store i64 %and, ptr addrspace(1) %out, align 8681 ret void682}683 684define amdgpu_ps void @s_and_u64_sext_with_vregs(ptr addrspace(1) %out, ptr addrspace(1) %in) {685; GFX7-LABEL: s_and_u64_sext_with_vregs:686; GFX7: ; %bb.0:687; GFX7-NEXT: s_mov_b32 s2, 0688; GFX7-NEXT: s_mov_b32 s3, 0xf000689; GFX7-NEXT: s_mov_b64 s[0:1], 0690; GFX7-NEXT: buffer_load_dword v2, v[2:3], s[0:3], 0 addr64691; GFX7-NEXT: v_mov_b32_e32 v3, 0692; GFX7-NEXT: s_waitcnt vmcnt(0)693; GFX7-NEXT: v_and_b32_e32 v2, 0x50, v2694; GFX7-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64695; GFX7-NEXT: s_endpgm696;697; GFX8-LABEL: s_and_u64_sext_with_vregs:698; GFX8: ; %bb.0:699; GFX8-NEXT: flat_load_dword v2, v[2:3]700; GFX8-NEXT: v_mov_b32_e32 v3, 0701; GFX8-NEXT: s_waitcnt vmcnt(0)702; GFX8-NEXT: v_and_b32_e32 v2, 0x50, v2703; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]704; GFX8-NEXT: s_endpgm705;706; GFX9-LABEL: s_and_u64_sext_with_vregs:707; GFX9: ; %bb.0:708; GFX9-NEXT: global_load_dword v2, v[2:3], off709; GFX9-NEXT: v_mov_b32_e32 v3, 0710; GFX9-NEXT: s_waitcnt vmcnt(0)711; GFX9-NEXT: v_and_b32_e32 v2, 0x50, v2712; GFX9-NEXT: global_store_dwordx2 v[0:1], v[2:3], off713; GFX9-NEXT: s_endpgm714;715; GFX10-LABEL: s_and_u64_sext_with_vregs:716; GFX10: ; %bb.0:717; GFX10-NEXT: global_load_dword v2, v[2:3], off718; GFX10-NEXT: v_mov_b32_e32 v3, 0719; GFX10-NEXT: s_waitcnt vmcnt(0)720; GFX10-NEXT: v_and_b32_e32 v2, 0x50, v2721; GFX10-NEXT: global_store_dwordx2 v[0:1], v[2:3], off722; GFX10-NEXT: s_endpgm723;724; GFX11-LABEL: s_and_u64_sext_with_vregs:725; GFX11: ; %bb.0:726; GFX11-NEXT: global_load_b32 v2, v[2:3], off727; GFX11-NEXT: s_waitcnt vmcnt(0)728; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 0x50, v2729; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off730; GFX11-NEXT: s_endpgm731;732; GFX12-LABEL: s_and_u64_sext_with_vregs:733; GFX12: ; %bb.0:734; GFX12-NEXT: global_load_b32 v2, v[2:3], off735; GFX12-NEXT: s_wait_loadcnt 0x0736; GFX12-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 0x50, v2737; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off738; GFX12-NEXT: s_endpgm739 %val = load i32, ptr addrspace(1) %in, align 4740 %ext = sext i32 %val to i64741 %and = and i64 %ext, 80742 store i64 %and, ptr addrspace(1) %out, align 8743 ret void744}745 746define amdgpu_kernel void @s_and_u64_sext_with_sregs(ptr addrspace(1) %out, ptr addrspace(1) %in) {747; GFX7-LABEL: s_and_u64_sext_with_sregs:748; GFX7: ; %bb.0:749; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9750; GFX7-NEXT: s_waitcnt lgkmcnt(0)751; GFX7-NEXT: s_load_dword s4, s[2:3], 0x0752; GFX7-NEXT: s_mov_b32 s2, -1753; GFX7-NEXT: s_mov_b32 s3, 0xf000754; GFX7-NEXT: s_waitcnt lgkmcnt(0)755; GFX7-NEXT: s_ashr_i32 s5, s4, 31756; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], 0x50757; GFX7-NEXT: v_mov_b32_e32 v0, s4758; GFX7-NEXT: v_mov_b32_e32 v1, s5759; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0760; GFX7-NEXT: s_endpgm761;762; GFX8-LABEL: s_and_u64_sext_with_sregs:763; GFX8: ; %bb.0:764; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24765; GFX8-NEXT: s_waitcnt lgkmcnt(0)766; GFX8-NEXT: v_mov_b32_e32 v3, s1767; GFX8-NEXT: s_load_dword s2, s[2:3], 0x0768; GFX8-NEXT: v_mov_b32_e32 v2, s0769; GFX8-NEXT: s_waitcnt lgkmcnt(0)770; GFX8-NEXT: s_ashr_i32 s3, s2, 31771; GFX8-NEXT: s_and_b64 s[2:3], s[2:3], 0x50772; GFX8-NEXT: v_mov_b32_e32 v0, s2773; GFX8-NEXT: v_mov_b32_e32 v1, s3774; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]775; GFX8-NEXT: s_endpgm776;777; GFX9-LABEL: s_and_u64_sext_with_sregs:778; GFX9: ; %bb.0:779; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24780; GFX9-NEXT: v_mov_b32_e32 v2, 0781; GFX9-NEXT: s_waitcnt lgkmcnt(0)782; GFX9-NEXT: s_load_dword s2, s[2:3], 0x0783; GFX9-NEXT: s_waitcnt lgkmcnt(0)784; GFX9-NEXT: s_ashr_i32 s3, s2, 31785; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], 0x50786; GFX9-NEXT: v_mov_b32_e32 v0, s2787; GFX9-NEXT: v_mov_b32_e32 v1, s3788; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]789; GFX9-NEXT: s_endpgm790;791; GFX10-LABEL: s_and_u64_sext_with_sregs:792; GFX10: ; %bb.0:793; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24794; GFX10-NEXT: v_mov_b32_e32 v2, 0795; GFX10-NEXT: s_waitcnt lgkmcnt(0)796; GFX10-NEXT: s_load_dword s2, s[2:3], 0x0797; GFX10-NEXT: s_waitcnt lgkmcnt(0)798; GFX10-NEXT: s_ashr_i32 s3, s2, 31799; GFX10-NEXT: s_and_b64 s[2:3], s[2:3], 0x50800; GFX10-NEXT: v_mov_b32_e32 v0, s2801; GFX10-NEXT: v_mov_b32_e32 v1, s3802; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]803; GFX10-NEXT: s_endpgm804;805; GFX11-LABEL: s_and_u64_sext_with_sregs:806; GFX11: ; %bb.0:807; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24808; GFX11-NEXT: v_mov_b32_e32 v2, 0809; GFX11-NEXT: s_waitcnt lgkmcnt(0)810; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0811; GFX11-NEXT: s_waitcnt lgkmcnt(0)812; GFX11-NEXT: s_ashr_i32 s3, s2, 31813; GFX11-NEXT: s_and_b64 s[2:3], s[2:3], 0x50814; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3815; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]816; GFX11-NEXT: s_endpgm817;818; GFX12-LABEL: s_and_u64_sext_with_sregs:819; GFX12: ; %bb.0:820; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24821; GFX12-NEXT: v_mov_b32_e32 v2, 0822; GFX12-NEXT: s_wait_kmcnt 0x0823; GFX12-NEXT: s_load_b32 s2, s[2:3], 0x0824; GFX12-NEXT: s_wait_kmcnt 0x0825; GFX12-NEXT: s_ashr_i32 s3, s2, 31826; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)827; GFX12-NEXT: s_and_b64 s[2:3], s[2:3], 0x50828; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3829; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]830; GFX12-NEXT: s_endpgm831 %val = load i32, ptr addrspace(1) %in, align 4832 %ext = sext i32 %val to i64833 %and = and i64 %ext, 80834 store i64 %and, ptr addrspace(1) %out, align 8835 ret void836}837 838define <2 x i128> @v_and_v2i128(<2 x i128> %a, <2 x i128> %b) {839; GCN-LABEL: v_and_v2i128:840; GCN: ; %bb.0:841; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)842; GCN-NEXT: v_and_b32_e32 v0, v0, v8843; GCN-NEXT: v_and_b32_e32 v1, v1, v9844; GCN-NEXT: v_and_b32_e32 v2, v2, v10845; GCN-NEXT: v_and_b32_e32 v3, v3, v11846; GCN-NEXT: v_and_b32_e32 v4, v4, v12847; GCN-NEXT: v_and_b32_e32 v5, v5, v13848; GCN-NEXT: v_and_b32_e32 v6, v6, v14849; GCN-NEXT: v_and_b32_e32 v7, v7, v15850; GCN-NEXT: s_setpc_b64 s[30:31]851;852; GFX10PLUS-LABEL: v_and_v2i128:853; GFX10PLUS: ; %bb.0:854; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)855; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v8856; GFX10PLUS-NEXT: v_and_b32_e32 v1, v1, v9857; GFX10PLUS-NEXT: v_and_b32_e32 v2, v2, v10858; GFX10PLUS-NEXT: v_and_b32_e32 v3, v3, v11859; GFX10PLUS-NEXT: v_and_b32_e32 v4, v4, v12860; GFX10PLUS-NEXT: v_and_b32_e32 v5, v5, v13861; GFX10PLUS-NEXT: v_and_b32_e32 v6, v6, v14862; GFX10PLUS-NEXT: v_and_b32_e32 v7, v7, v15863; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]864;865; GFX12-LABEL: v_and_v2i128:866; GFX12: ; %bb.0:867; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0868; GFX12-NEXT: s_wait_expcnt 0x0869; GFX12-NEXT: s_wait_samplecnt 0x0870; GFX12-NEXT: s_wait_bvhcnt 0x0871; GFX12-NEXT: s_wait_kmcnt 0x0872; GFX12-NEXT: v_and_b32_e32 v0, v0, v8873; GFX12-NEXT: v_and_b32_e32 v1, v1, v9874; GFX12-NEXT: v_and_b32_e32 v2, v2, v10875; GFX12-NEXT: v_and_b32_e32 v3, v3, v11876; GFX12-NEXT: v_and_b32_e32 v4, v4, v12877; GFX12-NEXT: v_and_b32_e32 v5, v5, v13878; GFX12-NEXT: v_and_b32_e32 v6, v6, v14879; GFX12-NEXT: v_and_b32_e32 v7, v7, v15880; GFX12-NEXT: s_setpc_b64 s[30:31]881 %and = and <2 x i128> %a, %b882 ret <2 x i128> %and883}884 885define <2 x i128> @v_and_v2i128_inline_imm(<2 x i128> %a) {886; GCN-LABEL: v_and_v2i128_inline_imm:887; GCN: ; %bb.0:888; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)889; GCN-NEXT: v_and_b32_e32 v0, 64, v0890; GCN-NEXT: v_and_b32_e32 v4, 64, v4891; GCN-NEXT: v_mov_b32_e32 v1, 0892; GCN-NEXT: v_mov_b32_e32 v2, 0893; GCN-NEXT: v_mov_b32_e32 v3, 0894; GCN-NEXT: v_mov_b32_e32 v5, 0895; GCN-NEXT: v_mov_b32_e32 v6, 0896; GCN-NEXT: v_mov_b32_e32 v7, 0897; GCN-NEXT: s_setpc_b64 s[30:31]898;899; GFX10-LABEL: v_and_v2i128_inline_imm:900; GFX10: ; %bb.0:901; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)902; GFX10-NEXT: v_and_b32_e32 v0, 64, v0903; GFX10-NEXT: v_and_b32_e32 v4, 64, v4904; GFX10-NEXT: v_mov_b32_e32 v1, 0905; GFX10-NEXT: v_mov_b32_e32 v2, 0906; GFX10-NEXT: v_mov_b32_e32 v3, 0907; GFX10-NEXT: v_mov_b32_e32 v5, 0908; GFX10-NEXT: v_mov_b32_e32 v6, 0909; GFX10-NEXT: v_mov_b32_e32 v7, 0910; GFX10-NEXT: s_setpc_b64 s[30:31]911;912; GFX11-LABEL: v_and_v2i128_inline_imm:913; GFX11: ; %bb.0:914; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)915; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 64, v0916; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v4, 64, v4917; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0918; GFX11-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0919; GFX11-NEXT: s_setpc_b64 s[30:31]920;921; GFX12-LABEL: v_and_v2i128_inline_imm:922; GFX12: ; %bb.0:923; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0924; GFX12-NEXT: s_wait_expcnt 0x0925; GFX12-NEXT: s_wait_samplecnt 0x0926; GFX12-NEXT: s_wait_bvhcnt 0x0927; GFX12-NEXT: s_wait_kmcnt 0x0928; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 64, v0929; GFX12-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v4, 64, v4930; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0931; GFX12-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0932; GFX12-NEXT: s_setpc_b64 s[30:31]933 %and = and <2 x i128> %a, <i128 64, i128 64>934 ret <2 x i128> %and935}936 937define <3 x i128> @v_and_v3i128(<3 x i128> %a, <3 x i128> %b) {938; GCN-LABEL: v_and_v3i128:939; GCN: ; %bb.0:940; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)941; GCN-NEXT: v_and_b32_e32 v0, v0, v12942; GCN-NEXT: v_and_b32_e32 v1, v1, v13943; GCN-NEXT: v_and_b32_e32 v2, v2, v14944; GCN-NEXT: v_and_b32_e32 v3, v3, v15945; GCN-NEXT: v_and_b32_e32 v4, v4, v16946; GCN-NEXT: v_and_b32_e32 v5, v5, v17947; GCN-NEXT: v_and_b32_e32 v6, v6, v18948; GCN-NEXT: v_and_b32_e32 v7, v7, v19949; GCN-NEXT: v_and_b32_e32 v8, v8, v20950; GCN-NEXT: v_and_b32_e32 v9, v9, v21951; GCN-NEXT: v_and_b32_e32 v10, v10, v22952; GCN-NEXT: v_and_b32_e32 v11, v11, v23953; GCN-NEXT: s_setpc_b64 s[30:31]954;955; GFX10PLUS-LABEL: v_and_v3i128:956; GFX10PLUS: ; %bb.0:957; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)958; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v12959; GFX10PLUS-NEXT: v_and_b32_e32 v1, v1, v13960; GFX10PLUS-NEXT: v_and_b32_e32 v2, v2, v14961; GFX10PLUS-NEXT: v_and_b32_e32 v3, v3, v15962; GFX10PLUS-NEXT: v_and_b32_e32 v4, v4, v16963; GFX10PLUS-NEXT: v_and_b32_e32 v5, v5, v17964; GFX10PLUS-NEXT: v_and_b32_e32 v6, v6, v18965; GFX10PLUS-NEXT: v_and_b32_e32 v7, v7, v19966; GFX10PLUS-NEXT: v_and_b32_e32 v8, v8, v20967; GFX10PLUS-NEXT: v_and_b32_e32 v9, v9, v21968; GFX10PLUS-NEXT: v_and_b32_e32 v10, v10, v22969; GFX10PLUS-NEXT: v_and_b32_e32 v11, v11, v23970; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]971;972; GFX12-LABEL: v_and_v3i128:973; GFX12: ; %bb.0:974; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0975; GFX12-NEXT: s_wait_expcnt 0x0976; GFX12-NEXT: s_wait_samplecnt 0x0977; GFX12-NEXT: s_wait_bvhcnt 0x0978; GFX12-NEXT: s_wait_kmcnt 0x0979; GFX12-NEXT: v_and_b32_e32 v0, v0, v12980; GFX12-NEXT: v_and_b32_e32 v1, v1, v13981; GFX12-NEXT: v_and_b32_e32 v2, v2, v14982; GFX12-NEXT: v_and_b32_e32 v3, v3, v15983; GFX12-NEXT: v_and_b32_e32 v4, v4, v16984; GFX12-NEXT: v_and_b32_e32 v5, v5, v17985; GFX12-NEXT: v_and_b32_e32 v6, v6, v18986; GFX12-NEXT: v_and_b32_e32 v7, v7, v19987; GFX12-NEXT: v_and_b32_e32 v8, v8, v20988; GFX12-NEXT: v_and_b32_e32 v9, v9, v21989; GFX12-NEXT: v_and_b32_e32 v10, v10, v22990; GFX12-NEXT: v_and_b32_e32 v11, v11, v23991; GFX12-NEXT: s_setpc_b64 s[30:31]992 %and = and <3 x i128> %a, %b993 ret <3 x i128> %and994}995 996define <1 x i128> @v_and_v1i128(<1 x i128> %a, <1 x i128> %b) {997; GCN-LABEL: v_and_v1i128:998; GCN: ; %bb.0:999; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1000; GCN-NEXT: v_and_b32_e32 v0, v0, v41001; GCN-NEXT: v_and_b32_e32 v1, v1, v51002; GCN-NEXT: v_and_b32_e32 v2, v2, v61003; GCN-NEXT: v_and_b32_e32 v3, v3, v71004; GCN-NEXT: s_setpc_b64 s[30:31]1005;1006; GFX10PLUS-LABEL: v_and_v1i128:1007; GFX10PLUS: ; %bb.0:1008; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1009; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v41010; GFX10PLUS-NEXT: v_and_b32_e32 v1, v1, v51011; GFX10PLUS-NEXT: v_and_b32_e32 v2, v2, v61012; GFX10PLUS-NEXT: v_and_b32_e32 v3, v3, v71013; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1014;1015; GFX12-LABEL: v_and_v1i128:1016; GFX12: ; %bb.0:1017; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01018; GFX12-NEXT: s_wait_expcnt 0x01019; GFX12-NEXT: s_wait_samplecnt 0x01020; GFX12-NEXT: s_wait_bvhcnt 0x01021; GFX12-NEXT: s_wait_kmcnt 0x01022; GFX12-NEXT: v_and_b32_e32 v0, v0, v41023; GFX12-NEXT: v_and_b32_e32 v1, v1, v51024; GFX12-NEXT: v_and_b32_e32 v2, v2, v61025; GFX12-NEXT: v_and_b32_e32 v3, v3, v71026; GFX12-NEXT: s_setpc_b64 s[30:31]1027 %and = and <1 x i128> %a, %b1028 ret <1 x i128> %and1029}1030 1031define <2 x i256> @v_and_v2i256(<2 x i256> %a, <2 x i256> %b) {1032; GCN-LABEL: v_and_v2i256:1033; GCN: ; %bb.0:1034; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1035; GCN-NEXT: v_and_b32_e32 v0, v0, v161036; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s321037; GCN-NEXT: v_and_b32_e32 v1, v1, v171038; GCN-NEXT: v_and_b32_e32 v2, v2, v181039; GCN-NEXT: v_and_b32_e32 v3, v3, v191040; GCN-NEXT: v_and_b32_e32 v4, v4, v201041; GCN-NEXT: v_and_b32_e32 v5, v5, v211042; GCN-NEXT: v_and_b32_e32 v6, v6, v221043; GCN-NEXT: v_and_b32_e32 v7, v7, v231044; GCN-NEXT: v_and_b32_e32 v8, v8, v241045; GCN-NEXT: v_and_b32_e32 v9, v9, v251046; GCN-NEXT: v_and_b32_e32 v10, v10, v261047; GCN-NEXT: v_and_b32_e32 v11, v11, v271048; GCN-NEXT: v_and_b32_e32 v12, v12, v281049; GCN-NEXT: v_and_b32_e32 v13, v13, v291050; GCN-NEXT: v_and_b32_e32 v14, v14, v301051; GCN-NEXT: s_waitcnt vmcnt(0)1052; GCN-NEXT: v_and_b32_e32 v15, v15, v161053; GCN-NEXT: s_setpc_b64 s[30:31]1054;1055; GFX10-LABEL: v_and_v2i256:1056; GFX10: ; %bb.0:1057; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1058; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s321059; GFX10-NEXT: v_and_b32_e32 v0, v0, v161060; GFX10-NEXT: v_and_b32_e32 v1, v1, v171061; GFX10-NEXT: v_and_b32_e32 v2, v2, v181062; GFX10-NEXT: v_and_b32_e32 v3, v3, v191063; GFX10-NEXT: v_and_b32_e32 v4, v4, v201064; GFX10-NEXT: v_and_b32_e32 v5, v5, v211065; GFX10-NEXT: v_and_b32_e32 v6, v6, v221066; GFX10-NEXT: v_and_b32_e32 v7, v7, v231067; GFX10-NEXT: v_and_b32_e32 v8, v8, v241068; GFX10-NEXT: v_and_b32_e32 v9, v9, v251069; GFX10-NEXT: v_and_b32_e32 v10, v10, v261070; GFX10-NEXT: v_and_b32_e32 v11, v11, v271071; GFX10-NEXT: v_and_b32_e32 v12, v12, v281072; GFX10-NEXT: v_and_b32_e32 v13, v13, v291073; GFX10-NEXT: v_and_b32_e32 v14, v14, v301074; GFX10-NEXT: s_waitcnt vmcnt(0)1075; GFX10-NEXT: v_and_b32_e32 v15, v15, v311076; GFX10-NEXT: s_setpc_b64 s[30:31]1077;1078; GFX11-LABEL: v_and_v2i256:1079; GFX11: ; %bb.0:1080; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1081; GFX11-NEXT: scratch_load_b32 v31, off, s321082; GFX11-NEXT: v_and_b32_e32 v0, v0, v161083; GFX11-NEXT: v_and_b32_e32 v1, v1, v171084; GFX11-NEXT: v_and_b32_e32 v2, v2, v181085; GFX11-NEXT: v_and_b32_e32 v3, v3, v191086; GFX11-NEXT: v_and_b32_e32 v4, v4, v201087; GFX11-NEXT: v_and_b32_e32 v5, v5, v211088; GFX11-NEXT: v_and_b32_e32 v6, v6, v221089; GFX11-NEXT: v_and_b32_e32 v7, v7, v231090; GFX11-NEXT: v_and_b32_e32 v8, v8, v241091; GFX11-NEXT: v_and_b32_e32 v9, v9, v251092; GFX11-NEXT: v_and_b32_e32 v10, v10, v261093; GFX11-NEXT: v_and_b32_e32 v11, v11, v271094; GFX11-NEXT: v_and_b32_e32 v12, v12, v281095; GFX11-NEXT: v_and_b32_e32 v13, v13, v291096; GFX11-NEXT: v_and_b32_e32 v14, v14, v301097; GFX11-NEXT: s_waitcnt vmcnt(0)1098; GFX11-NEXT: v_and_b32_e32 v15, v15, v311099; GFX11-NEXT: s_setpc_b64 s[30:31]1100;1101; GFX12-LABEL: v_and_v2i256:1102; GFX12: ; %bb.0:1103; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01104; GFX12-NEXT: s_wait_expcnt 0x01105; GFX12-NEXT: s_wait_samplecnt 0x01106; GFX12-NEXT: s_wait_bvhcnt 0x01107; GFX12-NEXT: s_wait_kmcnt 0x01108; GFX12-NEXT: scratch_load_b32 v31, off, s321109; GFX12-NEXT: v_and_b32_e32 v0, v0, v161110; GFX12-NEXT: v_and_b32_e32 v1, v1, v171111; GFX12-NEXT: v_and_b32_e32 v2, v2, v181112; GFX12-NEXT: v_and_b32_e32 v3, v3, v191113; GFX12-NEXT: v_and_b32_e32 v4, v4, v201114; GFX12-NEXT: v_and_b32_e32 v5, v5, v211115; GFX12-NEXT: v_and_b32_e32 v6, v6, v221116; GFX12-NEXT: v_and_b32_e32 v7, v7, v231117; GFX12-NEXT: v_and_b32_e32 v8, v8, v241118; GFX12-NEXT: v_and_b32_e32 v9, v9, v251119; GFX12-NEXT: v_and_b32_e32 v10, v10, v261120; GFX12-NEXT: v_and_b32_e32 v11, v11, v271121; GFX12-NEXT: v_and_b32_e32 v12, v12, v281122; GFX12-NEXT: v_and_b32_e32 v13, v13, v291123; GFX12-NEXT: v_and_b32_e32 v14, v14, v301124; GFX12-NEXT: s_wait_loadcnt 0x01125; GFX12-NEXT: v_and_b32_e32 v15, v15, v311126; GFX12-NEXT: s_setpc_b64 s[30:31]1127 %and = and <2 x i256> %a, %b1128 ret <2 x i256> %and1129}1130 1131;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1132; GFX11-FAKE16: {{.*}}1133; GFX11-TRUE16: {{.*}}1134