1121 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s4; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s5; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s6 7define amdgpu_ps i32 @s_andn2_i32(i32 inreg %src0, i32 inreg %src1) {8; GCN-LABEL: s_andn2_i32:9; GCN: ; %bb.0:10; GCN-NEXT: s_andn2_b32 s0, s2, s311; GCN-NEXT: ; return to shader part epilog12;13; GFX10-LABEL: s_andn2_i32:14; GFX10: ; %bb.0:15; GFX10-NEXT: s_andn2_b32 s0, s2, s316; GFX10-NEXT: ; return to shader part epilog17;18; GFX11-LABEL: s_andn2_i32:19; GFX11: ; %bb.0:20; GFX11-NEXT: s_and_not1_b32 s0, s2, s321; GFX11-NEXT: ; return to shader part epilog22 %not.src1 = xor i32 %src1, -123 %and = and i32 %src0, %not.src124 ret i32 %and25}26 27define amdgpu_ps i32 @s_andn2_i32_commute(i32 inreg %src0, i32 inreg %src1) {28; GCN-LABEL: s_andn2_i32_commute:29; GCN: ; %bb.0:30; GCN-NEXT: s_andn2_b32 s0, s2, s331; GCN-NEXT: ; return to shader part epilog32;33; GFX10-LABEL: s_andn2_i32_commute:34; GFX10: ; %bb.0:35; GFX10-NEXT: s_andn2_b32 s0, s2, s336; GFX10-NEXT: ; return to shader part epilog37;38; GFX11-LABEL: s_andn2_i32_commute:39; GFX11: ; %bb.0:40; GFX11-NEXT: s_and_not1_b32 s0, s2, s341; GFX11-NEXT: ; return to shader part epilog42 %not.src1 = xor i32 %src1, -143 %and = and i32 %not.src1, %src044 ret i32 %and45}46 47define amdgpu_ps { i32, i32 } @s_andn2_i32_multi_use(i32 inreg %src0, i32 inreg %src1) {48; GCN-LABEL: s_andn2_i32_multi_use:49; GCN: ; %bb.0:50; GCN-NEXT: s_not_b32 s1, s351; GCN-NEXT: s_andn2_b32 s0, s2, s352; GCN-NEXT: ; return to shader part epilog53;54; GFX10-LABEL: s_andn2_i32_multi_use:55; GFX10: ; %bb.0:56; GFX10-NEXT: s_andn2_b32 s0, s2, s357; GFX10-NEXT: s_not_b32 s1, s358; GFX10-NEXT: ; return to shader part epilog59;60; GFX11-LABEL: s_andn2_i32_multi_use:61; GFX11: ; %bb.0:62; GFX11-NEXT: s_and_not1_b32 s0, s2, s363; GFX11-NEXT: s_not_b32 s1, s364; GFX11-NEXT: ; return to shader part epilog65 %not.src1 = xor i32 %src1, -166 %and = and i32 %src0, %not.src167 %insert.0 = insertvalue { i32, i32 } poison, i32 %and, 068 %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %not.src1, 169 ret { i32, i32 } %insert.170}71 72define amdgpu_ps { i32, i32 } @s_andn2_i32_multi_foldable_use(i32 inreg %src0, i32 inreg %src1, i32 inreg %src2) {73; GCN-LABEL: s_andn2_i32_multi_foldable_use:74; GCN: ; %bb.0:75; GCN-NEXT: s_andn2_b32 s0, s2, s476; GCN-NEXT: s_andn2_b32 s1, s3, s477; GCN-NEXT: ; return to shader part epilog78;79; GFX10-LABEL: s_andn2_i32_multi_foldable_use:80; GFX10: ; %bb.0:81; GFX10-NEXT: s_andn2_b32 s0, s2, s482; GFX10-NEXT: s_andn2_b32 s1, s3, s483; GFX10-NEXT: ; return to shader part epilog84;85; GFX11-LABEL: s_andn2_i32_multi_foldable_use:86; GFX11: ; %bb.0:87; GFX11-NEXT: s_and_not1_b32 s0, s2, s488; GFX11-NEXT: s_and_not1_b32 s1, s3, s489; GFX11-NEXT: ; return to shader part epilog90 %not.src2 = xor i32 %src2, -191 %and0 = and i32 %src0, %not.src292 %and1 = and i32 %src1, %not.src293 %insert.0 = insertvalue { i32, i32 } poison, i32 %and0, 094 %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %and1, 195 ret { i32, i32 } %insert.196}97 98define i32 @v_andn2_i32(i32 %src0, i32 %src1) {99; GCN-LABEL: v_andn2_i32:100; GCN: ; %bb.0:101; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)102; GCN-NEXT: v_bfi_b32 v0, v1, 0, v0103; GCN-NEXT: s_setpc_b64 s[30:31]104;105; GFX10PLUS-LABEL: v_andn2_i32:106; GFX10PLUS: ; %bb.0:107; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)108; GFX10PLUS-NEXT: v_bfi_b32 v0, v1, 0, v0109; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]110 %not.src1 = xor i32 %src1, -1111 %and = and i32 %src0, %not.src1112 ret i32 %and113}114 115define amdgpu_ps float @v_andn2_i32_sv(i32 inreg %src0, i32 %src1) {116; GCN-LABEL: v_andn2_i32_sv:117; GCN: ; %bb.0:118; GCN-NEXT: v_bfi_b32 v0, v0, 0, s2119; GCN-NEXT: ; return to shader part epilog120;121; GFX10PLUS-LABEL: v_andn2_i32_sv:122; GFX10PLUS: ; %bb.0:123; GFX10PLUS-NEXT: v_bfi_b32 v0, v0, 0, s2124; GFX10PLUS-NEXT: ; return to shader part epilog125 %not.src1 = xor i32 %src1, -1126 %and = and i32 %src0, %not.src1127 %cast = bitcast i32 %and to float128 ret float %cast129}130 131define amdgpu_ps float @v_andn2_i32_vs(i32 %src0, i32 inreg %src1) {132; GCN-LABEL: v_andn2_i32_vs:133; GCN: ; %bb.0:134; GCN-NEXT: v_bfi_b32 v0, s2, 0, v0135; GCN-NEXT: ; return to shader part epilog136;137; GFX10PLUS-LABEL: v_andn2_i32_vs:138; GFX10PLUS: ; %bb.0:139; GFX10PLUS-NEXT: v_bfi_b32 v0, s2, 0, v0140; GFX10PLUS-NEXT: ; return to shader part epilog141 %not.src1 = xor i32 %src1, -1142 %and = and i32 %src0, %not.src1143 %cast = bitcast i32 %and to float144 ret float %cast145}146 147define amdgpu_ps i64 @s_andn2_i64(i64 inreg %src0, i64 inreg %src1) {148; GCN-LABEL: s_andn2_i64:149; GCN: ; %bb.0:150; GCN-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]151; GCN-NEXT: ; return to shader part epilog152;153; GFX10-LABEL: s_andn2_i64:154; GFX10: ; %bb.0:155; GFX10-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]156; GFX10-NEXT: ; return to shader part epilog157;158; GFX11-LABEL: s_andn2_i64:159; GFX11: ; %bb.0:160; GFX11-NEXT: s_and_not1_b64 s[0:1], s[2:3], s[4:5]161; GFX11-NEXT: ; return to shader part epilog162 %not.src1 = xor i64 %src1, -1163 %and = and i64 %src0, %not.src1164 ret i64 %and165}166 167define amdgpu_ps i64 @s_andn2_i64_commute(i64 inreg %src0, i64 inreg %src1) {168; GCN-LABEL: s_andn2_i64_commute:169; GCN: ; %bb.0:170; GCN-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]171; GCN-NEXT: ; return to shader part epilog172;173; GFX10-LABEL: s_andn2_i64_commute:174; GFX10: ; %bb.0:175; GFX10-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]176; GFX10-NEXT: ; return to shader part epilog177;178; GFX11-LABEL: s_andn2_i64_commute:179; GFX11: ; %bb.0:180; GFX11-NEXT: s_and_not1_b64 s[0:1], s[2:3], s[4:5]181; GFX11-NEXT: ; return to shader part epilog182 %not.src1 = xor i64 %src1, -1183 %and = and i64 %not.src1, %src0184 ret i64 %and185}186 187define amdgpu_ps { i64, i64 } @s_andn2_i64_multi_foldable_use(i64 inreg %src0, i64 inreg %src1, i64 inreg %src2) {188; GCN-LABEL: s_andn2_i64_multi_foldable_use:189; GCN: ; %bb.0:190; GCN-NEXT: s_andn2_b64 s[0:1], s[2:3], s[6:7]191; GCN-NEXT: s_andn2_b64 s[2:3], s[4:5], s[6:7]192; GCN-NEXT: ; return to shader part epilog193;194; GFX10-LABEL: s_andn2_i64_multi_foldable_use:195; GFX10: ; %bb.0:196; GFX10-NEXT: s_andn2_b64 s[0:1], s[2:3], s[6:7]197; GFX10-NEXT: s_andn2_b64 s[2:3], s[4:5], s[6:7]198; GFX10-NEXT: ; return to shader part epilog199;200; GFX11-LABEL: s_andn2_i64_multi_foldable_use:201; GFX11: ; %bb.0:202; GFX11-NEXT: s_and_not1_b64 s[0:1], s[2:3], s[6:7]203; GFX11-NEXT: s_and_not1_b64 s[2:3], s[4:5], s[6:7]204; GFX11-NEXT: ; return to shader part epilog205 %not.src2 = xor i64 %src2, -1206 %and0 = and i64 %src0, %not.src2207 %and1 = and i64 %src1, %not.src2208 %insert.0 = insertvalue { i64, i64 } poison, i64 %and0, 0209 %insert.1 = insertvalue { i64, i64 } %insert.0, i64 %and1, 1210 ret { i64, i64 } %insert.1211}212 213define amdgpu_ps { i64, i64 } @s_andn2_i64_multi_use(i64 inreg %src0, i64 inreg %src1) {214; GCN-LABEL: s_andn2_i64_multi_use:215; GCN: ; %bb.0:216; GCN-NEXT: s_not_b64 s[6:7], s[4:5]217; GCN-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]218; GCN-NEXT: s_mov_b32 s2, s6219; GCN-NEXT: s_mov_b32 s3, s7220; GCN-NEXT: ; return to shader part epilog221;222; GFX10-LABEL: s_andn2_i64_multi_use:223; GFX10: ; %bb.0:224; GFX10-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]225; GFX10-NEXT: s_not_b64 s[2:3], s[4:5]226; GFX10-NEXT: ; return to shader part epilog227;228; GFX11-LABEL: s_andn2_i64_multi_use:229; GFX11: ; %bb.0:230; GFX11-NEXT: s_and_not1_b64 s[0:1], s[2:3], s[4:5]231; GFX11-NEXT: s_not_b64 s[2:3], s[4:5]232; GFX11-NEXT: ; return to shader part epilog233 %not.src1 = xor i64 %src1, -1234 %and = and i64 %src0, %not.src1235 %insert.0 = insertvalue { i64, i64 } poison, i64 %and, 0236 %insert.1 = insertvalue { i64, i64 } %insert.0, i64 %not.src1, 1237 ret { i64, i64 } %insert.1238}239 240define i64 @v_andn2_i64(i64 %src0, i64 %src1) {241; GCN-LABEL: v_andn2_i64:242; GCN: ; %bb.0:243; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)244; GCN-NEXT: v_bfi_b32 v0, v2, 0, v0245; GCN-NEXT: v_bfi_b32 v1, v3, 0, v1246; GCN-NEXT: s_setpc_b64 s[30:31]247;248; GFX10PLUS-LABEL: v_andn2_i64:249; GFX10PLUS: ; %bb.0:250; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)251; GFX10PLUS-NEXT: v_bfi_b32 v0, v2, 0, v0252; GFX10PLUS-NEXT: v_bfi_b32 v1, v3, 0, v1253; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]254 %not.src1 = xor i64 %src1, -1255 %and = and i64 %src0, %not.src1256 ret i64 %and257}258 259define amdgpu_ps <2 x float> @v_andn2_i64_sv(i64 inreg %src0, i64 %src1) {260; GCN-LABEL: v_andn2_i64_sv:261; GCN: ; %bb.0:262; GCN-NEXT: v_bfi_b32 v0, v0, 0, s2263; GCN-NEXT: v_bfi_b32 v1, v1, 0, s3264; GCN-NEXT: ; return to shader part epilog265;266; GFX10PLUS-LABEL: v_andn2_i64_sv:267; GFX10PLUS: ; %bb.0:268; GFX10PLUS-NEXT: v_bfi_b32 v0, v0, 0, s2269; GFX10PLUS-NEXT: v_bfi_b32 v1, v1, 0, s3270; GFX10PLUS-NEXT: ; return to shader part epilog271 %not.src1 = xor i64 %src1, -1272 %and = and i64 %src0, %not.src1273 %cast = bitcast i64 %and to <2 x float>274 ret <2 x float> %cast275}276 277define amdgpu_ps <2 x float> @v_andn2_i64_vs(i64 %src0, i64 inreg %src1) {278; GCN-LABEL: v_andn2_i64_vs:279; GCN: ; %bb.0:280; GCN-NEXT: s_not_b64 s[0:1], s[2:3]281; GCN-NEXT: v_and_b32_e32 v0, s0, v0282; GCN-NEXT: v_and_b32_e32 v1, s1, v1283; GCN-NEXT: ; return to shader part epilog284;285; GFX10PLUS-LABEL: v_andn2_i64_vs:286; GFX10PLUS: ; %bb.0:287; GFX10PLUS-NEXT: s_not_b64 s[0:1], s[2:3]288; GFX10PLUS-NEXT: v_and_b32_e32 v0, s0, v0289; GFX10PLUS-NEXT: v_and_b32_e32 v1, s1, v1290; GFX10PLUS-NEXT: ; return to shader part epilog291 %not.src1 = xor i64 %src1, -1292 %and = and i64 %src0, %not.src1293 %cast = bitcast i64 %and to <2 x float>294 ret <2 x float> %cast295}296 297define amdgpu_ps <2 x i32> @s_andn2_v2i32(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {298; GCN-LABEL: s_andn2_v2i32:299; GCN: ; %bb.0:300; GCN-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]301; GCN-NEXT: ; return to shader part epilog302;303; GFX10-LABEL: s_andn2_v2i32:304; GFX10: ; %bb.0:305; GFX10-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]306; GFX10-NEXT: ; return to shader part epilog307;308; GFX11-LABEL: s_andn2_v2i32:309; GFX11: ; %bb.0:310; GFX11-NEXT: s_and_not1_b64 s[0:1], s[2:3], s[4:5]311; GFX11-NEXT: ; return to shader part epilog312 %not.src1 = xor <2 x i32> %src1, <i32 -1, i32 -1>313 %and = and <2 x i32> %src0, %not.src1314 ret <2 x i32> %and315}316 317define amdgpu_ps <2 x i32> @s_andn2_v2i32_commute(<2 x i32> inreg %src0, <2 x i32> inreg %src1) {318; GCN-LABEL: s_andn2_v2i32_commute:319; GCN: ; %bb.0:320; GCN-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]321; GCN-NEXT: ; return to shader part epilog322;323; GFX10-LABEL: s_andn2_v2i32_commute:324; GFX10: ; %bb.0:325; GFX10-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]326; GFX10-NEXT: ; return to shader part epilog327;328; GFX11-LABEL: s_andn2_v2i32_commute:329; GFX11: ; %bb.0:330; GFX11-NEXT: s_and_not1_b64 s[0:1], s[2:3], s[4:5]331; GFX11-NEXT: ; return to shader part epilog332 %not.src1 = xor <2 x i32> %src1, <i32 -1, i32 -1>333 %and = and <2 x i32> %not.src1, %src0334 ret <2 x i32> %and335}336 337define amdgpu_ps i16 @s_andn2_i16(i16 inreg %src0, i16 inreg %src1) {338; GCN-LABEL: s_andn2_i16:339; GCN: ; %bb.0:340; GCN-NEXT: s_andn2_b32 s0, s2, s3341; GCN-NEXT: ; return to shader part epilog342;343; GFX10-LABEL: s_andn2_i16:344; GFX10: ; %bb.0:345; GFX10-NEXT: s_andn2_b32 s0, s2, s3346; GFX10-NEXT: ; return to shader part epilog347;348; GFX11-LABEL: s_andn2_i16:349; GFX11: ; %bb.0:350; GFX11-NEXT: s_and_not1_b32 s0, s2, s3351; GFX11-NEXT: ; return to shader part epilog352 %not.src1 = xor i16 %src1, -1353 %and = and i16 %src0, %not.src1354 ret i16 %and355}356 357define amdgpu_ps i16 @s_andn2_i16_commute(i16 inreg %src0, i16 inreg %src1) {358; GCN-LABEL: s_andn2_i16_commute:359; GCN: ; %bb.0:360; GCN-NEXT: s_andn2_b32 s0, s2, s3361; GCN-NEXT: ; return to shader part epilog362;363; GFX10-LABEL: s_andn2_i16_commute:364; GFX10: ; %bb.0:365; GFX10-NEXT: s_andn2_b32 s0, s2, s3366; GFX10-NEXT: ; return to shader part epilog367;368; GFX11-LABEL: s_andn2_i16_commute:369; GFX11: ; %bb.0:370; GFX11-NEXT: s_and_not1_b32 s0, s2, s3371; GFX11-NEXT: ; return to shader part epilog372 %not.src1 = xor i16 %src1, -1373 %and = and i16 %not.src1, %src0374 ret i16 %and375}376 377define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_use(i16 inreg %src0, i16 inreg %src1) {378; GCN-LABEL: s_andn2_i16_multi_use:379; GCN: ; %bb.0:380; GCN-NEXT: s_not_b32 s1, s3381; GCN-NEXT: s_andn2_b32 s0, s2, s3382; GCN-NEXT: ; return to shader part epilog383;384; GFX10-LABEL: s_andn2_i16_multi_use:385; GFX10: ; %bb.0:386; GFX10-NEXT: s_andn2_b32 s0, s2, s3387; GFX10-NEXT: s_not_b32 s1, s3388; GFX10-NEXT: ; return to shader part epilog389;390; GFX11-LABEL: s_andn2_i16_multi_use:391; GFX11: ; %bb.0:392; GFX11-NEXT: s_and_not1_b32 s0, s2, s3393; GFX11-NEXT: s_not_b32 s1, s3394; GFX11-NEXT: ; return to shader part epilog395 %not.src1 = xor i16 %src1, -1396 %and = and i16 %src0, %not.src1397 %insert.0 = insertvalue { i16, i16 } poison, i16 %and, 0398 %insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1399 ret { i16, i16 } %insert.1400}401 402define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_foldable_use(i16 inreg %src0, i16 inreg %src1, i16 inreg %src2) {403; GCN-LABEL: s_andn2_i16_multi_foldable_use:404; GCN: ; %bb.0:405; GCN-NEXT: s_andn2_b32 s0, s2, s4406; GCN-NEXT: s_andn2_b32 s1, s3, s4407; GCN-NEXT: ; return to shader part epilog408;409; GFX10-LABEL: s_andn2_i16_multi_foldable_use:410; GFX10: ; %bb.0:411; GFX10-NEXT: s_andn2_b32 s0, s2, s4412; GFX10-NEXT: s_andn2_b32 s1, s3, s4413; GFX10-NEXT: ; return to shader part epilog414;415; GFX11-LABEL: s_andn2_i16_multi_foldable_use:416; GFX11: ; %bb.0:417; GFX11-NEXT: s_and_not1_b32 s0, s2, s4418; GFX11-NEXT: s_and_not1_b32 s1, s3, s4419; GFX11-NEXT: ; return to shader part epilog420 %not.src2 = xor i16 %src2, -1421 %and0 = and i16 %src0, %not.src2422 %and1 = and i16 %src1, %not.src2423 %insert.0 = insertvalue { i16, i16 } poison, i16 %and0, 0424 %insert.1 = insertvalue { i16, i16 } %insert.0, i16 %and1, 1425 ret { i16, i16 } %insert.1426}427 428define i16 @v_andn2_i16(i16 %src0, i16 %src1) {429; GCN-LABEL: v_andn2_i16:430; GCN: ; %bb.0:431; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)432; GCN-NEXT: v_xor_b32_e32 v1, -1, v1433; GCN-NEXT: v_and_b32_e32 v0, v0, v1434; GCN-NEXT: s_setpc_b64 s[30:31]435;436; GFX10PLUS-LABEL: v_andn2_i16:437; GFX10PLUS: ; %bb.0:438; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)439; GFX10PLUS-NEXT: v_xor_b32_e32 v1, -1, v1440; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v1441; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]442 %not.src1 = xor i16 %src1, -1443 %and = and i16 %src0, %not.src1444 ret i16 %and445}446 447define amdgpu_ps float @v_andn2_i16_sv(i16 inreg %src0, i16 %src1) {448; GCN-LABEL: v_andn2_i16_sv:449; GCN: ; %bb.0:450; GCN-NEXT: v_xor_b32_e32 v0, -1, v0451; GCN-NEXT: v_and_b32_e32 v0, s2, v0452; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0453; GCN-NEXT: ; return to shader part epilog454;455; GFX10PLUS-LABEL: v_andn2_i16_sv:456; GFX10PLUS: ; %bb.0:457; GFX10PLUS-NEXT: v_xor_b32_e32 v0, -1, v0458; GFX10PLUS-NEXT: v_and_b32_e32 v0, s2, v0459; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xffff, v0460; GFX10PLUS-NEXT: ; return to shader part epilog461 %not.src1 = xor i16 %src1, -1462 %and = and i16 %src0, %not.src1463 %zext = zext i16 %and to i32464 %cast.zext = bitcast i32 %zext to float465 ret float %cast.zext466}467 468define amdgpu_ps float @v_andn2_i16_vs(i16 %src0, i16 inreg %src1) {469; GCN-LABEL: v_andn2_i16_vs:470; GCN: ; %bb.0:471; GCN-NEXT: s_not_b32 s0, s2472; GCN-NEXT: v_and_b32_e32 v0, s0, v0473; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0474; GCN-NEXT: ; return to shader part epilog475;476; GFX10PLUS-LABEL: v_andn2_i16_vs:477; GFX10PLUS: ; %bb.0:478; GFX10PLUS-NEXT: s_not_b32 s0, s2479; GFX10PLUS-NEXT: v_and_b32_e32 v0, s0, v0480; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xffff, v0481; GFX10PLUS-NEXT: ; return to shader part epilog482 %not.src1 = xor i16 %src1, -1483 %and = and i16 %src0, %not.src1484 %zext = zext i16 %and to i32485 %cast.zext = bitcast i32 %zext to float486 ret float %cast.zext487}488 489define amdgpu_ps i32 @s_andn2_v2i16(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {490; GFX6-LABEL: s_andn2_v2i16:491; GFX6: ; %bb.0:492; GFX6-NEXT: s_lshl_b32 s0, s3, 16493; GFX6-NEXT: s_and_b32 s1, s2, 0xffff494; GFX6-NEXT: s_or_b32 s0, s0, s1495; GFX6-NEXT: s_lshl_b32 s1, s5, 16496; GFX6-NEXT: s_and_b32 s2, s4, 0xffff497; GFX6-NEXT: s_or_b32 s1, s1, s2498; GFX6-NEXT: s_xor_b32 s1, s1, -1499; GFX6-NEXT: s_and_b32 s0, s0, s1500; GFX6-NEXT: ; return to shader part epilog501;502; GFX9-LABEL: s_andn2_v2i16:503; GFX9: ; %bb.0:504; GFX9-NEXT: s_andn2_b32 s0, s2, s3505; GFX9-NEXT: ; return to shader part epilog506;507; GFX10-LABEL: s_andn2_v2i16:508; GFX10: ; %bb.0:509; GFX10-NEXT: s_andn2_b32 s0, s2, s3510; GFX10-NEXT: ; return to shader part epilog511;512; GFX11-LABEL: s_andn2_v2i16:513; GFX11: ; %bb.0:514; GFX11-NEXT: s_and_not1_b32 s0, s2, s3515; GFX11-NEXT: ; return to shader part epilog516 %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>517 %and = and <2 x i16> %src0, %not.src1518 %cast = bitcast <2 x i16> %and to i32519 ret i32 %cast520}521 522define amdgpu_ps i32 @s_andn2_v2i16_commute(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {523; GFX6-LABEL: s_andn2_v2i16_commute:524; GFX6: ; %bb.0:525; GFX6-NEXT: s_lshl_b32 s0, s3, 16526; GFX6-NEXT: s_and_b32 s1, s2, 0xffff527; GFX6-NEXT: s_or_b32 s0, s0, s1528; GFX6-NEXT: s_lshl_b32 s1, s5, 16529; GFX6-NEXT: s_and_b32 s2, s4, 0xffff530; GFX6-NEXT: s_or_b32 s1, s1, s2531; GFX6-NEXT: s_xor_b32 s1, s1, -1532; GFX6-NEXT: s_and_b32 s0, s1, s0533; GFX6-NEXT: ; return to shader part epilog534;535; GFX9-LABEL: s_andn2_v2i16_commute:536; GFX9: ; %bb.0:537; GFX9-NEXT: s_andn2_b32 s0, s2, s3538; GFX9-NEXT: ; return to shader part epilog539;540; GFX10-LABEL: s_andn2_v2i16_commute:541; GFX10: ; %bb.0:542; GFX10-NEXT: s_andn2_b32 s0, s2, s3543; GFX10-NEXT: ; return to shader part epilog544;545; GFX11-LABEL: s_andn2_v2i16_commute:546; GFX11: ; %bb.0:547; GFX11-NEXT: s_and_not1_b32 s0, s2, s3548; GFX11-NEXT: ; return to shader part epilog549 %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>550 %and = and <2 x i16> %not.src1, %src0551 %cast = bitcast <2 x i16> %and to i32552 ret i32 %cast553}554 555define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {556; GFX6-LABEL: s_andn2_v2i16_multi_use:557; GFX6: ; %bb.0:558; GFX6-NEXT: s_lshl_b32 s0, s3, 16559; GFX6-NEXT: s_and_b32 s1, s2, 0xffff560; GFX6-NEXT: s_or_b32 s0, s0, s1561; GFX6-NEXT: s_lshl_b32 s1, s5, 16562; GFX6-NEXT: s_and_b32 s2, s4, 0xffff563; GFX6-NEXT: s_or_b32 s1, s1, s2564; GFX6-NEXT: s_xor_b32 s1, s1, -1565; GFX6-NEXT: s_and_b32 s0, s0, s1566; GFX6-NEXT: ; return to shader part epilog567;568; GFX9-LABEL: s_andn2_v2i16_multi_use:569; GFX9: ; %bb.0:570; GFX9-NEXT: s_xor_b32 s1, s3, -1571; GFX9-NEXT: s_andn2_b32 s0, s2, s3572; GFX9-NEXT: ; return to shader part epilog573;574; GFX10-LABEL: s_andn2_v2i16_multi_use:575; GFX10: ; %bb.0:576; GFX10-NEXT: s_andn2_b32 s0, s2, s3577; GFX10-NEXT: s_xor_b32 s1, s3, -1578; GFX10-NEXT: ; return to shader part epilog579;580; GFX11-LABEL: s_andn2_v2i16_multi_use:581; GFX11: ; %bb.0:582; GFX11-NEXT: s_and_not1_b32 s0, s2, s3583; GFX11-NEXT: s_xor_b32 s1, s3, -1584; GFX11-NEXT: ; return to shader part epilog585 %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>586 %and = and <2 x i16> %src0, %not.src1587 588 %cast.0 = bitcast <2 x i16> %and to i32589 %cast.1 = bitcast <2 x i16> %not.src1 to i32590 %insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0591 %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1592 ret { i32, i32 } %insert.1593}594 595define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_foldable_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1, <2 x i16> inreg %src2) {596; GFX6-LABEL: s_andn2_v2i16_multi_foldable_use:597; GFX6: ; %bb.0:598; GFX6-NEXT: s_lshl_b32 s0, s3, 16599; GFX6-NEXT: s_and_b32 s1, s2, 0xffff600; GFX6-NEXT: s_or_b32 s0, s0, s1601; GFX6-NEXT: s_lshl_b32 s1, s5, 16602; GFX6-NEXT: s_and_b32 s2, s4, 0xffff603; GFX6-NEXT: s_or_b32 s1, s1, s2604; GFX6-NEXT: s_lshl_b32 s2, s7, 16605; GFX6-NEXT: s_and_b32 s3, s6, 0xffff606; GFX6-NEXT: s_or_b32 s2, s2, s3607; GFX6-NEXT: s_xor_b32 s2, s2, -1608; GFX6-NEXT: s_and_b32 s0, s0, s2609; GFX6-NEXT: s_and_b32 s1, s1, s2610; GFX6-NEXT: ; return to shader part epilog611;612; GFX9-LABEL: s_andn2_v2i16_multi_foldable_use:613; GFX9: ; %bb.0:614; GFX9-NEXT: s_andn2_b32 s0, s2, s4615; GFX9-NEXT: s_andn2_b32 s1, s3, s4616; GFX9-NEXT: ; return to shader part epilog617;618; GFX10-LABEL: s_andn2_v2i16_multi_foldable_use:619; GFX10: ; %bb.0:620; GFX10-NEXT: s_andn2_b32 s0, s2, s4621; GFX10-NEXT: s_andn2_b32 s1, s3, s4622; GFX10-NEXT: ; return to shader part epilog623;624; GFX11-LABEL: s_andn2_v2i16_multi_foldable_use:625; GFX11: ; %bb.0:626; GFX11-NEXT: s_and_not1_b32 s0, s2, s4627; GFX11-NEXT: s_and_not1_b32 s1, s3, s4628; GFX11-NEXT: ; return to shader part epilog629 %not.src2 = xor <2 x i16> %src2, <i16 -1, i16 -1>630 %and0 = and <2 x i16> %src0, %not.src2631 %and1 = and <2 x i16> %src1, %not.src2632 633 %cast.0 = bitcast <2 x i16> %and0 to i32634 %cast.1 = bitcast <2 x i16> %and1 to i32635 %insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0636 %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1637 ret { i32, i32 } %insert.1638}639 640define <2 x i16> @v_andn2_v2i16(<2 x i16> %src0, <2 x i16> %src1) {641; GFX6-LABEL: v_andn2_v2i16:642; GFX6: ; %bb.0:643; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)644; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1645; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0646; GFX6-NEXT: v_or_b32_e32 v0, v1, v0647; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3648; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2649; GFX6-NEXT: v_or_b32_e32 v1, v1, v2650; GFX6-NEXT: v_xor_b32_e32 v1, -1, v1651; GFX6-NEXT: v_and_b32_e32 v0, v0, v1652; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0653; GFX6-NEXT: s_setpc_b64 s[30:31]654;655; GFX9-LABEL: v_andn2_v2i16:656; GFX9: ; %bb.0:657; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)658; GFX9-NEXT: v_xor_b32_e32 v1, -1, v1659; GFX9-NEXT: v_and_b32_e32 v0, v0, v1660; GFX9-NEXT: s_setpc_b64 s[30:31]661;662; GFX10PLUS-LABEL: v_andn2_v2i16:663; GFX10PLUS: ; %bb.0:664; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)665; GFX10PLUS-NEXT: v_xor_b32_e32 v1, -1, v1666; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v1667; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]668 %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>669 %and = and <2 x i16> %src0, %not.src1670 ret <2 x i16> %and671}672 673 674define amdgpu_ps i48 @s_andn2_v3i16(<3 x i16> inreg %src0, <3 x i16> inreg %src1) {675; GFX6-LABEL: s_andn2_v3i16:676; GFX6: ; %bb.0:677; GFX6-NEXT: s_and_b32 s6, s6, 0xffff678; GFX6-NEXT: s_mov_b32 s0, -1679; GFX6-NEXT: s_and_b32 s5, s5, 0xffff680; GFX6-NEXT: s_lshl_b32 s6, s6, 16681; GFX6-NEXT: s_and_b32 s3, s3, 0xffff682; GFX6-NEXT: s_mov_b32 s1, 0xffff683; GFX6-NEXT: s_or_b32 s6, s5, s6684; GFX6-NEXT: s_and_b32 s7, s7, 0xffff685; GFX6-NEXT: s_and_b32 s2, s2, 0xffff686; GFX6-NEXT: s_lshl_b32 s3, s3, 16687; GFX6-NEXT: s_xor_b64 s[0:1], s[6:7], s[0:1]688; GFX6-NEXT: s_or_b32 s2, s2, s3689; GFX6-NEXT: s_and_b32 s3, s4, 0xffff690; GFX6-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]691; GFX6-NEXT: s_lshr_b32 s2, s0, 16692; GFX6-NEXT: s_and_b32 s0, s0, 0xffff693; GFX6-NEXT: s_lshl_b32 s2, s2, 16694; GFX6-NEXT: s_or_b32 s0, s0, s2695; GFX6-NEXT: s_and_b32 s1, s1, 0xffff696; GFX6-NEXT: ; return to shader part epilog697;698; GFX9-LABEL: s_andn2_v3i16:699; GFX9: ; %bb.0:700; GFX9-NEXT: s_mov_b64 s[0:1], -1701; GFX9-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]702; GFX9-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]703; GFX9-NEXT: s_lshr_b32 s2, s0, 16704; GFX9-NEXT: s_and_b32 s0, s0, 0xffff705; GFX9-NEXT: s_lshl_b32 s2, s2, 16706; GFX9-NEXT: s_or_b32 s0, s0, s2707; GFX9-NEXT: s_and_b32 s1, s1, 0xffff708; GFX9-NEXT: ; return to shader part epilog709;710; GFX10PLUS-LABEL: s_andn2_v3i16:711; GFX10PLUS: ; %bb.0:712; GFX10PLUS-NEXT: s_mov_b64 s[0:1], -1713; GFX10PLUS-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]714; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]715; GFX10PLUS-NEXT: s_lshr_b32 s2, s0, 16716; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff717; GFX10PLUS-NEXT: s_lshl_b32 s2, s2, 16718; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xffff719; GFX10PLUS-NEXT: s_or_b32 s0, s0, s2720; GFX10PLUS-NEXT: ; return to shader part epilog721 %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>722 %and = and <3 x i16> %src0, %not.src1723 %cast = bitcast <3 x i16> %and to i48724 ret i48 %cast725}726 727define amdgpu_ps i48 @s_andn2_v3i16_commute(<3 x i16> inreg %src0, <3 x i16> inreg %src1) {728; GFX6-LABEL: s_andn2_v3i16_commute:729; GFX6: ; %bb.0:730; GFX6-NEXT: s_and_b32 s6, s6, 0xffff731; GFX6-NEXT: s_mov_b32 s0, -1732; GFX6-NEXT: s_and_b32 s5, s5, 0xffff733; GFX6-NEXT: s_lshl_b32 s6, s6, 16734; GFX6-NEXT: s_and_b32 s3, s3, 0xffff735; GFX6-NEXT: s_mov_b32 s1, 0xffff736; GFX6-NEXT: s_or_b32 s6, s5, s6737; GFX6-NEXT: s_and_b32 s7, s7, 0xffff738; GFX6-NEXT: s_and_b32 s2, s2, 0xffff739; GFX6-NEXT: s_lshl_b32 s3, s3, 16740; GFX6-NEXT: s_xor_b64 s[0:1], s[6:7], s[0:1]741; GFX6-NEXT: s_or_b32 s2, s2, s3742; GFX6-NEXT: s_and_b32 s3, s4, 0xffff743; GFX6-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]744; GFX6-NEXT: s_lshr_b32 s2, s0, 16745; GFX6-NEXT: s_and_b32 s0, s0, 0xffff746; GFX6-NEXT: s_lshl_b32 s2, s2, 16747; GFX6-NEXT: s_or_b32 s0, s0, s2748; GFX6-NEXT: s_and_b32 s1, s1, 0xffff749; GFX6-NEXT: ; return to shader part epilog750;751; GFX9-LABEL: s_andn2_v3i16_commute:752; GFX9: ; %bb.0:753; GFX9-NEXT: s_mov_b64 s[0:1], -1754; GFX9-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]755; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]756; GFX9-NEXT: s_lshr_b32 s2, s0, 16757; GFX9-NEXT: s_and_b32 s0, s0, 0xffff758; GFX9-NEXT: s_lshl_b32 s2, s2, 16759; GFX9-NEXT: s_or_b32 s0, s0, s2760; GFX9-NEXT: s_and_b32 s1, s1, 0xffff761; GFX9-NEXT: ; return to shader part epilog762;763; GFX10PLUS-LABEL: s_andn2_v3i16_commute:764; GFX10PLUS: ; %bb.0:765; GFX10PLUS-NEXT: s_mov_b64 s[0:1], -1766; GFX10PLUS-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]767; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]768; GFX10PLUS-NEXT: s_lshr_b32 s2, s0, 16769; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff770; GFX10PLUS-NEXT: s_lshl_b32 s2, s2, 16771; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xffff772; GFX10PLUS-NEXT: s_or_b32 s0, s0, s2773; GFX10PLUS-NEXT: ; return to shader part epilog774 %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>775 %and = and <3 x i16> %not.src1, %src0776 %cast = bitcast <3 x i16> %and to i48777 ret i48 %cast778}779 780define amdgpu_ps { i48, i48 } @s_andn2_v3i16_multi_use(<3 x i16> inreg %src0, <3 x i16> inreg %src1) {781; GFX6-LABEL: s_andn2_v3i16_multi_use:782; GFX6: ; %bb.0:783; GFX6-NEXT: s_and_b32 s6, s6, 0xffff784; GFX6-NEXT: s_mov_b32 s0, -1785; GFX6-NEXT: s_and_b32 s5, s5, 0xffff786; GFX6-NEXT: s_lshl_b32 s6, s6, 16787; GFX6-NEXT: s_mov_b32 s1, 0xffff788; GFX6-NEXT: s_or_b32 s6, s5, s6789; GFX6-NEXT: s_and_b32 s7, s7, 0xffff790; GFX6-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1]791; GFX6-NEXT: s_and_b32 s1, s3, 0xffff792; GFX6-NEXT: s_and_b32 s0, s2, 0xffff793; GFX6-NEXT: s_lshl_b32 s1, s1, 16794; GFX6-NEXT: s_or_b32 s0, s0, s1795; GFX6-NEXT: s_and_b32 s1, s4, 0xffff796; GFX6-NEXT: s_and_b64 s[0:1], s[0:1], s[6:7]797; GFX6-NEXT: s_lshr_b32 s2, s0, 16798; GFX6-NEXT: s_lshr_b32 s5, s6, 16799; GFX6-NEXT: s_and_b32 s0, s0, 0xffff800; GFX6-NEXT: s_lshl_b32 s2, s2, 16801; GFX6-NEXT: s_or_b32 s0, s0, s2802; GFX6-NEXT: s_and_b32 s2, s6, 0xffff803; GFX6-NEXT: s_lshl_b32 s3, s5, 16804; GFX6-NEXT: s_and_b32 s1, s1, 0xffff805; GFX6-NEXT: s_or_b32 s2, s2, s3806; GFX6-NEXT: s_and_b32 s3, s7, 0xffff807; GFX6-NEXT: ; return to shader part epilog808;809; GFX9-LABEL: s_andn2_v3i16_multi_use:810; GFX9: ; %bb.0:811; GFX9-NEXT: s_mov_b64 s[0:1], -1812; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1]813; GFX9-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5]814; GFX9-NEXT: s_lshr_b32 s2, s0, 16815; GFX9-NEXT: s_lshr_b32 s6, s4, 16816; GFX9-NEXT: s_and_b32 s0, s0, 0xffff817; GFX9-NEXT: s_lshl_b32 s2, s2, 16818; GFX9-NEXT: s_or_b32 s0, s0, s2819; GFX9-NEXT: s_and_b32 s2, s4, 0xffff820; GFX9-NEXT: s_lshl_b32 s3, s6, 16821; GFX9-NEXT: s_and_b32 s1, s1, 0xffff822; GFX9-NEXT: s_or_b32 s2, s2, s3823; GFX9-NEXT: s_and_b32 s3, s5, 0xffff824; GFX9-NEXT: ; return to shader part epilog825;826; GFX10PLUS-LABEL: s_andn2_v3i16_multi_use:827; GFX10PLUS: ; %bb.0:828; GFX10PLUS-NEXT: s_mov_b64 s[0:1], -1829; GFX10PLUS-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1]830; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5]831; GFX10PLUS-NEXT: s_lshr_b32 s3, s4, 16832; GFX10PLUS-NEXT: s_lshr_b32 s2, s0, 16833; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0xffff834; GFX10PLUS-NEXT: s_lshl_b32 s2, s2, 16835; GFX10PLUS-NEXT: s_lshl_b32 s3, s3, 16836; GFX10PLUS-NEXT: s_or_b32 s0, s0, s2837; GFX10PLUS-NEXT: s_and_b32 s2, s4, 0xffff838; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xffff839; GFX10PLUS-NEXT: s_or_b32 s2, s2, s3840; GFX10PLUS-NEXT: s_and_b32 s3, s5, 0xffff841; GFX10PLUS-NEXT: ; return to shader part epilog842 %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>843 %and = and <3 x i16> %src0, %not.src1844 %cast.0 = bitcast <3 x i16> %and to i48845 %cast.1 = bitcast <3 x i16> %not.src1 to i48846 %insert.0 = insertvalue { i48, i48 } poison, i48 %cast.0, 0847 %insert.1 = insertvalue { i48, i48 } %insert.0, i48 %cast.1, 1848 ret { i48, i48 } %insert.1849}850 851define <3 x i16> @v_andn2_v3i16(<3 x i16> %src0, <3 x i16> %src1) {852; GFX6-LABEL: v_andn2_v3i16:853; GFX6: ; %bb.0:854; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)855; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4856; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3857; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4858; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1859; GFX6-NEXT: v_or_b32_e32 v3, v3, v4860; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0861; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1862; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5863; GFX6-NEXT: v_xor_b32_e32 v3, -1, v3864; GFX6-NEXT: v_or_b32_e32 v0, v0, v1865; GFX6-NEXT: v_xor_b32_e32 v4, 0xfff5, v4866; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2867; GFX6-NEXT: v_and_b32_e32 v0, v0, v3868; GFX6-NEXT: v_and_b32_e32 v2, v1, v4869; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0870; GFX6-NEXT: s_setpc_b64 s[30:31]871;872; GFX9-LABEL: v_andn2_v3i16:873; GFX9: ; %bb.0:874; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)875; GFX9-NEXT: v_xor_b32_e32 v2, -1, v2876; GFX9-NEXT: v_xor_b32_e32 v3, -11, v3877; GFX9-NEXT: v_and_b32_e32 v0, v0, v2878; GFX9-NEXT: v_and_b32_e32 v1, v1, v3879; GFX9-NEXT: s_setpc_b64 s[30:31]880;881; GFX10PLUS-LABEL: v_andn2_v3i16:882; GFX10PLUS: ; %bb.0:883; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)884; GFX10PLUS-NEXT: v_xor_b32_e32 v2, -1, v2885; GFX10PLUS-NEXT: v_xor_b32_e32 v3, -11, v3886; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v2887; GFX10PLUS-NEXT: v_and_b32_e32 v1, v1, v3888; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]889 %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -11>890 %and = and <3 x i16> %src0, %not.src1891 ret <3 x i16> %and892}893 894define amdgpu_ps i64 @s_andn2_v4i16(<4 x i16> inreg %src0, <4 x i16> inreg %src1) {895; GFX6-LABEL: s_andn2_v4i16:896; GFX6: ; %bb.0:897; GFX6-NEXT: s_lshl_b32 s0, s3, 16898; GFX6-NEXT: s_and_b32 s1, s2, 0xffff899; GFX6-NEXT: s_or_b32 s0, s0, s1900; GFX6-NEXT: s_lshl_b32 s1, s5, 16901; GFX6-NEXT: s_and_b32 s2, s4, 0xffff902; GFX6-NEXT: s_or_b32 s1, s1, s2903; GFX6-NEXT: s_lshl_b32 s2, s7, 16904; GFX6-NEXT: s_and_b32 s3, s6, 0xffff905; GFX6-NEXT: s_or_b32 s2, s2, s3906; GFX6-NEXT: s_lshl_b32 s3, s9, 16907; GFX6-NEXT: s_and_b32 s4, s8, 0xffff908; GFX6-NEXT: s_or_b32 s3, s3, s4909; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], -1910; GFX6-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]911; GFX6-NEXT: ; return to shader part epilog912;913; GFX9-LABEL: s_andn2_v4i16:914; GFX9: ; %bb.0:915; GFX9-NEXT: s_mov_b32 s0, -1916; GFX9-NEXT: s_mov_b32 s1, s0917; GFX9-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]918; GFX9-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]919; GFX9-NEXT: ; return to shader part epilog920;921; GFX10PLUS-LABEL: s_andn2_v4i16:922; GFX10PLUS: ; %bb.0:923; GFX10PLUS-NEXT: s_mov_b32 s0, -1924; GFX10PLUS-NEXT: s_mov_b32 s1, s0925; GFX10PLUS-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]926; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]927; GFX10PLUS-NEXT: ; return to shader part epilog928 %not.src1 = xor <4 x i16> %src1, <i16 -1, i16 -1, i16 -1, i16 -1>929 %and = and <4 x i16> %src0, %not.src1930 %cast = bitcast <4 x i16> %and to i64931 ret i64 %cast932}933 934define amdgpu_ps i64 @s_andn2_v4i16_commute(<4 x i16> inreg %src0, <4 x i16> inreg %src1) {935; GFX6-LABEL: s_andn2_v4i16_commute:936; GFX6: ; %bb.0:937; GFX6-NEXT: s_lshl_b32 s0, s3, 16938; GFX6-NEXT: s_and_b32 s1, s2, 0xffff939; GFX6-NEXT: s_or_b32 s0, s0, s1940; GFX6-NEXT: s_lshl_b32 s1, s5, 16941; GFX6-NEXT: s_and_b32 s2, s4, 0xffff942; GFX6-NEXT: s_or_b32 s1, s1, s2943; GFX6-NEXT: s_lshl_b32 s2, s7, 16944; GFX6-NEXT: s_and_b32 s3, s6, 0xffff945; GFX6-NEXT: s_or_b32 s2, s2, s3946; GFX6-NEXT: s_lshl_b32 s3, s9, 16947; GFX6-NEXT: s_and_b32 s4, s8, 0xffff948; GFX6-NEXT: s_or_b32 s3, s3, s4949; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], -1950; GFX6-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]951; GFX6-NEXT: ; return to shader part epilog952;953; GFX9-LABEL: s_andn2_v4i16_commute:954; GFX9: ; %bb.0:955; GFX9-NEXT: s_mov_b32 s0, -1956; GFX9-NEXT: s_mov_b32 s1, s0957; GFX9-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]958; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]959; GFX9-NEXT: ; return to shader part epilog960;961; GFX10PLUS-LABEL: s_andn2_v4i16_commute:962; GFX10PLUS: ; %bb.0:963; GFX10PLUS-NEXT: s_mov_b32 s0, -1964; GFX10PLUS-NEXT: s_mov_b32 s1, s0965; GFX10PLUS-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]966; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]967; GFX10PLUS-NEXT: ; return to shader part epilog968 %not.src1 = xor <4 x i16> %src1, <i16 -1, i16 -1, i16 -1, i16 -1>969 %and = and <4 x i16> %not.src1, %src0970 %cast = bitcast <4 x i16> %and to i64971 ret i64 %cast972}973 974define amdgpu_ps { i64, i64 } @s_andn2_v4i16_multi_use(<4 x i16> inreg %src0, <4 x i16> inreg %src1) {975; GFX6-LABEL: s_andn2_v4i16_multi_use:976; GFX6: ; %bb.0:977; GFX6-NEXT: s_lshl_b32 s0, s3, 16978; GFX6-NEXT: s_and_b32 s1, s2, 0xffff979; GFX6-NEXT: s_or_b32 s0, s0, s1980; GFX6-NEXT: s_lshl_b32 s1, s5, 16981; GFX6-NEXT: s_and_b32 s2, s4, 0xffff982; GFX6-NEXT: s_or_b32 s1, s1, s2983; GFX6-NEXT: s_lshl_b32 s2, s7, 16984; GFX6-NEXT: s_and_b32 s3, s6, 0xffff985; GFX6-NEXT: s_or_b32 s2, s2, s3986; GFX6-NEXT: s_lshl_b32 s3, s9, 16987; GFX6-NEXT: s_and_b32 s4, s8, 0xffff988; GFX6-NEXT: s_or_b32 s3, s3, s4989; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], -1990; GFX6-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]991; GFX6-NEXT: ; return to shader part epilog992;993; GFX9-LABEL: s_andn2_v4i16_multi_use:994; GFX9: ; %bb.0:995; GFX9-NEXT: s_mov_b32 s0, -1996; GFX9-NEXT: s_mov_b32 s1, s0997; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1]998; GFX9-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5]999; GFX9-NEXT: s_mov_b32 s2, s41000; GFX9-NEXT: s_mov_b32 s3, s51001; GFX9-NEXT: ; return to shader part epilog1002;1003; GFX10PLUS-LABEL: s_andn2_v4i16_multi_use:1004; GFX10PLUS: ; %bb.0:1005; GFX10PLUS-NEXT: s_mov_b32 s0, -11006; GFX10PLUS-NEXT: s_mov_b32 s1, s01007; GFX10PLUS-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1]1008; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5]1009; GFX10PLUS-NEXT: s_mov_b32 s2, s41010; GFX10PLUS-NEXT: s_mov_b32 s3, s51011; GFX10PLUS-NEXT: ; return to shader part epilog1012 %not.src1 = xor <4 x i16> %src1, <i16 -1, i16 -1, i16 -1, i16 -1>1013 %and = and <4 x i16> %src0, %not.src11014 1015 %cast.0 = bitcast <4 x i16> %and to i641016 %cast.1 = bitcast <4 x i16> %not.src1 to i641017 %insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 01018 %insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 11019 ret { i64, i64 } %insert.11020}1021 1022define amdgpu_ps { i64, i64 } @s_andn2_v4i16_multi_foldable_use(<4 x i16> inreg %src0, <4 x i16> inreg %src1, <4 x i16> inreg %src2) {1023; GFX6-LABEL: s_andn2_v4i16_multi_foldable_use:1024; GFX6: ; %bb.0:1025; GFX6-NEXT: s_lshl_b32 s0, s3, 161026; GFX6-NEXT: s_and_b32 s1, s2, 0xffff1027; GFX6-NEXT: s_or_b32 s0, s0, s11028; GFX6-NEXT: s_lshl_b32 s1, s5, 161029; GFX6-NEXT: s_and_b32 s2, s4, 0xffff1030; GFX6-NEXT: s_or_b32 s1, s1, s21031; GFX6-NEXT: s_lshl_b32 s2, s7, 161032; GFX6-NEXT: s_and_b32 s3, s6, 0xffff1033; GFX6-NEXT: s_or_b32 s2, s2, s31034; GFX6-NEXT: s_lshl_b32 s3, s9, 161035; GFX6-NEXT: s_and_b32 s4, s8, 0xffff1036; GFX6-NEXT: s_or_b32 s3, s3, s41037; GFX6-NEXT: s_lshl_b32 s4, s11, 161038; GFX6-NEXT: s_and_b32 s5, s10, 0xffff1039; GFX6-NEXT: s_or_b32 s4, s4, s51040; GFX6-NEXT: s_lshl_b32 s5, s13, 161041; GFX6-NEXT: s_and_b32 s6, s12, 0xffff1042; GFX6-NEXT: s_or_b32 s5, s5, s61043; GFX6-NEXT: s_xor_b64 s[4:5], s[4:5], -11044; GFX6-NEXT: s_and_b64 s[0:1], s[0:1], s[4:5]1045; GFX6-NEXT: s_and_b64 s[2:3], s[2:3], s[4:5]1046; GFX6-NEXT: ; return to shader part epilog1047;1048; GFX9-LABEL: s_andn2_v4i16_multi_foldable_use:1049; GFX9: ; %bb.0:1050; GFX9-NEXT: s_mov_b32 s0, -11051; GFX9-NEXT: s_mov_b32 s1, s01052; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1]1053; GFX9-NEXT: s_and_b64 s[0:1], s[2:3], s[6:7]1054; GFX9-NEXT: s_and_b64 s[2:3], s[4:5], s[6:7]1055; GFX9-NEXT: ; return to shader part epilog1056;1057; GFX10PLUS-LABEL: s_andn2_v4i16_multi_foldable_use:1058; GFX10PLUS: ; %bb.0:1059; GFX10PLUS-NEXT: s_mov_b32 s0, -11060; GFX10PLUS-NEXT: s_mov_b32 s1, s01061; GFX10PLUS-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1]1062; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[2:3], s[6:7]1063; GFX10PLUS-NEXT: s_and_b64 s[2:3], s[4:5], s[6:7]1064; GFX10PLUS-NEXT: ; return to shader part epilog1065 %not.src2 = xor <4 x i16> %src2, <i16 -1, i16 -1, i16 -1, i16 -1>1066 %and0 = and <4 x i16> %src0, %not.src21067 %and1 = and <4 x i16> %src1, %not.src21068 1069 %cast.0 = bitcast <4 x i16> %and0 to i641070 %cast.1 = bitcast <4 x i16> %and1 to i641071 %insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 01072 %insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 11073 ret { i64, i64 } %insert.11074}1075 1076define <4 x i16> @v_andn2_v4i16(<4 x i16> %src0, <4 x i16> %src1) {1077; GFX6-LABEL: v_andn2_v4i16:1078; GFX6: ; %bb.0:1079; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1080; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v11081; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v01082; GFX6-NEXT: v_or_b32_e32 v0, v1, v01083; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v31084; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v21085; GFX6-NEXT: v_or_b32_e32 v1, v1, v21086; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v51087; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v41088; GFX6-NEXT: v_or_b32_e32 v2, v2, v31089; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v71090; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v61091; GFX6-NEXT: v_or_b32_e32 v3, v3, v41092; GFX6-NEXT: v_xor_b32_e32 v2, -1, v21093; GFX6-NEXT: v_xor_b32_e32 v3, -1, v31094; GFX6-NEXT: v_and_b32_e32 v0, v0, v21095; GFX6-NEXT: v_and_b32_e32 v2, v1, v31096; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v01097; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v21098; GFX6-NEXT: s_setpc_b64 s[30:31]1099;1100; GFX9-LABEL: v_andn2_v4i16:1101; GFX9: ; %bb.0:1102; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1103; GFX9-NEXT: v_xor_b32_e32 v2, -1, v21104; GFX9-NEXT: v_xor_b32_e32 v3, -1, v31105; GFX9-NEXT: v_and_b32_e32 v0, v0, v21106; GFX9-NEXT: v_and_b32_e32 v1, v1, v31107; GFX9-NEXT: s_setpc_b64 s[30:31]1108;1109; GFX10PLUS-LABEL: v_andn2_v4i16:1110; GFX10PLUS: ; %bb.0:1111; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1112; GFX10PLUS-NEXT: v_xor_b32_e32 v2, -1, v21113; GFX10PLUS-NEXT: v_xor_b32_e32 v3, -1, v31114; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v21115; GFX10PLUS-NEXT: v_and_b32_e32 v1, v1, v31116; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1117 %not.src1 = xor <4 x i16> %src1, <i16 -1, i16 -1, i16 -1, i16 -1>1118 %and = and <4 x i16> %src0, %not.src11119 ret <4 x i16> %and1120}1121