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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s3 4---5name: test_zext_trunc_v2s32_to_v2s16_to_v2s326body: |7 bb.0:8 liveins: $vgpr0_vgpr19 10 ; CHECK-LABEL: name: test_zext_trunc_v2s32_to_v2s16_to_v2s3211 ; CHECK: liveins: $vgpr0_vgpr112 ; CHECK-NEXT: {{ $}}13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr114 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6553515 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)16 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR]]17 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)18 %0:_(<2 x s32>) = COPY $vgpr0_vgpr119 %1:_(<2 x s16>) = G_TRUNC %020 %2:_(<2 x s32>) = G_ZEXT %121 $vgpr0_vgpr1 = COPY %222...23 24---25name: test_zext_trunc_v2s32_to_v2s16_to_v2s6426body: |27 bb.0:28 liveins: $vgpr0_vgpr129 30 ; CHECK-LABEL: name: test_zext_trunc_v2s32_to_v2s16_to_v2s6431 ; CHECK: liveins: $vgpr0_vgpr132 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr134 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)35 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)36 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32)37 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 6553538 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]39 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C]]40 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[AND]](s64), [[AND1]](s64)41 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)42 %0:_(<2 x s32>) = COPY $vgpr0_vgpr143 %1:_(<2 x s16>) = G_TRUNC %044 %2:_(<2 x s64>) = G_ZEXT %145 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %246...47 48---49name: test_zext_trunc_v2s32_to_v2s8_to_v2s1650body: |51 bb.0:52 liveins: $vgpr0_vgpr153 54 ; CHECK-LABEL: name: test_zext_trunc_v2s32_to_v2s8_to_v2s1655 ; CHECK: liveins: $vgpr0_vgpr156 ; CHECK-NEXT: {{ $}}57 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr158 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)59 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25560 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)61 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1662 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C]], [[C1]](s32)63 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[SHL]]64 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)65 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[TRUNC]], [[BITCAST]]66 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](<2 x s16>)67 %0:_(<2 x s32>) = COPY $vgpr0_vgpr168 %1:_(<2 x s8>) = G_TRUNC %069 %2:_(<2 x s16>) = G_ZEXT %170 $vgpr0 = COPY %271...72 73---74name: test_zext_trunc_v3s32_to_v3s16_to_v3s3275body: |76 bb.0:77 liveins: $vgpr0_vgpr1_vgpr278 79 ; CHECK-LABEL: name: test_zext_trunc_v3s32_to_v3s16_to_v3s3280 ; CHECK: liveins: $vgpr0_vgpr1_vgpr281 ; CHECK-NEXT: {{ $}}82 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr283 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6553584 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)85 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32)86 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)87 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR1]]88 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]89 ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](<2 x s32>)90 ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV3]](s32), [[UV4]](s32), [[AND1]](s32)91 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR2]](<3 x s32>)92 %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr293 %1:_(<3 x s16>) = G_TRUNC %094 %2:_(<3 x s32>) = G_ZEXT %195 $vgpr0_vgpr1_vgpr2 = COPY %296...97 98# Test for "Too many bits for uint64_t" assertion when combining99# zexts with wide sources.100---101name: test_zext_128_trunc_s128_merge102body: |103 bb.0:104 liveins: $vgpr0_vgpr1105 106 ; CHECK-LABEL: name: test_zext_128_trunc_s128_merge107 ; CHECK: liveins: $vgpr0_vgpr1108 ; CHECK-NEXT: {{ $}}109 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1110 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1111 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1112 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295113 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]114 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]115 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[AND]](s64), [[AND1]](s64)116 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)117 %0:_(s64) = COPY $vgpr0_vgpr1118 %1:_(s64) = COPY $vgpr0_vgpr1119 %2:_(s128) = G_MERGE_VALUES %0, %1120 %3:_(s96) = G_TRUNC %2121 %4:_(s128) = G_ZEXT %3122 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4123...124 125---126name: test_zext_s8_to_s32_of_sext_s1_to_s8127body: |128 bb.0:129 liveins: $vgpr0, $vgpr1130 131 ; CHECK-LABEL: name: test_zext_s8_to_s32_of_sext_s1_to_s8132 ; CHECK: liveins: $vgpr0, $vgpr1133 ; CHECK-NEXT: {{ $}}134 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0135 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1136 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]137 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)138 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255139 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT]], [[C]]140 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)141 %0:_(s32) = COPY $vgpr0142 %1:_(s32) = COPY $vgpr1143 %2:_(s1) = G_ICMP intpred(eq), %0, %1144 %3:_(s8) = G_SEXT %2145 %4:_(s32) = G_ZEXT %3146 $vgpr0 = COPY %4147...148 149---150name: test_zext_s8_to_s32_of_sext_s1_to_s16151body: |152 bb.0:153 liveins: $vgpr0, $vgpr1154 155 ; CHECK-LABEL: name: test_zext_s8_to_s32_of_sext_s1_to_s16156 ; CHECK: liveins: $vgpr0, $vgpr1157 ; CHECK-NEXT: {{ $}}158 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0159 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1160 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]161 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)162 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535163 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT]], [[C]]164 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)165 %0:_(s32) = COPY $vgpr0166 %1:_(s32) = COPY $vgpr1167 %2:_(s1) = G_ICMP intpred(eq), %0, %1168 %3:_(s16) = G_SEXT %2169 %4:_(s32) = G_ZEXT %3170 $vgpr0 = COPY %4171...172 173---174name: test_zext_s8_to_s32_of_sext_s8_to_s16175body: |176 bb.0:177 liveins: $vgpr0_vgpr1178 179 ; CHECK-LABEL: name: test_zext_s8_to_s32_of_sext_s8_to_s16180 ; CHECK: liveins: $vgpr0_vgpr1181 ; CHECK-NEXT: {{ $}}182 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1183 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)184 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 8185 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535186 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]187 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)188 %0:_(p1) = COPY $vgpr0_vgpr1189 %1:_(s8) = G_LOAD %0 :: (load (s8), addrspace 1)190 %2:_(s16) = G_SEXT %1191 %3:_(s32) = G_ZEXT %2192 $vgpr0 = COPY %3193...194 195---196name: test_zext_v2s8_to_v2s32_of_sext_v2s1_to_v2s8197body: |198 bb.0:199 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3200 201 ; CHECK-LABEL: name: test_zext_v2s8_to_v2s32_of_sext_v2s1_to_v2s8202 ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3203 ; CHECK-NEXT: {{ $}}204 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1205 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3206 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)207 ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)208 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV]](s32), [[UV2]]209 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV1]](s32), [[UV3]]210 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)211 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)212 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1213 ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1214 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)215 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255216 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)217 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR1]]218 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)219 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1220 %1:_(<2 x s32>) = COPY $vgpr2_vgpr3221 %2:_(<2 x s1>) = G_ICMP intpred(eq), %0, %1222 %3:_(<2 x s8>) = G_SEXT %2223 %4:_(<2 x s32>) = G_ZEXT %3224 $vgpr0_vgpr1 = COPY %4225...226 227---228name: test_zext_v2s8_to_v2s32_of_sext_v2s1_to_v2s16229body: |230 bb.0:231 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3232 233 ; CHECK-LABEL: name: test_zext_v2s8_to_v2s32_of_sext_v2s1_to_v2s16234 ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3235 ; CHECK-NEXT: {{ $}}236 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1237 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3238 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)239 ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)240 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV]](s32), [[UV2]]241 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV1]](s32), [[UV3]]242 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)243 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)244 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1245 ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1246 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)247 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535248 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)249 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR1]]250 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)251 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1252 %1:_(<2 x s32>) = COPY $vgpr2_vgpr3253 %2:_(<2 x s1>) = G_ICMP intpred(eq), %0, %1254 %3:_(<2 x s16>) = G_SEXT %2255 %4:_(<2 x s32>) = G_ZEXT %3256 $vgpr0_vgpr1 = COPY %4257...258 259---260name: test_zext_v2s8_to_v2s32_of_sext_v2s8_to_v2s16261body: |262 bb.0:263 liveins: $vgpr0_vgpr1264 265 ; CHECK-LABEL: name: test_zext_v2s8_to_v2s32_of_sext_v2s8_to_v2s16266 ; CHECK: liveins: $vgpr0_vgpr1267 ; CHECK-NEXT: {{ $}}268 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1269 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)270 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8271 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)272 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 8273 ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8274 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)275 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535276 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)277 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR1]]278 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)279 %0:_(p1) = COPY $vgpr0_vgpr1280 %1:_(<2 x s8>) = G_LOAD %0 :: (load (<2 x s8>), addrspace 1)281 %2:_(<2 x s16>) = G_SEXT %1282 %3:_(<2 x s32>) = G_ZEXT %2283 $vgpr0_vgpr1 = COPY %3284...285