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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s4; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s5; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s6; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s7 8define i8 @v_ashr_i8(i8 %value, i8 %amount) {9; GFX6-LABEL: v_ashr_i8:10; GFX6: ; %bb.0:11; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v113; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 814; GFX6-NEXT: v_ashrrev_i32_e32 v0, v1, v015; GFX6-NEXT: s_setpc_b64 s[30:31]16;17; GFX8-LABEL: v_ashr_i8:18; GFX8: ; %bb.0:19; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)20; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_021; GFX8-NEXT: s_setpc_b64 s[30:31]22;23; GFX9-LABEL: v_ashr_i8:24; GFX9: ; %bb.0:25; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)26; GFX9-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_027; GFX9-NEXT: s_setpc_b64 s[30:31]28;29; GFX10PLUS-LABEL: v_ashr_i8:30; GFX10PLUS: ; %bb.0:31; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xff, v133; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 834; GFX10PLUS-NEXT: v_ashrrev_i16 v0, v1, v035; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]36 %result = ashr i8 %value, %amount37 ret i8 %result38}39 40define i8 @v_ashr_i8_7(i8 %value) {41; GFX6-LABEL: v_ashr_i8_7:42; GFX6: ; %bb.0:43; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)44; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 845; GFX6-NEXT: v_ashrrev_i32_e32 v0, 7, v046; GFX6-NEXT: s_setpc_b64 s[30:31]47;48; GFX8-LABEL: v_ashr_i8_7:49; GFX8: ; %bb.0:50; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)51; GFX8-NEXT: v_mov_b32_e32 v1, 752; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_053; GFX8-NEXT: s_setpc_b64 s[30:31]54;55; GFX9-LABEL: v_ashr_i8_7:56; GFX9: ; %bb.0:57; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)58; GFX9-NEXT: v_mov_b32_e32 v1, 759; GFX9-NEXT: v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_060; GFX9-NEXT: s_setpc_b64 s[30:31]61;62; GFX10PLUS-LABEL: v_ashr_i8_7:63; GFX10PLUS: ; %bb.0:64; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)65; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 866; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 7, v067; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]68 %result = ashr i8 %value, 769 ret i8 %result70}71 72define amdgpu_ps i8 @s_ashr_i8(i8 inreg %value, i8 inreg %amount) {73; GFX6-LABEL: s_ashr_i8:74; GFX6: ; %bb.0:75; GFX6-NEXT: s_sext_i32_i8 s0, s076; GFX6-NEXT: s_ashr_i32 s0, s0, s177; GFX6-NEXT: ; return to shader part epilog78;79; GFX8-LABEL: s_ashr_i8:80; GFX8: ; %bb.0:81; GFX8-NEXT: s_and_b32 s1, s1, 0xff82; GFX8-NEXT: s_sext_i32_i8 s0, s083; GFX8-NEXT: s_ashr_i32 s0, s0, s184; GFX8-NEXT: ; return to shader part epilog85;86; GFX9-LABEL: s_ashr_i8:87; GFX9: ; %bb.0:88; GFX9-NEXT: s_and_b32 s1, s1, 0xff89; GFX9-NEXT: s_sext_i32_i8 s0, s090; GFX9-NEXT: s_ashr_i32 s0, s0, s191; GFX9-NEXT: ; return to shader part epilog92;93; GFX10PLUS-LABEL: s_ashr_i8:94; GFX10PLUS: ; %bb.0:95; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xff96; GFX10PLUS-NEXT: s_sext_i32_i8 s0, s097; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s198; GFX10PLUS-NEXT: ; return to shader part epilog99 %result = ashr i8 %value, %amount100 ret i8 %result101}102 103define amdgpu_ps i8 @s_ashr_i8_7(i8 inreg %value) {104; GCN-LABEL: s_ashr_i8_7:105; GCN: ; %bb.0:106; GCN-NEXT: s_sext_i32_i8 s0, s0107; GCN-NEXT: s_ashr_i32 s0, s0, 7108; GCN-NEXT: ; return to shader part epilog109;110; GFX10PLUS-LABEL: s_ashr_i8_7:111; GFX10PLUS: ; %bb.0:112; GFX10PLUS-NEXT: s_sext_i32_i8 s0, s0113; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 7114; GFX10PLUS-NEXT: ; return to shader part epilog115 %result = ashr i8 %value, 7116 ret i8 %result117}118 119 120define i24 @v_ashr_i24(i24 %value, i24 %amount) {121; GCN-LABEL: v_ashr_i24:122; GCN: ; %bb.0:123; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)124; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1125; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24126; GCN-NEXT: v_ashrrev_i32_e32 v0, v1, v0127; GCN-NEXT: s_setpc_b64 s[30:31]128;129; GFX10PLUS-LABEL: v_ashr_i24:130; GFX10PLUS: ; %bb.0:131; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)132; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xffffff, v1133; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 24134; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v1, v0135; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]136 %result = ashr i24 %value, %amount137 ret i24 %result138}139 140define i24 @v_ashr_i24_7(i24 %value) {141; GCN-LABEL: v_ashr_i24_7:142; GCN: ; %bb.0:143; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)144; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24145; GCN-NEXT: v_ashrrev_i32_e32 v0, 7, v0146; GCN-NEXT: s_setpc_b64 s[30:31]147;148; GFX10PLUS-LABEL: v_ashr_i24_7:149; GFX10PLUS: ; %bb.0:150; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)151; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 24152; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 7, v0153; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]154 %result = ashr i24 %value, 7155 ret i24 %result156}157 158define amdgpu_ps i24 @s_ashr_i24(i24 inreg %value, i24 inreg %amount) {159; GCN-LABEL: s_ashr_i24:160; GCN: ; %bb.0:161; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000162; GCN-NEXT: s_ashr_i32 s0, s0, s1163; GCN-NEXT: ; return to shader part epilog164;165; GFX10PLUS-LABEL: s_ashr_i24:166; GFX10PLUS: ; %bb.0:167; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x180000168; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s1169; GFX10PLUS-NEXT: ; return to shader part epilog170 %result = ashr i24 %value, %amount171 ret i24 %result172}173 174define amdgpu_ps i24 @s_ashr_i24_7(i24 inreg %value) {175; GCN-LABEL: s_ashr_i24_7:176; GCN: ; %bb.0:177; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000178; GCN-NEXT: s_ashr_i32 s0, s0, 7179; GCN-NEXT: ; return to shader part epilog180;181; GFX10PLUS-LABEL: s_ashr_i24_7:182; GFX10PLUS: ; %bb.0:183; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x180000184; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 7185; GFX10PLUS-NEXT: ; return to shader part epilog186 %result = ashr i24 %value, 7187 ret i24 %result188}189 190define i32 @v_ashr_i32(i32 %value, i32 %amount) {191; GCN-LABEL: v_ashr_i32:192; GCN: ; %bb.0:193; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)194; GCN-NEXT: v_ashrrev_i32_e32 v0, v1, v0195; GCN-NEXT: s_setpc_b64 s[30:31]196;197; GFX10PLUS-LABEL: v_ashr_i32:198; GFX10PLUS: ; %bb.0:199; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)200; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v1, v0201; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]202 %result = ashr i32 %value, %amount203 ret i32 %result204}205 206define i32 @v_ashr_i32_31(i32 %value) {207; GCN-LABEL: v_ashr_i32_31:208; GCN: ; %bb.0:209; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)210; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0211; GCN-NEXT: s_setpc_b64 s[30:31]212;213; GFX10PLUS-LABEL: v_ashr_i32_31:214; GFX10PLUS: ; %bb.0:215; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)216; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 31, v0217; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]218 %result = ashr i32 %value, 31219 ret i32 %result220}221 222define amdgpu_ps i32 @s_ashr_i32(i32 inreg %value, i32 inreg %amount) {223; GCN-LABEL: s_ashr_i32:224; GCN: ; %bb.0:225; GCN-NEXT: s_ashr_i32 s0, s0, s1226; GCN-NEXT: ; return to shader part epilog227;228; GFX10PLUS-LABEL: s_ashr_i32:229; GFX10PLUS: ; %bb.0:230; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s1231; GFX10PLUS-NEXT: ; return to shader part epilog232 %result = ashr i32 %value, %amount233 ret i32 %result234}235 236define amdgpu_ps i32 @s_ashr_i32_31(i32 inreg %value) {237; GCN-LABEL: s_ashr_i32_31:238; GCN: ; %bb.0:239; GCN-NEXT: s_ashr_i32 s0, s0, 31240; GCN-NEXT: ; return to shader part epilog241;242; GFX10PLUS-LABEL: s_ashr_i32_31:243; GFX10PLUS: ; %bb.0:244; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 31245; GFX10PLUS-NEXT: ; return to shader part epilog246 %result = ashr i32 %value, 31247 ret i32 %result248}249 250define amdgpu_ps float @ashr_i32_sv(i32 inreg %value, i32 %amount) {251; GFX6-LABEL: ashr_i32_sv:252; GFX6: ; %bb.0:253; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0254; GFX6-NEXT: ; return to shader part epilog255;256; GFX8-LABEL: ashr_i32_sv:257; GFX8: ; %bb.0:258; GFX8-NEXT: v_ashrrev_i32_e64 v0, v0, s0259; GFX8-NEXT: ; return to shader part epilog260;261; GFX9-LABEL: ashr_i32_sv:262; GFX9: ; %bb.0:263; GFX9-NEXT: v_ashrrev_i32_e64 v0, v0, s0264; GFX9-NEXT: ; return to shader part epilog265;266; GFX10PLUS-LABEL: ashr_i32_sv:267; GFX10PLUS: ; %bb.0:268; GFX10PLUS-NEXT: v_ashrrev_i32_e64 v0, v0, s0269; GFX10PLUS-NEXT: ; return to shader part epilog270 %result = ashr i32 %value, %amount271 %cast = bitcast i32 %result to float272 ret float %cast273}274 275define amdgpu_ps float @ashr_i32_vs(i32 %value, i32 inreg %amount) {276; GCN-LABEL: ashr_i32_vs:277; GCN: ; %bb.0:278; GCN-NEXT: v_ashrrev_i32_e32 v0, s0, v0279; GCN-NEXT: ; return to shader part epilog280;281; GFX10PLUS-LABEL: ashr_i32_vs:282; GFX10PLUS: ; %bb.0:283; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, s0, v0284; GFX10PLUS-NEXT: ; return to shader part epilog285 %result = ashr i32 %value, %amount286 %cast = bitcast i32 %result to float287 ret float %cast288}289 290define <2 x i32> @v_ashr_v2i32(<2 x i32> %value, <2 x i32> %amount) {291; GCN-LABEL: v_ashr_v2i32:292; GCN: ; %bb.0:293; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)294; GCN-NEXT: v_ashrrev_i32_e32 v0, v2, v0295; GCN-NEXT: v_ashrrev_i32_e32 v1, v3, v1296; GCN-NEXT: s_setpc_b64 s[30:31]297;298; GFX10PLUS-LABEL: v_ashr_v2i32:299; GFX10PLUS: ; %bb.0:300; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)301; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v2, v0302; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, v3, v1303; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]304 %result = ashr <2 x i32> %value, %amount305 ret <2 x i32> %result306}307 308define <2 x i32> @v_ashr_v2i32_31(<2 x i32> %value) {309; GCN-LABEL: v_ashr_v2i32_31:310; GCN: ; %bb.0:311; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)312; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0313; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v1314; GCN-NEXT: s_setpc_b64 s[30:31]315;316; GFX10PLUS-LABEL: v_ashr_v2i32_31:317; GFX10PLUS: ; %bb.0:318; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)319; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 31, v0320; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v1321; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]322 %result = ashr <2 x i32> %value, <i32 31, i32 31>323 ret <2 x i32> %result324}325 326define amdgpu_ps <2 x i32> @s_ashr_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) {327; GCN-LABEL: s_ashr_v2i32:328; GCN: ; %bb.0:329; GCN-NEXT: s_ashr_i32 s0, s0, s2330; GCN-NEXT: s_ashr_i32 s1, s1, s3331; GCN-NEXT: ; return to shader part epilog332;333; GFX10PLUS-LABEL: s_ashr_v2i32:334; GFX10PLUS: ; %bb.0:335; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s2336; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s3337; GFX10PLUS-NEXT: ; return to shader part epilog338 %result = ashr <2 x i32> %value, %amount339 ret <2 x i32> %result340}341 342define <3 x i32> @v_ashr_v3i32(<3 x i32> %value, <3 x i32> %amount) {343; GCN-LABEL: v_ashr_v3i32:344; GCN: ; %bb.0:345; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)346; GCN-NEXT: v_ashrrev_i32_e32 v0, v3, v0347; GCN-NEXT: v_ashrrev_i32_e32 v1, v4, v1348; GCN-NEXT: v_ashrrev_i32_e32 v2, v5, v2349; GCN-NEXT: s_setpc_b64 s[30:31]350;351; GFX10PLUS-LABEL: v_ashr_v3i32:352; GFX10PLUS: ; %bb.0:353; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)354; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v3, v0355; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, v4, v1356; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, v5, v2357; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]358 %result = ashr <3 x i32> %value, %amount359 ret <3 x i32> %result360}361 362define amdgpu_ps <3 x i32> @s_ashr_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) {363; GCN-LABEL: s_ashr_v3i32:364; GCN: ; %bb.0:365; GCN-NEXT: s_ashr_i32 s0, s0, s3366; GCN-NEXT: s_ashr_i32 s1, s1, s4367; GCN-NEXT: s_ashr_i32 s2, s2, s5368; GCN-NEXT: ; return to shader part epilog369;370; GFX10PLUS-LABEL: s_ashr_v3i32:371; GFX10PLUS: ; %bb.0:372; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s3373; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s4374; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s5375; GFX10PLUS-NEXT: ; return to shader part epilog376 %result = ashr <3 x i32> %value, %amount377 ret <3 x i32> %result378}379 380define <4 x i32> @v_ashr_v4i32(<4 x i32> %value, <4 x i32> %amount) {381; GCN-LABEL: v_ashr_v4i32:382; GCN: ; %bb.0:383; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)384; GCN-NEXT: v_ashrrev_i32_e32 v0, v4, v0385; GCN-NEXT: v_ashrrev_i32_e32 v1, v5, v1386; GCN-NEXT: v_ashrrev_i32_e32 v2, v6, v2387; GCN-NEXT: v_ashrrev_i32_e32 v3, v7, v3388; GCN-NEXT: s_setpc_b64 s[30:31]389;390; GFX10PLUS-LABEL: v_ashr_v4i32:391; GFX10PLUS: ; %bb.0:392; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)393; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v4, v0394; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, v5, v1395; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, v6, v2396; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v3, v7, v3397; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]398 %result = ashr <4 x i32> %value, %amount399 ret <4 x i32> %result400}401 402define amdgpu_ps <4 x i32> @s_ashr_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) {403; GCN-LABEL: s_ashr_v4i32:404; GCN: ; %bb.0:405; GCN-NEXT: s_ashr_i32 s0, s0, s4406; GCN-NEXT: s_ashr_i32 s1, s1, s5407; GCN-NEXT: s_ashr_i32 s2, s2, s6408; GCN-NEXT: s_ashr_i32 s3, s3, s7409; GCN-NEXT: ; return to shader part epilog410;411; GFX10PLUS-LABEL: s_ashr_v4i32:412; GFX10PLUS: ; %bb.0:413; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s4414; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s5415; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s6416; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s7417; GFX10PLUS-NEXT: ; return to shader part epilog418 %result = ashr <4 x i32> %value, %amount419 ret <4 x i32> %result420}421 422define <5 x i32> @v_ashr_v5i32(<5 x i32> %value, <5 x i32> %amount) {423; GCN-LABEL: v_ashr_v5i32:424; GCN: ; %bb.0:425; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)426; GCN-NEXT: v_ashrrev_i32_e32 v0, v5, v0427; GCN-NEXT: v_ashrrev_i32_e32 v1, v6, v1428; GCN-NEXT: v_ashrrev_i32_e32 v2, v7, v2429; GCN-NEXT: v_ashrrev_i32_e32 v3, v8, v3430; GCN-NEXT: v_ashrrev_i32_e32 v4, v9, v4431; GCN-NEXT: s_setpc_b64 s[30:31]432;433; GFX10PLUS-LABEL: v_ashr_v5i32:434; GFX10PLUS: ; %bb.0:435; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)436; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, v5, v0437; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, v6, v1438; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, v7, v2439; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v3, v8, v3440; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v4, v9, v4441; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]442 %result = ashr <5 x i32> %value, %amount443 ret <5 x i32> %result444}445 446define amdgpu_ps <5 x i32> @s_ashr_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) {447; GCN-LABEL: s_ashr_v5i32:448; GCN: ; %bb.0:449; GCN-NEXT: s_ashr_i32 s0, s0, s5450; GCN-NEXT: s_ashr_i32 s1, s1, s6451; GCN-NEXT: s_ashr_i32 s2, s2, s7452; GCN-NEXT: s_ashr_i32 s3, s3, s8453; GCN-NEXT: s_ashr_i32 s4, s4, s9454; GCN-NEXT: ; return to shader part epilog455;456; GFX10PLUS-LABEL: s_ashr_v5i32:457; GFX10PLUS: ; %bb.0:458; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s5459; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s6460; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s7461; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s8462; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, s9463; GFX10PLUS-NEXT: ; return to shader part epilog464 %result = ashr <5 x i32> %value, %amount465 ret <5 x i32> %result466}467 468define <16 x i32> @v_ashr_v16i32(<16 x i32> %value, <16 x i32> %amount) {469; GCN-LABEL: v_ashr_v16i32:470; GCN: ; %bb.0:471; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)472; GCN-NEXT: v_ashrrev_i32_e32 v0, v16, v0473; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32474; GCN-NEXT: v_ashrrev_i32_e32 v1, v17, v1475; GCN-NEXT: v_ashrrev_i32_e32 v2, v18, v2476; GCN-NEXT: v_ashrrev_i32_e32 v3, v19, v3477; GCN-NEXT: v_ashrrev_i32_e32 v4, v20, v4478; GCN-NEXT: v_ashrrev_i32_e32 v5, v21, v5479; GCN-NEXT: v_ashrrev_i32_e32 v6, v22, v6480; GCN-NEXT: v_ashrrev_i32_e32 v7, v23, v7481; GCN-NEXT: v_ashrrev_i32_e32 v8, v24, v8482; GCN-NEXT: v_ashrrev_i32_e32 v9, v25, v9483; GCN-NEXT: v_ashrrev_i32_e32 v10, v26, v10484; GCN-NEXT: v_ashrrev_i32_e32 v11, v27, v11485; GCN-NEXT: v_ashrrev_i32_e32 v12, v28, v12486; GCN-NEXT: v_ashrrev_i32_e32 v13, v29, v13487; GCN-NEXT: v_ashrrev_i32_e32 v14, v30, v14488; GCN-NEXT: s_waitcnt vmcnt(0)489; GCN-NEXT: v_ashrrev_i32_e32 v15, v16, v15490; GCN-NEXT: s_setpc_b64 s[30:31]491;492; GFX10-LABEL: v_ashr_v16i32:493; GFX10: ; %bb.0:494; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)495; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32496; GFX10-NEXT: v_ashrrev_i32_e32 v0, v16, v0497; GFX10-NEXT: v_ashrrev_i32_e32 v1, v17, v1498; GFX10-NEXT: v_ashrrev_i32_e32 v2, v18, v2499; GFX10-NEXT: v_ashrrev_i32_e32 v3, v19, v3500; GFX10-NEXT: v_ashrrev_i32_e32 v4, v20, v4501; GFX10-NEXT: v_ashrrev_i32_e32 v5, v21, v5502; GFX10-NEXT: v_ashrrev_i32_e32 v6, v22, v6503; GFX10-NEXT: v_ashrrev_i32_e32 v7, v23, v7504; GFX10-NEXT: v_ashrrev_i32_e32 v8, v24, v8505; GFX10-NEXT: v_ashrrev_i32_e32 v9, v25, v9506; GFX10-NEXT: v_ashrrev_i32_e32 v10, v26, v10507; GFX10-NEXT: v_ashrrev_i32_e32 v11, v27, v11508; GFX10-NEXT: v_ashrrev_i32_e32 v12, v28, v12509; GFX10-NEXT: v_ashrrev_i32_e32 v13, v29, v13510; GFX10-NEXT: v_ashrrev_i32_e32 v14, v30, v14511; GFX10-NEXT: s_waitcnt vmcnt(0)512; GFX10-NEXT: v_ashrrev_i32_e32 v15, v31, v15513; GFX10-NEXT: s_setpc_b64 s[30:31]514;515; GFX11-LABEL: v_ashr_v16i32:516; GFX11: ; %bb.0:517; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)518; GFX11-NEXT: scratch_load_b32 v31, off, s32519; GFX11-NEXT: v_ashrrev_i32_e32 v0, v16, v0520; GFX11-NEXT: v_ashrrev_i32_e32 v1, v17, v1521; GFX11-NEXT: v_ashrrev_i32_e32 v2, v18, v2522; GFX11-NEXT: v_ashrrev_i32_e32 v3, v19, v3523; GFX11-NEXT: v_ashrrev_i32_e32 v4, v20, v4524; GFX11-NEXT: v_ashrrev_i32_e32 v5, v21, v5525; GFX11-NEXT: v_ashrrev_i32_e32 v6, v22, v6526; GFX11-NEXT: v_ashrrev_i32_e32 v7, v23, v7527; GFX11-NEXT: v_ashrrev_i32_e32 v8, v24, v8528; GFX11-NEXT: v_ashrrev_i32_e32 v9, v25, v9529; GFX11-NEXT: v_ashrrev_i32_e32 v10, v26, v10530; GFX11-NEXT: v_ashrrev_i32_e32 v11, v27, v11531; GFX11-NEXT: v_ashrrev_i32_e32 v12, v28, v12532; GFX11-NEXT: v_ashrrev_i32_e32 v13, v29, v13533; GFX11-NEXT: v_ashrrev_i32_e32 v14, v30, v14534; GFX11-NEXT: s_waitcnt vmcnt(0)535; GFX11-NEXT: v_ashrrev_i32_e32 v15, v31, v15536; GFX11-NEXT: s_setpc_b64 s[30:31]537 %result = ashr <16 x i32> %value, %amount538 ret <16 x i32> %result539}540 541define amdgpu_ps <16 x i32> @s_ashr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) {542; GCN-LABEL: s_ashr_v16i32:543; GCN: ; %bb.0:544; GCN-NEXT: s_ashr_i32 s0, s0, s16545; GCN-NEXT: s_ashr_i32 s1, s1, s17546; GCN-NEXT: s_ashr_i32 s2, s2, s18547; GCN-NEXT: s_ashr_i32 s3, s3, s19548; GCN-NEXT: s_ashr_i32 s4, s4, s20549; GCN-NEXT: s_ashr_i32 s5, s5, s21550; GCN-NEXT: s_ashr_i32 s6, s6, s22551; GCN-NEXT: s_ashr_i32 s7, s7, s23552; GCN-NEXT: s_ashr_i32 s8, s8, s24553; GCN-NEXT: s_ashr_i32 s9, s9, s25554; GCN-NEXT: s_ashr_i32 s10, s10, s26555; GCN-NEXT: s_ashr_i32 s11, s11, s27556; GCN-NEXT: s_ashr_i32 s12, s12, s28557; GCN-NEXT: s_ashr_i32 s13, s13, s29558; GCN-NEXT: s_ashr_i32 s14, s14, s30559; GCN-NEXT: s_ashr_i32 s15, s15, s31560; GCN-NEXT: ; return to shader part epilog561;562; GFX10PLUS-LABEL: s_ashr_v16i32:563; GFX10PLUS: ; %bb.0:564; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s16565; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s17566; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s18567; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s19568; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, s20569; GFX10PLUS-NEXT: s_ashr_i32 s5, s5, s21570; GFX10PLUS-NEXT: s_ashr_i32 s6, s6, s22571; GFX10PLUS-NEXT: s_ashr_i32 s7, s7, s23572; GFX10PLUS-NEXT: s_ashr_i32 s8, s8, s24573; GFX10PLUS-NEXT: s_ashr_i32 s9, s9, s25574; GFX10PLUS-NEXT: s_ashr_i32 s10, s10, s26575; GFX10PLUS-NEXT: s_ashr_i32 s11, s11, s27576; GFX10PLUS-NEXT: s_ashr_i32 s12, s12, s28577; GFX10PLUS-NEXT: s_ashr_i32 s13, s13, s29578; GFX10PLUS-NEXT: s_ashr_i32 s14, s14, s30579; GFX10PLUS-NEXT: s_ashr_i32 s15, s15, s31580; GFX10PLUS-NEXT: ; return to shader part epilog581 %result = ashr <16 x i32> %value, %amount582 ret <16 x i32> %result583}584 585define i16 @v_ashr_i16(i16 %value, i16 %amount) {586; GFX6-LABEL: v_ashr_i16:587; GFX6: ; %bb.0:588; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)589; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1590; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16591; GFX6-NEXT: v_ashrrev_i32_e32 v0, v1, v0592; GFX6-NEXT: s_setpc_b64 s[30:31]593;594; GFX8-LABEL: v_ashr_i16:595; GFX8: ; %bb.0:596; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)597; GFX8-NEXT: v_ashrrev_i16_e32 v0, v1, v0598; GFX8-NEXT: s_setpc_b64 s[30:31]599;600; GFX9-LABEL: v_ashr_i16:601; GFX9: ; %bb.0:602; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)603; GFX9-NEXT: v_ashrrev_i16_e32 v0, v1, v0604; GFX9-NEXT: s_setpc_b64 s[30:31]605;606; GFX10PLUS-LABEL: v_ashr_i16:607; GFX10PLUS: ; %bb.0:608; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)609; GFX10PLUS-NEXT: v_ashrrev_i16 v0, v1, v0610; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]611 %result = ashr i16 %value, %amount612 ret i16 %result613}614 615define i16 @v_ashr_i16_15(i16 %value) {616; GFX6-LABEL: v_ashr_i16_15:617; GFX6: ; %bb.0:618; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)619; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16620; GFX6-NEXT: v_ashrrev_i32_e32 v0, 15, v0621; GFX6-NEXT: s_setpc_b64 s[30:31]622;623; GFX8-LABEL: v_ashr_i16_15:624; GFX8: ; %bb.0:625; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)626; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v0627; GFX8-NEXT: s_setpc_b64 s[30:31]628;629; GFX9-LABEL: v_ashr_i16_15:630; GFX9: ; %bb.0:631; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)632; GFX9-NEXT: v_ashrrev_i16_e32 v0, 15, v0633; GFX9-NEXT: s_setpc_b64 s[30:31]634;635; GFX10PLUS-LABEL: v_ashr_i16_15:636; GFX10PLUS: ; %bb.0:637; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)638; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 15, v0639; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]640 %result = ashr i16 %value, 15641 ret i16 %result642}643 644define amdgpu_ps i16 @s_ashr_i16(i16 inreg %value, i16 inreg %amount) {645; GCN-LABEL: s_ashr_i16:646; GCN: ; %bb.0:647; GCN-NEXT: s_sext_i32_i16 s0, s0648; GCN-NEXT: s_ashr_i32 s0, s0, s1649; GCN-NEXT: ; return to shader part epilog650;651; GFX10PLUS-LABEL: s_ashr_i16:652; GFX10PLUS: ; %bb.0:653; GFX10PLUS-NEXT: s_sext_i32_i16 s0, s0654; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s1655; GFX10PLUS-NEXT: ; return to shader part epilog656 %result = ashr i16 %value, %amount657 ret i16 %result658}659 660define amdgpu_ps i16 @s_ashr_i16_15(i16 inreg %value) {661; GCN-LABEL: s_ashr_i16_15:662; GCN: ; %bb.0:663; GCN-NEXT: s_sext_i32_i16 s0, s0664; GCN-NEXT: s_ashr_i32 s0, s0, 15665; GCN-NEXT: ; return to shader part epilog666;667; GFX10PLUS-LABEL: s_ashr_i16_15:668; GFX10PLUS: ; %bb.0:669; GFX10PLUS-NEXT: s_sext_i32_i16 s0, s0670; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 15671; GFX10PLUS-NEXT: ; return to shader part epilog672 %result = ashr i16 %value, 15673 ret i16 %result674}675 676define amdgpu_ps half @ashr_i16_sv(i16 inreg %value, i16 %amount) {677; GFX6-LABEL: ashr_i16_sv:678; GFX6: ; %bb.0:679; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0680; GFX6-NEXT: s_sext_i32_i16 s0, s0681; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0682; GFX6-NEXT: ; return to shader part epilog683;684; GFX8-LABEL: ashr_i16_sv:685; GFX8: ; %bb.0:686; GFX8-NEXT: v_ashrrev_i16_e64 v0, v0, s0687; GFX8-NEXT: ; return to shader part epilog688;689; GFX9-LABEL: ashr_i16_sv:690; GFX9: ; %bb.0:691; GFX9-NEXT: v_ashrrev_i16_e64 v0, v0, s0692; GFX9-NEXT: ; return to shader part epilog693;694; GFX10PLUS-LABEL: ashr_i16_sv:695; GFX10PLUS: ; %bb.0:696; GFX10PLUS-NEXT: v_ashrrev_i16 v0, v0, s0697; GFX10PLUS-NEXT: ; return to shader part epilog698 %result = ashr i16 %value, %amount699 %cast = bitcast i16 %result to half700 ret half %cast701}702 703define amdgpu_ps half @ashr_i16_vs(i16 %value, i16 inreg %amount) {704; GFX6-LABEL: ashr_i16_vs:705; GFX6: ; %bb.0:706; GFX6-NEXT: s_and_b32 s0, s0, 0xffff707; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16708; GFX6-NEXT: v_ashrrev_i32_e32 v0, s0, v0709; GFX6-NEXT: ; return to shader part epilog710;711; GFX8-LABEL: ashr_i16_vs:712; GFX8: ; %bb.0:713; GFX8-NEXT: v_ashrrev_i16_e32 v0, s0, v0714; GFX8-NEXT: ; return to shader part epilog715;716; GFX9-LABEL: ashr_i16_vs:717; GFX9: ; %bb.0:718; GFX9-NEXT: v_ashrrev_i16_e32 v0, s0, v0719; GFX9-NEXT: ; return to shader part epilog720;721; GFX10PLUS-LABEL: ashr_i16_vs:722; GFX10PLUS: ; %bb.0:723; GFX10PLUS-NEXT: v_ashrrev_i16 v0, s0, v0724; GFX10PLUS-NEXT: ; return to shader part epilog725 %result = ashr i16 %value, %amount726 %cast = bitcast i16 %result to half727 ret half %cast728}729 730define <2 x i16> @v_ashr_v2i16(<2 x i16> %value, <2 x i16> %amount) {731; GFX6-LABEL: v_ashr_v2i16:732; GFX6: ; %bb.0:733; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)734; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2735; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16736; GFX6-NEXT: v_ashrrev_i32_e32 v0, v2, v0737; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3738; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16739; GFX6-NEXT: v_ashrrev_i32_e32 v1, v2, v1740; GFX6-NEXT: s_setpc_b64 s[30:31]741;742; GFX8-LABEL: v_ashr_v2i16:743; GFX8: ; %bb.0:744; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)745; GFX8-NEXT: v_ashrrev_i16_e32 v2, v1, v0746; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1747; GFX8-NEXT: v_or_b32_e32 v0, v2, v0748; GFX8-NEXT: s_setpc_b64 s[30:31]749;750; GFX9-LABEL: v_ashr_v2i16:751; GFX9: ; %bb.0:752; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)753; GFX9-NEXT: v_pk_ashrrev_i16 v0, v1, v0754; GFX9-NEXT: s_setpc_b64 s[30:31]755;756; GFX10PLUS-LABEL: v_ashr_v2i16:757; GFX10PLUS: ; %bb.0:758; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)759; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, v1, v0760; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]761 %result = ashr <2 x i16> %value, %amount762 ret <2 x i16> %result763}764 765define <2 x i16> @v_ashr_v2i16_15(<2 x i16> %value) {766; GFX6-LABEL: v_ashr_v2i16_15:767; GFX6: ; %bb.0:768; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)769; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16770; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16771; GFX6-NEXT: v_ashrrev_i32_e32 v0, 15, v0772; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v1773; GFX6-NEXT: s_setpc_b64 s[30:31]774;775; GFX8-LABEL: v_ashr_v2i16_15:776; GFX8: ; %bb.0:777; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)778; GFX8-NEXT: v_mov_b32_e32 v2, 15779; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v0780; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1781; GFX8-NEXT: v_or_b32_e32 v0, v1, v0782; GFX8-NEXT: s_setpc_b64 s[30:31]783;784; GFX9-LABEL: v_ashr_v2i16_15:785; GFX9: ; %bb.0:786; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)787; GFX9-NEXT: v_pk_ashrrev_i16 v0, 15, v0 op_sel_hi:[0,1]788; GFX9-NEXT: s_setpc_b64 s[30:31]789;790; GFX10PLUS-LABEL: v_ashr_v2i16_15:791; GFX10PLUS: ; %bb.0:792; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)793; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, 15, v0 op_sel_hi:[0,1]794; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]795 %result = ashr <2 x i16> %value, <i16 15, i16 15>796 ret <2 x i16> %result797}798 799define amdgpu_ps i32 @s_ashr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) {800; GFX6-LABEL: s_ashr_v2i16:801; GFX6: ; %bb.0:802; GFX6-NEXT: s_sext_i32_i16 s1, s1803; GFX6-NEXT: s_sext_i32_i16 s0, s0804; GFX6-NEXT: s_ashr_i32 s1, s1, s3805; GFX6-NEXT: s_ashr_i32 s0, s0, s2806; GFX6-NEXT: s_and_b32 s1, s1, 0xffff807; GFX6-NEXT: s_and_b32 s0, s0, 0xffff808; GFX6-NEXT: s_lshl_b32 s1, s1, 16809; GFX6-NEXT: s_or_b32 s0, s0, s1810; GFX6-NEXT: ; return to shader part epilog811;812; GFX8-LABEL: s_ashr_v2i16:813; GFX8: ; %bb.0:814; GFX8-NEXT: s_lshr_b32 s2, s0, 16815; GFX8-NEXT: s_sext_i32_i16 s0, s0816; GFX8-NEXT: s_lshr_b32 s3, s1, 16817; GFX8-NEXT: s_ashr_i32 s0, s0, s1818; GFX8-NEXT: s_sext_i32_i16 s1, s2819; GFX8-NEXT: s_ashr_i32 s1, s1, s3820; GFX8-NEXT: s_and_b32 s1, 0xffff, s1821; GFX8-NEXT: s_and_b32 s0, 0xffff, s0822; GFX8-NEXT: s_lshl_b32 s1, s1, 16823; GFX8-NEXT: s_or_b32 s0, s0, s1824; GFX8-NEXT: ; return to shader part epilog825;826; GFX9-LABEL: s_ashr_v2i16:827; GFX9: ; %bb.0:828; GFX9-NEXT: s_sext_i32_i16 s2, s0829; GFX9-NEXT: s_ashr_i32 s0, s0, 16830; GFX9-NEXT: s_sext_i32_i16 s3, s1831; GFX9-NEXT: s_ashr_i32 s1, s1, 16832; GFX9-NEXT: s_ashr_i32 s2, s2, s3833; GFX9-NEXT: s_ashr_i32 s0, s0, s1834; GFX9-NEXT: s_pack_ll_b32_b16 s0, s2, s0835; GFX9-NEXT: ; return to shader part epilog836;837; GFX10PLUS-LABEL: s_ashr_v2i16:838; GFX10PLUS: ; %bb.0:839; GFX10PLUS-NEXT: s_sext_i32_i16 s2, s0840; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 16841; GFX10PLUS-NEXT: s_sext_i32_i16 s3, s1842; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 16843; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s3844; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s1845; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s2, s0846; GFX10PLUS-NEXT: ; return to shader part epilog847 %result = ashr <2 x i16> %value, %amount848 %cast = bitcast <2 x i16> %result to i32849 ret i32 %cast850}851 852define amdgpu_ps float @ashr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {853; GFX6-LABEL: ashr_v2i16_sv:854; GFX6: ; %bb.0:855; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0856; GFX6-NEXT: s_sext_i32_i16 s0, s0857; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0858; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1859; GFX6-NEXT: s_sext_i32_i16 s0, s1860; GFX6-NEXT: v_ashr_i32_e32 v1, s0, v1861; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1862; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0863; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1864; GFX6-NEXT: v_or_b32_e32 v0, v0, v1865; GFX6-NEXT: ; return to shader part epilog866;867; GFX8-LABEL: ashr_v2i16_sv:868; GFX8: ; %bb.0:869; GFX8-NEXT: s_lshr_b32 s1, s0, 16870; GFX8-NEXT: v_mov_b32_e32 v2, s1871; GFX8-NEXT: v_ashrrev_i16_e64 v1, v0, s0872; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD873; GFX8-NEXT: v_or_b32_e32 v0, v1, v0874; GFX8-NEXT: ; return to shader part epilog875;876; GFX9-LABEL: ashr_v2i16_sv:877; GFX9: ; %bb.0:878; GFX9-NEXT: v_pk_ashrrev_i16 v0, v0, s0879; GFX9-NEXT: ; return to shader part epilog880;881; GFX10PLUS-LABEL: ashr_v2i16_sv:882; GFX10PLUS: ; %bb.0:883; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, v0, s0884; GFX10PLUS-NEXT: ; return to shader part epilog885 %result = ashr <2 x i16> %value, %amount886 %cast = bitcast <2 x i16> %result to float887 ret float %cast888}889 890define amdgpu_ps float @ashr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {891; GFX6-LABEL: ashr_v2i16_vs:892; GFX6: ; %bb.0:893; GFX6-NEXT: s_and_b32 s0, s0, 0xffff894; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16895; GFX6-NEXT: v_ashrrev_i32_e32 v0, s0, v0896; GFX6-NEXT: s_and_b32 s0, s1, 0xffff897; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16898; GFX6-NEXT: v_ashrrev_i32_e32 v1, s0, v1899; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1900; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0901; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1902; GFX6-NEXT: v_or_b32_e32 v0, v0, v1903; GFX6-NEXT: ; return to shader part epilog904;905; GFX8-LABEL: ashr_v2i16_vs:906; GFX8: ; %bb.0:907; GFX8-NEXT: s_lshr_b32 s1, s0, 16908; GFX8-NEXT: v_mov_b32_e32 v2, s1909; GFX8-NEXT: v_ashrrev_i16_e32 v1, s0, v0910; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1911; GFX8-NEXT: v_or_b32_e32 v0, v1, v0912; GFX8-NEXT: ; return to shader part epilog913;914; GFX9-LABEL: ashr_v2i16_vs:915; GFX9: ; %bb.0:916; GFX9-NEXT: v_pk_ashrrev_i16 v0, s0, v0917; GFX9-NEXT: ; return to shader part epilog918;919; GFX10PLUS-LABEL: ashr_v2i16_vs:920; GFX10PLUS: ; %bb.0:921; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, s0, v0922; GFX10PLUS-NEXT: ; return to shader part epilog923 %result = ashr <2 x i16> %value, %amount924 %cast = bitcast <2 x i16> %result to float925 ret float %cast926}927 928; FIXME929; define <3 x i16> @v_ashr_v3i16(<3 x i16> %value, <3 x i16> %amount) {930; %result = ashr <3 x i16> %value, %amount931; ret <3 x i16> %result932; }933 934; define amdgpu_ps <3 x i16> @s_ashr_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) {935; %result = ashr <3 x i16> %value, %amount936; ret <3 x i16> %result937; }938 939define <2 x float> @v_ashr_v4i16(<4 x i16> %value, <4 x i16> %amount) {940; GFX6-LABEL: v_ashr_v4i16:941; GFX6: ; %bb.0:942; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)943; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4944; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16945; GFX6-NEXT: v_ashrrev_i32_e32 v0, v4, v0946; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5947; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16948; GFX6-NEXT: v_ashrrev_i32_e32 v1, v4, v1949; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6950; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16951; GFX6-NEXT: v_ashrrev_i32_e32 v2, v4, v2952; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7953; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16954; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1955; GFX6-NEXT: v_ashrrev_i32_e32 v3, v4, v3956; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0957; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1958; GFX6-NEXT: v_or_b32_e32 v0, v0, v1959; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2960; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3961; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2962; GFX6-NEXT: v_or_b32_e32 v1, v1, v2963; GFX6-NEXT: s_setpc_b64 s[30:31]964;965; GFX8-LABEL: v_ashr_v4i16:966; GFX8: ; %bb.0:967; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)968; GFX8-NEXT: v_ashrrev_i16_e32 v4, v2, v0969; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1970; GFX8-NEXT: v_ashrrev_i16_e32 v2, v3, v1971; GFX8-NEXT: v_ashrrev_i16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1972; GFX8-NEXT: v_or_b32_e32 v0, v4, v0973; GFX8-NEXT: v_or_b32_e32 v1, v2, v1974; GFX8-NEXT: s_setpc_b64 s[30:31]975;976; GFX9-LABEL: v_ashr_v4i16:977; GFX9: ; %bb.0:978; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)979; GFX9-NEXT: v_pk_ashrrev_i16 v0, v2, v0980; GFX9-NEXT: v_pk_ashrrev_i16 v1, v3, v1981; GFX9-NEXT: s_setpc_b64 s[30:31]982;983; GFX10PLUS-LABEL: v_ashr_v4i16:984; GFX10PLUS: ; %bb.0:985; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)986; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, v2, v0987; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v1, v3, v1988; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]989 %result = ashr <4 x i16> %value, %amount990 %cast = bitcast <4 x i16> %result to <2 x float>991 ret <2 x float> %cast992}993 994define amdgpu_ps <2 x i32> @s_ashr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) {995; GFX6-LABEL: s_ashr_v4i16:996; GFX6: ; %bb.0:997; GFX6-NEXT: s_sext_i32_i16 s1, s1998; GFX6-NEXT: s_sext_i32_i16 s0, s0999; GFX6-NEXT: s_ashr_i32 s1, s1, s51000; GFX6-NEXT: s_ashr_i32 s0, s0, s41001; GFX6-NEXT: s_sext_i32_i16 s2, s21002; GFX6-NEXT: s_sext_i32_i16 s3, s31003; GFX6-NEXT: s_and_b32 s1, s1, 0xffff1004; GFX6-NEXT: s_ashr_i32 s2, s2, s61005; GFX6-NEXT: s_ashr_i32 s3, s3, s71006; GFX6-NEXT: s_and_b32 s0, s0, 0xffff1007; GFX6-NEXT: s_lshl_b32 s1, s1, 161008; GFX6-NEXT: s_or_b32 s0, s0, s11009; GFX6-NEXT: s_and_b32 s1, s2, 0xffff1010; GFX6-NEXT: s_and_b32 s2, s3, 0xffff1011; GFX6-NEXT: s_lshl_b32 s2, s2, 161012; GFX6-NEXT: s_or_b32 s1, s1, s21013; GFX6-NEXT: ; return to shader part epilog1014;1015; GFX8-LABEL: s_ashr_v4i16:1016; GFX8: ; %bb.0:1017; GFX8-NEXT: s_lshr_b32 s4, s0, 161018; GFX8-NEXT: s_sext_i32_i16 s0, s01019; GFX8-NEXT: s_lshr_b32 s6, s2, 161020; GFX8-NEXT: s_ashr_i32 s0, s0, s21021; GFX8-NEXT: s_sext_i32_i16 s2, s41022; GFX8-NEXT: s_lshr_b32 s5, s1, 161023; GFX8-NEXT: s_ashr_i32 s2, s2, s61024; GFX8-NEXT: s_sext_i32_i16 s1, s11025; GFX8-NEXT: s_lshr_b32 s7, s3, 161026; GFX8-NEXT: s_ashr_i32 s1, s1, s31027; GFX8-NEXT: s_sext_i32_i16 s3, s51028; GFX8-NEXT: s_and_b32 s2, 0xffff, s21029; GFX8-NEXT: s_ashr_i32 s3, s3, s71030; GFX8-NEXT: s_and_b32 s0, 0xffff, s01031; GFX8-NEXT: s_lshl_b32 s2, s2, 161032; GFX8-NEXT: s_or_b32 s0, s0, s21033; GFX8-NEXT: s_and_b32 s2, 0xffff, s31034; GFX8-NEXT: s_and_b32 s1, 0xffff, s11035; GFX8-NEXT: s_lshl_b32 s2, s2, 161036; GFX8-NEXT: s_or_b32 s1, s1, s21037; GFX8-NEXT: ; return to shader part epilog1038;1039; GFX9-LABEL: s_ashr_v4i16:1040; GFX9: ; %bb.0:1041; GFX9-NEXT: s_sext_i32_i16 s4, s01042; GFX9-NEXT: s_ashr_i32 s0, s0, 161043; GFX9-NEXT: s_sext_i32_i16 s5, s21044; GFX9-NEXT: s_ashr_i32 s2, s2, 161045; GFX9-NEXT: s_ashr_i32 s4, s4, s51046; GFX9-NEXT: s_ashr_i32 s0, s0, s21047; GFX9-NEXT: s_pack_ll_b32_b16 s0, s4, s01048; GFX9-NEXT: s_sext_i32_i16 s2, s11049; GFX9-NEXT: s_ashr_i32 s1, s1, 161050; GFX9-NEXT: s_sext_i32_i16 s4, s31051; GFX9-NEXT: s_ashr_i32 s3, s3, 161052; GFX9-NEXT: s_ashr_i32 s2, s2, s41053; GFX9-NEXT: s_ashr_i32 s1, s1, s31054; GFX9-NEXT: s_pack_ll_b32_b16 s1, s2, s11055; GFX9-NEXT: ; return to shader part epilog1056;1057; GFX10PLUS-LABEL: s_ashr_v4i16:1058; GFX10PLUS: ; %bb.0:1059; GFX10PLUS-NEXT: s_sext_i32_i16 s4, s01060; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 161061; GFX10PLUS-NEXT: s_sext_i32_i16 s5, s21062; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, 161063; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, s51064; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s21065; GFX10PLUS-NEXT: s_sext_i32_i16 s2, s11066; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 161067; GFX10PLUS-NEXT: s_sext_i32_i16 s5, s31068; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, 161069; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s51070; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s31071; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s4, s01072; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s2, s11073; GFX10PLUS-NEXT: ; return to shader part epilog1074 %result = ashr <4 x i16> %value, %amount1075 %cast = bitcast <4 x i16> %result to <2 x i32>1076 ret <2 x i32> %cast1077}1078 1079; FIXME1080; define <5 x i16> @v_ashr_v5i16(<5 x i16> %value, <5 x i16> %amount) {1081; %result = ashr <5 x i16> %value, %amount1082; ret <5 x i16> %result1083; }1084 1085; define amdgpu_ps <5 x i16> @s_ashr_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) {1086; %result = ashr <5 x i16> %value, %amount1087; ret <5 x i16> %result1088; }1089 1090; define <3 x float> @v_ashr_v6i16(<6 x i16> %value, <6 x i16> %amount) {1091; %result = ashr <6 x i16> %value, %amount1092; %cast = bitcast <6 x i16> %result to <3 x float>1093; ret <3 x float> %cast1094; }1095 1096; define amdgpu_ps <3 x i32> @s_ashr_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) {1097; %result = ashr <6 x i16> %value, %amount1098; %cast = bitcast <6 x i16> %result to <3 x i32>1099; ret <3 x i32> %cast1100; }1101 1102define <4 x float> @v_ashr_v8i16(<8 x i16> %value, <8 x i16> %amount) {1103; GFX6-LABEL: v_ashr_v8i16:1104; GFX6: ; %bb.0:1105; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1106; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v81107; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 161108; GFX6-NEXT: v_ashrrev_i32_e32 v0, v8, v01109; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v91110; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 161111; GFX6-NEXT: v_ashrrev_i32_e32 v1, v8, v11112; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v101113; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 161114; GFX6-NEXT: v_ashrrev_i32_e32 v2, v8, v21115; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v111116; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 161117; GFX6-NEXT: v_ashrrev_i32_e32 v3, v8, v31118; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v121119; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 161120; GFX6-NEXT: v_ashrrev_i32_e32 v4, v8, v41121; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v131122; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 161123; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v11124; GFX6-NEXT: v_ashrrev_i32_e32 v5, v8, v51125; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v141126; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 161127; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v01128; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v11129; GFX6-NEXT: v_ashrrev_i32_e32 v6, v8, v61130; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v151131; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 161132; GFX6-NEXT: v_or_b32_e32 v0, v0, v11133; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v21134; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v31135; GFX6-NEXT: v_ashrrev_i32_e32 v7, v8, v71136; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v21137; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v51138; GFX6-NEXT: v_or_b32_e32 v1, v1, v21139; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v41140; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v31141; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v71142; GFX6-NEXT: v_or_b32_e32 v2, v2, v31143; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v61144; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v41145; GFX6-NEXT: v_or_b32_e32 v3, v3, v41146; GFX6-NEXT: s_setpc_b64 s[30:31]1147;1148; GFX8-LABEL: v_ashr_v8i16:1149; GFX8: ; %bb.0:1150; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1151; GFX8-NEXT: v_ashrrev_i16_e32 v8, v4, v01152; GFX8-NEXT: v_ashrrev_i16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11153; GFX8-NEXT: v_ashrrev_i16_e32 v4, v5, v11154; GFX8-NEXT: v_ashrrev_i16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11155; GFX8-NEXT: v_or_b32_e32 v1, v4, v11156; GFX8-NEXT: v_ashrrev_i16_e32 v4, v6, v21157; GFX8-NEXT: v_ashrrev_i16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11158; GFX8-NEXT: v_or_b32_e32 v2, v4, v21159; GFX8-NEXT: v_ashrrev_i16_e32 v4, v7, v31160; GFX8-NEXT: v_ashrrev_i16_sdwa v3, v7, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11161; GFX8-NEXT: v_or_b32_e32 v0, v8, v01162; GFX8-NEXT: v_or_b32_e32 v3, v4, v31163; GFX8-NEXT: s_setpc_b64 s[30:31]1164;1165; GFX9-LABEL: v_ashr_v8i16:1166; GFX9: ; %bb.0:1167; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1168; GFX9-NEXT: v_pk_ashrrev_i16 v0, v4, v01169; GFX9-NEXT: v_pk_ashrrev_i16 v1, v5, v11170; GFX9-NEXT: v_pk_ashrrev_i16 v2, v6, v21171; GFX9-NEXT: v_pk_ashrrev_i16 v3, v7, v31172; GFX9-NEXT: s_setpc_b64 s[30:31]1173;1174; GFX10PLUS-LABEL: v_ashr_v8i16:1175; GFX10PLUS: ; %bb.0:1176; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1177; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, v4, v01178; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v1, v5, v11179; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v2, v6, v21180; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v3, v7, v31181; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1182 %result = ashr <8 x i16> %value, %amount1183 %cast = bitcast <8 x i16> %result to <4 x float>1184 ret <4 x float> %cast1185}1186 1187define amdgpu_ps <4 x i32> @s_ashr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) {1188; GFX6-LABEL: s_ashr_v8i16:1189; GFX6: ; %bb.0:1190; GFX6-NEXT: s_sext_i32_i16 s1, s11191; GFX6-NEXT: s_sext_i32_i16 s0, s01192; GFX6-NEXT: s_ashr_i32 s1, s1, s91193; GFX6-NEXT: s_ashr_i32 s0, s0, s81194; GFX6-NEXT: s_sext_i32_i16 s2, s21195; GFX6-NEXT: s_sext_i32_i16 s3, s31196; GFX6-NEXT: s_and_b32 s1, s1, 0xffff1197; GFX6-NEXT: s_ashr_i32 s2, s2, s101198; GFX6-NEXT: s_ashr_i32 s3, s3, s111199; GFX6-NEXT: s_sext_i32_i16 s5, s51200; GFX6-NEXT: s_and_b32 s0, s0, 0xffff1201; GFX6-NEXT: s_lshl_b32 s1, s1, 161202; GFX6-NEXT: s_sext_i32_i16 s4, s41203; GFX6-NEXT: s_ashr_i32 s5, s5, s131204; GFX6-NEXT: s_sext_i32_i16 s7, s71205; GFX6-NEXT: s_or_b32 s0, s0, s11206; GFX6-NEXT: s_and_b32 s1, s2, 0xffff1207; GFX6-NEXT: s_and_b32 s2, s3, 0xffff1208; GFX6-NEXT: s_ashr_i32 s4, s4, s121209; GFX6-NEXT: s_sext_i32_i16 s6, s61210; GFX6-NEXT: s_ashr_i32 s7, s7, s151211; GFX6-NEXT: s_lshl_b32 s2, s2, 161212; GFX6-NEXT: s_and_b32 s3, s5, 0xffff1213; GFX6-NEXT: s_ashr_i32 s6, s6, s141214; GFX6-NEXT: s_or_b32 s1, s1, s21215; GFX6-NEXT: s_and_b32 s2, s4, 0xffff1216; GFX6-NEXT: s_lshl_b32 s3, s3, 161217; GFX6-NEXT: s_and_b32 s4, s7, 0xffff1218; GFX6-NEXT: s_or_b32 s2, s2, s31219; GFX6-NEXT: s_and_b32 s3, s6, 0xffff1220; GFX6-NEXT: s_lshl_b32 s4, s4, 161221; GFX6-NEXT: s_or_b32 s3, s3, s41222; GFX6-NEXT: ; return to shader part epilog1223;1224; GFX8-LABEL: s_ashr_v8i16:1225; GFX8: ; %bb.0:1226; GFX8-NEXT: s_lshr_b32 s8, s0, 161227; GFX8-NEXT: s_sext_i32_i16 s0, s01228; GFX8-NEXT: s_lshr_b32 s12, s4, 161229; GFX8-NEXT: s_ashr_i32 s0, s0, s41230; GFX8-NEXT: s_sext_i32_i16 s4, s81231; GFX8-NEXT: s_lshr_b32 s9, s1, 161232; GFX8-NEXT: s_ashr_i32 s4, s4, s121233; GFX8-NEXT: s_sext_i32_i16 s1, s11234; GFX8-NEXT: s_lshr_b32 s13, s5, 161235; GFX8-NEXT: s_ashr_i32 s1, s1, s51236; GFX8-NEXT: s_sext_i32_i16 s5, s91237; GFX8-NEXT: s_and_b32 s4, 0xffff, s41238; GFX8-NEXT: s_lshr_b32 s10, s2, 161239; GFX8-NEXT: s_ashr_i32 s5, s5, s131240; GFX8-NEXT: s_sext_i32_i16 s2, s21241; GFX8-NEXT: s_and_b32 s0, 0xffff, s01242; GFX8-NEXT: s_lshl_b32 s4, s4, 161243; GFX8-NEXT: s_lshr_b32 s14, s6, 161244; GFX8-NEXT: s_ashr_i32 s2, s2, s61245; GFX8-NEXT: s_sext_i32_i16 s6, s101246; GFX8-NEXT: s_or_b32 s0, s0, s41247; GFX8-NEXT: s_and_b32 s4, 0xffff, s51248; GFX8-NEXT: s_lshr_b32 s11, s3, 161249; GFX8-NEXT: s_ashr_i32 s6, s6, s141250; GFX8-NEXT: s_sext_i32_i16 s3, s31251; GFX8-NEXT: s_and_b32 s1, 0xffff, s11252; GFX8-NEXT: s_lshl_b32 s4, s4, 161253; GFX8-NEXT: s_lshr_b32 s15, s7, 161254; GFX8-NEXT: s_ashr_i32 s3, s3, s71255; GFX8-NEXT: s_sext_i32_i16 s7, s111256; GFX8-NEXT: s_or_b32 s1, s1, s41257; GFX8-NEXT: s_and_b32 s4, 0xffff, s61258; GFX8-NEXT: s_ashr_i32 s7, s7, s151259; GFX8-NEXT: s_and_b32 s2, 0xffff, s21260; GFX8-NEXT: s_lshl_b32 s4, s4, 161261; GFX8-NEXT: s_or_b32 s2, s2, s41262; GFX8-NEXT: s_and_b32 s4, 0xffff, s71263; GFX8-NEXT: s_and_b32 s3, 0xffff, s31264; GFX8-NEXT: s_lshl_b32 s4, s4, 161265; GFX8-NEXT: s_or_b32 s3, s3, s41266; GFX8-NEXT: ; return to shader part epilog1267;1268; GFX9-LABEL: s_ashr_v8i16:1269; GFX9: ; %bb.0:1270; GFX9-NEXT: s_sext_i32_i16 s8, s01271; GFX9-NEXT: s_ashr_i32 s0, s0, 161272; GFX9-NEXT: s_sext_i32_i16 s9, s41273; GFX9-NEXT: s_ashr_i32 s4, s4, 161274; GFX9-NEXT: s_ashr_i32 s8, s8, s91275; GFX9-NEXT: s_ashr_i32 s0, s0, s41276; GFX9-NEXT: s_pack_ll_b32_b16 s0, s8, s01277; GFX9-NEXT: s_sext_i32_i16 s4, s11278; GFX9-NEXT: s_ashr_i32 s1, s1, 161279; GFX9-NEXT: s_sext_i32_i16 s8, s51280; GFX9-NEXT: s_ashr_i32 s5, s5, 161281; GFX9-NEXT: s_ashr_i32 s4, s4, s81282; GFX9-NEXT: s_ashr_i32 s1, s1, s51283; GFX9-NEXT: s_pack_ll_b32_b16 s1, s4, s11284; GFX9-NEXT: s_sext_i32_i16 s4, s21285; GFX9-NEXT: s_ashr_i32 s2, s2, 161286; GFX9-NEXT: s_sext_i32_i16 s5, s61287; GFX9-NEXT: s_ashr_i32 s6, s6, 161288; GFX9-NEXT: s_ashr_i32 s4, s4, s51289; GFX9-NEXT: s_ashr_i32 s2, s2, s61290; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s21291; GFX9-NEXT: s_sext_i32_i16 s4, s31292; GFX9-NEXT: s_ashr_i32 s3, s3, 161293; GFX9-NEXT: s_sext_i32_i16 s5, s71294; GFX9-NEXT: s_ashr_i32 s6, s7, 161295; GFX9-NEXT: s_ashr_i32 s4, s4, s51296; GFX9-NEXT: s_ashr_i32 s3, s3, s61297; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s31298; GFX9-NEXT: ; return to shader part epilog1299;1300; GFX10PLUS-LABEL: s_ashr_v8i16:1301; GFX10PLUS: ; %bb.0:1302; GFX10PLUS-NEXT: s_sext_i32_i16 s8, s01303; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 161304; GFX10PLUS-NEXT: s_sext_i32_i16 s9, s41305; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, 161306; GFX10PLUS-NEXT: s_ashr_i32 s8, s8, s91307; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s41308; GFX10PLUS-NEXT: s_sext_i32_i16 s4, s11309; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 161310; GFX10PLUS-NEXT: s_sext_i32_i16 s9, s51311; GFX10PLUS-NEXT: s_ashr_i32 s5, s5, 161312; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, s91313; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s51314; GFX10PLUS-NEXT: s_sext_i32_i16 s5, s61315; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s4, s11316; GFX10PLUS-NEXT: s_sext_i32_i16 s4, s21317; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, 161318; GFX10PLUS-NEXT: s_ashr_i32 s6, s6, 161319; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, s51320; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s61321; GFX10PLUS-NEXT: s_sext_i32_i16 s5, s31322; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, 161323; GFX10PLUS-NEXT: s_sext_i32_i16 s6, s71324; GFX10PLUS-NEXT: s_ashr_i32 s7, s7, 161325; GFX10PLUS-NEXT: s_ashr_i32 s5, s5, s61326; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s71327; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s8, s01328; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s2, s4, s21329; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s3, s5, s31330; GFX10PLUS-NEXT: ; return to shader part epilog1331 %result = ashr <8 x i16> %value, %amount1332 %cast = bitcast <8 x i16> %result to <4 x i32>1333 ret <4 x i32> %cast1334}1335 1336define i64 @v_ashr_i64(i64 %value, i64 %amount) {1337; GFX6-LABEL: v_ashr_i64:1338; GFX6: ; %bb.0:1339; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1340; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], v21341; GFX6-NEXT: s_setpc_b64 s[30:31]1342;1343; GFX8-LABEL: v_ashr_i64:1344; GFX8: ; %bb.0:1345; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1346; GFX8-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]1347; GFX8-NEXT: s_setpc_b64 s[30:31]1348;1349; GFX9-LABEL: v_ashr_i64:1350; GFX9: ; %bb.0:1351; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1352; GFX9-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]1353; GFX9-NEXT: s_setpc_b64 s[30:31]1354;1355; GFX10PLUS-LABEL: v_ashr_i64:1356; GFX10PLUS: ; %bb.0:1357; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1358; GFX10PLUS-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]1359; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1360 %result = ashr i64 %value, %amount1361 ret i64 %result1362}1363 1364define i64 @v_ashr_i64_63(i64 %value) {1365; GCN-LABEL: v_ashr_i64_63:1366; GCN: ; %bb.0:1367; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1368; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v11369; GCN-NEXT: v_mov_b32_e32 v1, v01370; GCN-NEXT: s_setpc_b64 s[30:31]1371;1372; GFX10PLUS-LABEL: v_ashr_i64_63:1373; GFX10PLUS: ; %bb.0:1374; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1375; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 31, v11376; GFX10PLUS-NEXT: v_mov_b32_e32 v1, v01377; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1378 %result = ashr i64 %value, 631379 ret i64 %result1380}1381 1382define i64 @v_ashr_i64_33(i64 %value) {1383; GCN-LABEL: v_ashr_i64_33:1384; GCN: ; %bb.0:1385; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1386; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v11387; GCN-NEXT: v_ashrrev_i32_e32 v0, 1, v11388; GCN-NEXT: v_mov_b32_e32 v1, v21389; GCN-NEXT: s_setpc_b64 s[30:31]1390;1391; GFX10PLUS-LABEL: v_ashr_i64_33:1392; GFX10PLUS: ; %bb.0:1393; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1394; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 1, v11395; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v11396; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1397 %result = ashr i64 %value, 331398 ret i64 %result1399}1400 1401define i64 @v_ashr_i64_32(i64 %value) {1402; GCN-LABEL: v_ashr_i64_32:1403; GCN: ; %bb.0:1404; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1405; GCN-NEXT: v_mov_b32_e32 v0, v11406; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v01407; GCN-NEXT: s_setpc_b64 s[30:31]1408;1409; GFX10PLUS-LABEL: v_ashr_i64_32:1410; GFX10PLUS: ; %bb.0:1411; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1412; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v11413; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v01414; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1415 %result = ashr i64 %value, 321416 ret i64 %result1417}1418 1419define i64 @v_ashr_i64_31(i64 %value) {1420; GFX6-LABEL: v_ashr_i64_31:1421; GFX6: ; %bb.0:1422; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1423; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], 311424; GFX6-NEXT: s_setpc_b64 s[30:31]1425;1426; GFX8-LABEL: v_ashr_i64_31:1427; GFX8: ; %bb.0:1428; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1429; GFX8-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1]1430; GFX8-NEXT: s_setpc_b64 s[30:31]1431;1432; GFX9-LABEL: v_ashr_i64_31:1433; GFX9: ; %bb.0:1434; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1435; GFX9-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1]1436; GFX9-NEXT: s_setpc_b64 s[30:31]1437;1438; GFX10PLUS-LABEL: v_ashr_i64_31:1439; GFX10PLUS: ; %bb.0:1440; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1441; GFX10PLUS-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1]1442; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1443 %result = ashr i64 %value, 311444 ret i64 %result1445}1446 1447define amdgpu_ps i64 @s_ashr_i64(i64 inreg %value, i64 inreg %amount) {1448; GCN-LABEL: s_ashr_i64:1449; GCN: ; %bb.0:1450; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], s21451; GCN-NEXT: ; return to shader part epilog1452;1453; GFX10PLUS-LABEL: s_ashr_i64:1454; GFX10PLUS: ; %bb.0:1455; GFX10PLUS-NEXT: s_ashr_i64 s[0:1], s[0:1], s21456; GFX10PLUS-NEXT: ; return to shader part epilog1457 %result = ashr i64 %value, %amount1458 ret i64 %result1459}1460 1461define amdgpu_ps i64 @s_ashr_i64_63(i64 inreg %value) {1462; GCN-LABEL: s_ashr_i64_63:1463; GCN: ; %bb.0:1464; GCN-NEXT: s_ashr_i32 s0, s1, 311465; GCN-NEXT: s_mov_b32 s1, s01466; GCN-NEXT: ; return to shader part epilog1467;1468; GFX10PLUS-LABEL: s_ashr_i64_63:1469; GFX10PLUS: ; %bb.0:1470; GFX10PLUS-NEXT: s_ashr_i32 s0, s1, 311471; GFX10PLUS-NEXT: s_mov_b32 s1, s01472; GFX10PLUS-NEXT: ; return to shader part epilog1473 %result = ashr i64 %value, 631474 ret i64 %result1475}1476 1477define amdgpu_ps i64 @s_ashr_i64_33(i64 inreg %value) {1478; GCN-LABEL: s_ashr_i64_33:1479; GCN: ; %bb.0:1480; GCN-NEXT: s_ashr_i32 s2, s1, 311481; GCN-NEXT: s_ashr_i32 s0, s1, 11482; GCN-NEXT: s_mov_b32 s1, s21483; GCN-NEXT: ; return to shader part epilog1484;1485; GFX10PLUS-LABEL: s_ashr_i64_33:1486; GFX10PLUS: ; %bb.0:1487; GFX10PLUS-NEXT: s_ashr_i32 s0, s1, 11488; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 311489; GFX10PLUS-NEXT: ; return to shader part epilog1490 %result = ashr i64 %value, 331491 ret i64 %result1492}1493 1494define amdgpu_ps i64 @s_ashr_i64_32(i64 inreg %value) {1495; GCN-LABEL: s_ashr_i64_32:1496; GCN: ; %bb.0:1497; GCN-NEXT: s_mov_b32 s0, s11498; GCN-NEXT: s_ashr_i32 s1, s1, 311499; GCN-NEXT: ; return to shader part epilog1500;1501; GFX10PLUS-LABEL: s_ashr_i64_32:1502; GFX10PLUS: ; %bb.0:1503; GFX10PLUS-NEXT: s_mov_b32 s0, s11504; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 311505; GFX10PLUS-NEXT: ; return to shader part epilog1506 %result = ashr i64 %value, 321507 ret i64 %result1508}1509 1510define amdgpu_ps i64 @s_ashr_i64_31(i64 inreg %value) {1511; GCN-LABEL: s_ashr_i64_31:1512; GCN: ; %bb.0:1513; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 311514; GCN-NEXT: ; return to shader part epilog1515;1516; GFX10PLUS-LABEL: s_ashr_i64_31:1517; GFX10PLUS: ; %bb.0:1518; GFX10PLUS-NEXT: s_ashr_i64 s[0:1], s[0:1], 311519; GFX10PLUS-NEXT: ; return to shader part epilog1520 %result = ashr i64 %value, 311521 ret i64 %result1522}1523 1524define amdgpu_ps <2 x float> @ashr_i64_sv(i64 inreg %value, i64 %amount) {1525; GFX6-LABEL: ashr_i64_sv:1526; GFX6: ; %bb.0:1527; GFX6-NEXT: v_ashr_i64 v[0:1], s[0:1], v01528; GFX6-NEXT: ; return to shader part epilog1529;1530; GFX8-LABEL: ashr_i64_sv:1531; GFX8: ; %bb.0:1532; GFX8-NEXT: v_ashrrev_i64 v[0:1], v0, s[0:1]1533; GFX8-NEXT: ; return to shader part epilog1534;1535; GFX9-LABEL: ashr_i64_sv:1536; GFX9: ; %bb.0:1537; GFX9-NEXT: v_ashrrev_i64 v[0:1], v0, s[0:1]1538; GFX9-NEXT: ; return to shader part epilog1539;1540; GFX10PLUS-LABEL: ashr_i64_sv:1541; GFX10PLUS: ; %bb.0:1542; GFX10PLUS-NEXT: v_ashrrev_i64 v[0:1], v0, s[0:1]1543; GFX10PLUS-NEXT: ; return to shader part epilog1544 %result = ashr i64 %value, %amount1545 %cast = bitcast i64 %result to <2 x float>1546 ret <2 x float> %cast1547}1548 1549define amdgpu_ps <2 x float> @ashr_i64_vs(i64 %value, i64 inreg %amount) {1550; GFX6-LABEL: ashr_i64_vs:1551; GFX6: ; %bb.0:1552; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], s01553; GFX6-NEXT: ; return to shader part epilog1554;1555; GFX8-LABEL: ashr_i64_vs:1556; GFX8: ; %bb.0:1557; GFX8-NEXT: v_ashrrev_i64 v[0:1], s0, v[0:1]1558; GFX8-NEXT: ; return to shader part epilog1559;1560; GFX9-LABEL: ashr_i64_vs:1561; GFX9: ; %bb.0:1562; GFX9-NEXT: v_ashrrev_i64 v[0:1], s0, v[0:1]1563; GFX9-NEXT: ; return to shader part epilog1564;1565; GFX10PLUS-LABEL: ashr_i64_vs:1566; GFX10PLUS: ; %bb.0:1567; GFX10PLUS-NEXT: v_ashrrev_i64 v[0:1], s0, v[0:1]1568; GFX10PLUS-NEXT: ; return to shader part epilog1569 %result = ashr i64 %value, %amount1570 %cast = bitcast i64 %result to <2 x float>1571 ret <2 x float> %cast1572}1573 1574define <2 x i64> @v_ashr_v2i64(<2 x i64> %value, <2 x i64> %amount) {1575; GFX6-LABEL: v_ashr_v2i64:1576; GFX6: ; %bb.0:1577; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1578; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], v41579; GFX6-NEXT: v_ashr_i64 v[2:3], v[2:3], v61580; GFX6-NEXT: s_setpc_b64 s[30:31]1581;1582; GFX8-LABEL: v_ashr_v2i64:1583; GFX8: ; %bb.0:1584; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1585; GFX8-NEXT: v_ashrrev_i64 v[0:1], v4, v[0:1]1586; GFX8-NEXT: v_ashrrev_i64 v[2:3], v6, v[2:3]1587; GFX8-NEXT: s_setpc_b64 s[30:31]1588;1589; GFX9-LABEL: v_ashr_v2i64:1590; GFX9: ; %bb.0:1591; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1592; GFX9-NEXT: v_ashrrev_i64 v[0:1], v4, v[0:1]1593; GFX9-NEXT: v_ashrrev_i64 v[2:3], v6, v[2:3]1594; GFX9-NEXT: s_setpc_b64 s[30:31]1595;1596; GFX10PLUS-LABEL: v_ashr_v2i64:1597; GFX10PLUS: ; %bb.0:1598; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1599; GFX10PLUS-NEXT: v_ashrrev_i64 v[0:1], v4, v[0:1]1600; GFX10PLUS-NEXT: v_ashrrev_i64 v[2:3], v6, v[2:3]1601; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1602 %result = ashr <2 x i64> %value, %amount1603 ret <2 x i64> %result1604}1605 1606define <2 x i64> @v_ashr_v2i64_31(<2 x i64> %value) {1607; GFX6-LABEL: v_ashr_v2i64_31:1608; GFX6: ; %bb.0:1609; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1610; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], 311611; GFX6-NEXT: v_ashr_i64 v[2:3], v[2:3], 311612; GFX6-NEXT: s_setpc_b64 s[30:31]1613;1614; GFX8-LABEL: v_ashr_v2i64_31:1615; GFX8: ; %bb.0:1616; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1617; GFX8-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1]1618; GFX8-NEXT: v_ashrrev_i64 v[2:3], 31, v[2:3]1619; GFX8-NEXT: s_setpc_b64 s[30:31]1620;1621; GFX9-LABEL: v_ashr_v2i64_31:1622; GFX9: ; %bb.0:1623; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1624; GFX9-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1]1625; GFX9-NEXT: v_ashrrev_i64 v[2:3], 31, v[2:3]1626; GFX9-NEXT: s_setpc_b64 s[30:31]1627;1628; GFX10PLUS-LABEL: v_ashr_v2i64_31:1629; GFX10PLUS: ; %bb.0:1630; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1631; GFX10PLUS-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1]1632; GFX10PLUS-NEXT: v_ashrrev_i64 v[2:3], 31, v[2:3]1633; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1634 %result = ashr <2 x i64> %value, <i64 31, i64 31>1635 ret <2 x i64> %result1636}1637 1638define amdgpu_ps <2 x i64> @s_ashr_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) {1639; GCN-LABEL: s_ashr_v2i64:1640; GCN: ; %bb.0:1641; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], s41642; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], s61643; GCN-NEXT: ; return to shader part epilog1644;1645; GFX10PLUS-LABEL: s_ashr_v2i64:1646; GFX10PLUS: ; %bb.0:1647; GFX10PLUS-NEXT: s_ashr_i64 s[0:1], s[0:1], s41648; GFX10PLUS-NEXT: s_ashr_i64 s[2:3], s[2:3], s61649; GFX10PLUS-NEXT: ; return to shader part epilog1650 %result = ashr <2 x i64> %value, %amount1651 ret <2 x i64> %result1652}1653 1654define i65 @v_ashr_i65(i65 %value, i65 %amount) {1655; GFX6-LABEL: v_ashr_i65:1656; GFX6: ; %bb.0:1657; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1658; GFX6-NEXT: v_bfe_i32 v4, v2, 0, 11659; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v41660; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v31661; GFX6-NEXT: v_lshr_b64 v[6:7], v[0:1], v31662; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], v81663; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xffffffc0, v31664; GFX6-NEXT: v_ashr_i64 v[10:11], v[4:5], v31665; GFX6-NEXT: v_or_b32_e32 v6, v6, v81666; GFX6-NEXT: v_ashrrev_i32_e32 v8, 31, v51667; GFX6-NEXT: v_ashr_i64 v[4:5], v[4:5], v21668; GFX6-NEXT: v_or_b32_e32 v7, v7, v91669; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v31670; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc1671; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc1672; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v31673; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]1674; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]1675; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc1676; GFX6-NEXT: s_setpc_b64 s[30:31]1677;1678; GFX8-LABEL: v_ashr_i65:1679; GFX8: ; %bb.0:1680; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1681; GFX8-NEXT: v_bfe_i32 v4, v2, 0, 11682; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v41683; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v31684; GFX8-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]1685; GFX8-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5]1686; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0xffffffc0, v31687; GFX8-NEXT: v_ashrrev_i64 v[10:11], v3, v[4:5]1688; GFX8-NEXT: v_or_b32_e32 v6, v6, v81689; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v51690; GFX8-NEXT: v_ashrrev_i64 v[4:5], v2, v[4:5]1691; GFX8-NEXT: v_or_b32_e32 v7, v7, v91692; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v31693; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc1694; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc1695; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v31696; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]1697; GFX8-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]1698; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc1699; GFX8-NEXT: s_setpc_b64 s[30:31]1700;1701; GFX9-LABEL: v_ashr_i65:1702; GFX9: ; %bb.0:1703; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1704; GFX9-NEXT: v_bfe_i32 v4, v2, 0, 11705; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v41706; GFX9-NEXT: v_sub_u32_e32 v8, 64, v31707; GFX9-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]1708; GFX9-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5]1709; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffc0, v31710; GFX9-NEXT: v_ashrrev_i64 v[10:11], v3, v[4:5]1711; GFX9-NEXT: v_or_b32_e32 v6, v6, v81712; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v51713; GFX9-NEXT: v_ashrrev_i64 v[4:5], v2, v[4:5]1714; GFX9-NEXT: v_or_b32_e32 v7, v7, v91715; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v31716; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc1717; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc1718; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v31719; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]1720; GFX9-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]1721; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc1722; GFX9-NEXT: s_setpc_b64 s[30:31]1723;1724; GFX10-LABEL: v_ashr_i65:1725; GFX10: ; %bb.0:1726; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1727; GFX10-NEXT: v_bfe_i32 v4, v2, 0, 11728; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v31729; GFX10-NEXT: v_add_nc_u32_e32 v10, 0xffffffc0, v31730; GFX10-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]1731; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v31732; GFX10-NEXT: v_ashrrev_i32_e32 v5, 31, v41733; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v31734; GFX10-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5]1735; GFX10-NEXT: v_ashrrev_i64 v[10:11], v10, v[4:5]1736; GFX10-NEXT: v_or_b32_e32 v2, v6, v81737; GFX10-NEXT: v_or_b32_e32 v8, v7, v91738; GFX10-NEXT: v_ashrrev_i64 v[6:7], v3, v[4:5]1739; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v51740; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo1741; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v8, vcc_lo1742; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v0, s41743; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, v1, s41744; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo1745; GFX10-NEXT: s_setpc_b64 s[30:31]1746;1747; GFX11-LABEL: v_ashr_i65:1748; GFX11: ; %bb.0:1749; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1750; GFX11-NEXT: v_bfe_i32 v4, v2, 0, 11751; GFX11-NEXT: v_sub_nc_u32_e32 v2, 64, v31752; GFX11-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]1753; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v31754; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 0, v31755; GFX11-NEXT: v_ashrrev_i32_e32 v5, 31, v41756; GFX11-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5]1757; GFX11-NEXT: v_or_b32_e32 v2, v6, v81758; GFX11-NEXT: v_or_b32_e32 v8, v7, v91759; GFX11-NEXT: v_add_nc_u32_e32 v10, 0xffffffc0, v31760; GFX11-NEXT: v_ashrrev_i64 v[6:7], v3, v[4:5]1761; GFX11-NEXT: v_ashrrev_i64 v[10:11], v10, v[4:5]1762; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v51763; GFX11-NEXT: v_dual_cndmask_b32 v2, v10, v2 :: v_dual_cndmask_b32 v3, v11, v81764; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, v0, s01765; GFX11-NEXT: v_cndmask_b32_e64 v1, v3, v1, s01766; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo1767; GFX11-NEXT: s_setpc_b64 s[30:31]1768 %result = ashr i65 %value, %amount1769 ret i65 %result1770}1771 1772define i65 @v_ashr_i65_33(i65 %value) {1773; GFX6-LABEL: v_ashr_i65_33:1774; GFX6: ; %bb.0:1775; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1776; GFX6-NEXT: v_mov_b32_e32 v3, v11777; GFX6-NEXT: v_bfe_i32 v1, v2, 0, 11778; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v11779; GFX6-NEXT: v_lshl_b64 v[0:1], v[1:2], 311780; GFX6-NEXT: v_lshrrev_b32_e32 v3, 1, v31781; GFX6-NEXT: v_or_b32_e32 v0, v0, v31782; GFX6-NEXT: v_ashrrev_i32_e32 v2, 1, v21783; GFX6-NEXT: s_setpc_b64 s[30:31]1784;1785; GFX8-LABEL: v_ashr_i65_33:1786; GFX8: ; %bb.0:1787; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1788; GFX8-NEXT: v_mov_b32_e32 v3, v11789; GFX8-NEXT: v_bfe_i32 v1, v2, 0, 11790; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v11791; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]1792; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v31793; GFX8-NEXT: v_or_b32_e32 v0, v0, v31794; GFX8-NEXT: v_ashrrev_i32_e32 v2, 1, v21795; GFX8-NEXT: s_setpc_b64 s[30:31]1796;1797; GFX9-LABEL: v_ashr_i65_33:1798; GFX9: ; %bb.0:1799; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1800; GFX9-NEXT: v_mov_b32_e32 v3, v11801; GFX9-NEXT: v_bfe_i32 v1, v2, 0, 11802; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v11803; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]1804; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v31805; GFX9-NEXT: v_or_b32_e32 v0, v0, v31806; GFX9-NEXT: v_ashrrev_i32_e32 v2, 1, v21807; GFX9-NEXT: s_setpc_b64 s[30:31]1808;1809; GFX10PLUS-LABEL: v_ashr_i65_33:1810; GFX10PLUS: ; %bb.0:1811; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1812; GFX10PLUS-NEXT: v_mov_b32_e32 v3, v11813; GFX10PLUS-NEXT: v_bfe_i32 v1, v2, 0, 11814; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, 1, v31815; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 31, v11816; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]1817; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 1, v21818; GFX10PLUS-NEXT: v_or_b32_e32 v0, v0, v31819; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1820 %result = ashr i65 %value, 331821 ret i65 %result1822}1823 1824define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) {1825; GCN-LABEL: s_ashr_i65:1826; GCN: ; %bb.0:1827; GCN-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x100001828; GCN-NEXT: s_sub_i32 s10, s3, 641829; GCN-NEXT: s_sub_i32 s8, 64, s31830; GCN-NEXT: s_cmp_lt_u32 s3, 641831; GCN-NEXT: s_cselect_b32 s11, 1, 01832; GCN-NEXT: s_cmp_eq_u32 s3, 01833; GCN-NEXT: s_cselect_b32 s12, 1, 01834; GCN-NEXT: s_ashr_i64 s[6:7], s[4:5], s31835; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], s31836; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], s81837; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]1838; GCN-NEXT: s_ashr_i32 s7, s5, 311839; GCN-NEXT: s_ashr_i64 s[4:5], s[4:5], s101840; GCN-NEXT: s_cmp_lg_u32 s11, 01841; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]1842; GCN-NEXT: s_cmp_lg_u32 s12, 01843; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]1844; GCN-NEXT: s_cmp_lg_u32 s11, 01845; GCN-NEXT: s_cselect_b32 s2, s6, s71846; GCN-NEXT: ; return to shader part epilog1847;1848; GFX10PLUS-LABEL: s_ashr_i65:1849; GFX10PLUS: ; %bb.0:1850; GFX10PLUS-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x100001851; GFX10PLUS-NEXT: s_sub_i32 s10, s3, 641852; GFX10PLUS-NEXT: s_sub_i32 s2, 64, s31853; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 641854; GFX10PLUS-NEXT: s_cselect_b32 s11, 1, 01855; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 01856; GFX10PLUS-NEXT: s_cselect_b32 s12, 1, 01857; GFX10PLUS-NEXT: s_lshr_b64 s[6:7], s[0:1], s31858; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[4:5], s21859; GFX10PLUS-NEXT: s_ashr_i64 s[2:3], s[4:5], s31860; GFX10PLUS-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]1861; GFX10PLUS-NEXT: s_ashr_i32 s3, s5, 311862; GFX10PLUS-NEXT: s_ashr_i64 s[4:5], s[4:5], s101863; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 01864; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]1865; GFX10PLUS-NEXT: s_cmp_lg_u32 s12, 01866; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]1867; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 01868; GFX10PLUS-NEXT: s_cselect_b32 s2, s2, s31869; GFX10PLUS-NEXT: ; return to shader part epilog1870 %result = ashr i65 %value, %amount1871 ret i65 %result1872}1873 1874define amdgpu_ps i65 @s_ashr_i65_33(i65 inreg %value) {1875; GCN-LABEL: s_ashr_i65_33:1876; GCN: ; %bb.0:1877; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100001878; GCN-NEXT: s_lshr_b32 s4, s1, 11879; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 311880; GCN-NEXT: s_or_b32 s0, s0, s41881; GCN-NEXT: s_ashr_i32 s2, s3, 11882; GCN-NEXT: ; return to shader part epilog1883;1884; GFX10PLUS-LABEL: s_ashr_i65_33:1885; GFX10PLUS: ; %bb.0:1886; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100001887; GFX10PLUS-NEXT: s_lshr_b32 s4, s1, 11888; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[2:3], 311889; GFX10PLUS-NEXT: s_ashr_i32 s2, s3, 11890; GFX10PLUS-NEXT: s_or_b32 s0, s0, s41891; GFX10PLUS-NEXT: ; return to shader part epilog1892 %result = ashr i65 %value, 331893 ret i65 %result1894}1895 1896define <4 x i2> @v_ashr_v4i2(<4 x i2> %value, <4 x i2> %amount) {1897; GFX6-LABEL: v_ashr_v4i2:1898; GFX6: ; %bb.0:1899; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1900; GFX6-NEXT: v_and_b32_e32 v4, 3, v41901; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 21902; GFX6-NEXT: v_ashrrev_i32_e32 v0, v4, v01903; GFX6-NEXT: v_and_b32_e32 v4, 3, v51904; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 21905; GFX6-NEXT: v_ashrrev_i32_e32 v1, v4, v11906; GFX6-NEXT: v_and_b32_e32 v4, 3, v61907; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 21908; GFX6-NEXT: v_ashrrev_i32_e32 v2, v4, v21909; GFX6-NEXT: v_and_b32_e32 v4, 3, v71910; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 21911; GFX6-NEXT: v_ashrrev_i32_e32 v3, v4, v31912; GFX6-NEXT: s_setpc_b64 s[30:31]1913;1914; GFX8-LABEL: v_ashr_v4i2:1915; GFX8: ; %bb.0:1916; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1917; GFX8-NEXT: v_and_b32_e32 v4, 3, v41918; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 21919; GFX8-NEXT: v_ashrrev_i16_e32 v0, v4, v01920; GFX8-NEXT: v_and_b32_e32 v4, 3, v51921; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 21922; GFX8-NEXT: v_ashrrev_i16_e32 v1, v4, v11923; GFX8-NEXT: v_and_b32_e32 v4, 3, v61924; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 21925; GFX8-NEXT: v_ashrrev_i16_e32 v2, v4, v21926; GFX8-NEXT: v_and_b32_e32 v4, 3, v71927; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 21928; GFX8-NEXT: v_ashrrev_i16_e32 v3, v4, v31929; GFX8-NEXT: s_setpc_b64 s[30:31]1930;1931; GFX9-LABEL: v_ashr_v4i2:1932; GFX9: ; %bb.0:1933; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1934; GFX9-NEXT: v_and_b32_e32 v4, 3, v41935; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 21936; GFX9-NEXT: v_ashrrev_i16_e32 v0, v4, v01937; GFX9-NEXT: v_and_b32_e32 v4, 3, v51938; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 21939; GFX9-NEXT: v_ashrrev_i16_e32 v1, v4, v11940; GFX9-NEXT: v_and_b32_e32 v4, 3, v61941; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 21942; GFX9-NEXT: v_ashrrev_i16_e32 v2, v4, v21943; GFX9-NEXT: v_and_b32_e32 v4, 3, v71944; GFX9-NEXT: v_bfe_i32 v3, v3, 0, 21945; GFX9-NEXT: v_ashrrev_i16_e32 v3, v4, v31946; GFX9-NEXT: s_setpc_b64 s[30:31]1947;1948; GFX10PLUS-LABEL: v_ashr_v4i2:1949; GFX10PLUS: ; %bb.0:1950; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1951; GFX10PLUS-NEXT: v_and_b32_e32 v4, 3, v41952; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 21953; GFX10PLUS-NEXT: v_and_b32_e32 v5, 3, v51954; GFX10PLUS-NEXT: v_bfe_i32 v1, v1, 0, 21955; GFX10PLUS-NEXT: v_and_b32_e32 v6, 3, v61956; GFX10PLUS-NEXT: v_bfe_i32 v2, v2, 0, 21957; GFX10PLUS-NEXT: v_and_b32_e32 v7, 3, v71958; GFX10PLUS-NEXT: v_bfe_i32 v3, v3, 0, 21959; GFX10PLUS-NEXT: v_ashrrev_i16 v0, v4, v01960; GFX10PLUS-NEXT: v_ashrrev_i16 v1, v5, v11961; GFX10PLUS-NEXT: v_ashrrev_i16 v2, v6, v21962; GFX10PLUS-NEXT: v_ashrrev_i16 v3, v7, v31963; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1964 %result = ashr <4 x i2> %value, %amount1965 ret <4 x i2> %result1966}1967 1968; arithmetic shifts of an i1 are identity operations1969define amdgpu_ps <4 x i1> @s_ashr_v4i1(<4 x i1> inreg %value, <4 x i1> inreg %amount) {1970; GCN-LABEL: s_ashr_v4i1:1971; GCN: ; %bb.0:1972; GCN-NEXT: ; return to shader part epilog1973;1974; GFX10PLUS-LABEL: s_ashr_v4i1:1975; GFX10PLUS: ; %bb.0:1976; GFX10PLUS-NEXT: ; return to shader part epilog1977 %result = ashr <4 x i1> %value, %amount1978 ret <4 x i1> %result1979}1980 1981define <4 x i1> @v_ashr_v4i1(<4 x i1> %value, <4 x i1> %amount) {1982; GCN-LABEL: v_ashr_v4i1:1983; GCN: ; %bb.0:1984; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1985; GCN-NEXT: s_setpc_b64 s[30:31]1986;1987; GFX10PLUS-LABEL: v_ashr_v4i1:1988; GFX10PLUS: ; %bb.0:1989; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1990; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1991 %result = ashr <4 x i1> %value, %amount1992 ret <4 x i1> %result1993}1994 1995define amdgpu_ps <4 x i2> @s_ashr_v4i2(<4 x i2> inreg %value, <4 x i2> inreg %amount) {1996; GCN-LABEL: s_ashr_v4i2:1997; GCN: ; %bb.0:1998; GCN-NEXT: s_and_b32 s4, s4, 31999; GCN-NEXT: s_bfe_i32 s0, s0, 0x200002000; GCN-NEXT: s_ashr_i32 s0, s0, s42001; GCN-NEXT: s_and_b32 s4, s5, 32002; GCN-NEXT: s_bfe_i32 s1, s1, 0x200002003; GCN-NEXT: s_ashr_i32 s1, s1, s42004; GCN-NEXT: s_and_b32 s4, s6, 32005; GCN-NEXT: s_bfe_i32 s2, s2, 0x200002006; GCN-NEXT: s_ashr_i32 s2, s2, s42007; GCN-NEXT: s_and_b32 s4, s7, 32008; GCN-NEXT: s_bfe_i32 s3, s3, 0x200002009; GCN-NEXT: s_ashr_i32 s3, s3, s42010; GCN-NEXT: ; return to shader part epilog2011;2012; GFX10PLUS-LABEL: s_ashr_v4i2:2013; GFX10PLUS: ; %bb.0:2014; GFX10PLUS-NEXT: s_and_b32 s4, s4, 32015; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x200002016; GFX10PLUS-NEXT: s_and_b32 s5, s5, 32017; GFX10PLUS-NEXT: s_bfe_i32 s1, s1, 0x200002018; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, s42019; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, s52020; GFX10PLUS-NEXT: s_and_b32 s4, s6, 32021; GFX10PLUS-NEXT: s_bfe_i32 s2, s2, 0x200002022; GFX10PLUS-NEXT: s_and_b32 s5, s7, 32023; GFX10PLUS-NEXT: s_bfe_i32 s3, s3, 0x200002024; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, s42025; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s52026; GFX10PLUS-NEXT: ; return to shader part epilog2027 %result = ashr <4 x i2> %value, %amount2028 ret <4 x i2> %result2029}2030 2031; FIXME: Argument lowering asserts2032; define <2 x i65> @v_ashr_v2i65(<2 x i65> %value, <2 x i65> %amount) {2033; %result = ashr <2 x i65> %value, %amount2034; ret <2 x i65> %result2035; }2036 2037; define amdgpu_ps <2 x i65> @s_ashr_v2i65(<2 x i65> inreg %value, <2 x i65> inreg %amount) {2038; %result = ashr <2 x i65> %value, %amount2039; ret <2 x i65> %result2040; }2041