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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-atomic-optimizer %s | FileCheck -check-prefix=IR %s3; RUN: llc -global-isel -mtriple=amdgcn-- < %s | FileCheck -check-prefix=GCN %s4 5declare i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)6declare i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)7declare i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32, <4 x i32>, i32, i32, i32, i32 immarg)8declare void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32 immarg)9 10declare i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add.i32(i32, ptr addrspace(8), i32, i32, i32, i32 immarg)11declare i32 @llvm.amdgcn.struct.ptr.buffer.atomic.sub.i32(i32, ptr addrspace (8), i32, i32, i32, i32 immarg)12declare i32 @llvm.amdgcn.struct.ptr.buffer.atomic.xor.i32(i32, ptr addrspace(8), i32, i32, i32, i32 immarg)13declare void @llvm.amdgcn.struct.ptr.buffer.store.format.v4i32(<4 x i32>, ptr addrspace(8), i32, i32, i32, i32 immarg)14 15 16define amdgpu_cs void @atomic_add(<4 x i32> inreg %arg) {17; IR-LABEL: define amdgpu_cs void @atomic_add(18; IR-SAME: <4 x i32> inreg [[ARG:%.*]]) {19; IR-NEXT: [[_ENTRY:.*:]]20; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)21; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i3222; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 3223; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i3224; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)25; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])26; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])27; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i3228; IR-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 029; IR-NEXT: br i1 [[TMP8]], label %[[BB9:.*]], label %[[BB11:.*]]30; IR: [[BB9]]:31; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 [[TMP7]], <4 x i32> [[ARG]], i32 0, i32 0, i32 0, i32 0)32; IR-NEXT: br label %[[BB11]]33; IR: [[BB11]]:34; IR-NEXT: ret void35;36; GCN-LABEL: atomic_add:37; GCN: ; %bb.0: ; %.entry38; GCN-NEXT: s_mov_b64 s[4:5], exec39; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 040; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v041; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v042; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc43; GCN-NEXT: s_cbranch_execz .LBB0_244; GCN-NEXT: ; %bb.1:45; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]46; GCN-NEXT: v_mov_b32_e32 v0, 047; GCN-NEXT: v_mov_b32_e32 v1, s448; GCN-NEXT: buffer_atomic_add v1, v0, s[0:3], 0 idxen49; GCN-NEXT: .LBB0_2:50; GCN-NEXT: s_endpgm51.entry:52 call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)53 ret void54}55 56define amdgpu_cs void @atomic_add_and_format(<4 x i32> inreg %arg) {57; IR-LABEL: define amdgpu_cs void @atomic_add_and_format(58; IR-SAME: <4 x i32> inreg [[ARG:%.*]]) {59; IR-NEXT: [[_ENTRY:.*:]]60; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)61; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i3262; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 3263; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i3264; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)65; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])66; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])67; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i3268; IR-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 069; IR-NEXT: br i1 [[TMP8]], label %[[TMP9:.*]], label %[[BB11:.*]]70; IR: [[TMP9]]:71; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 [[TMP7]], <4 x i32> [[ARG]], i32 0, i32 0, i32 0, i32 0)72; IR-NEXT: br label %[[BB11]]73; IR: [[BB11]]:74; IR-NEXT: [[TMP12:%.*]] = phi i32 [ poison, [[DOTENTRY:%.*]] ], [ [[TMP10]], %[[TMP9]] ]75; IR-NEXT: [[TMP13:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP12]])76; IR-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], [[TMP5]]77; IR-NEXT: call void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32> [[ARG]], <4 x i32> [[ARG]], i32 [[TMP14]], i32 0, i32 0, i32 0)78; IR-NEXT: ret void79;80; GCN-LABEL: atomic_add_and_format:81; GCN: ; %bb.0: ; %.entry82; GCN-NEXT: s_mov_b64 s[6:7], exec83; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 084; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v085; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v086; GCN-NEXT: ; implicit-def: $vgpr187; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc88; GCN-NEXT: s_cbranch_execz .LBB1_289; GCN-NEXT: ; %bb.1:90; GCN-NEXT: s_bcnt1_i32_b64 s6, s[6:7]91; GCN-NEXT: v_mov_b32_e32 v1, s692; GCN-NEXT: v_mov_b32_e32 v2, 093; GCN-NEXT: buffer_atomic_add v1, v2, s[0:3], 0 idxen glc94; GCN-NEXT: .LBB1_2:95; GCN-NEXT: s_or_b64 exec, exec, s[4:5]96; GCN-NEXT: s_waitcnt vmcnt(0)97; GCN-NEXT: v_readfirstlane_b32 s4, v198; GCN-NEXT: v_add_i32_e32 v4, vcc, s4, v099; GCN-NEXT: s_waitcnt expcnt(0)100; GCN-NEXT: v_mov_b32_e32 v0, s0101; GCN-NEXT: v_mov_b32_e32 v1, s1102; GCN-NEXT: v_mov_b32_e32 v2, s2103; GCN-NEXT: v_mov_b32_e32 v3, s3104; GCN-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen105; GCN-NEXT: s_endpgm106.entry:107 %a = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)108 call void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32> %arg, <4 x i32> %arg, i32 %a, i32 0, i32 0, i32 0)109 ret void110}111 112define amdgpu_cs void @atomic_sub(<4 x i32> inreg %arg) {113; IR-LABEL: define amdgpu_cs void @atomic_sub(114; IR-SAME: <4 x i32> inreg [[ARG:%.*]]) {115; IR-NEXT: [[_ENTRY:.*:]]116; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)117; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32118; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32119; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32120; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)121; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])122; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])123; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32124; IR-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0125; IR-NEXT: br i1 [[TMP8]], label %[[BB9:.*]], label %[[BB11:.*]]126; IR: [[BB9]]:127; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 [[TMP7]], <4 x i32> [[ARG]], i32 0, i32 0, i32 0, i32 0)128; IR-NEXT: br label %[[BB11]]129; IR: [[BB11]]:130; IR-NEXT: ret void131;132; GCN-LABEL: atomic_sub:133; GCN: ; %bb.0: ; %.entry134; GCN-NEXT: s_mov_b64 s[4:5], exec135; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0136; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0137; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0138; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc139; GCN-NEXT: s_cbranch_execz .LBB2_2140; GCN-NEXT: ; %bb.1:141; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]142; GCN-NEXT: v_mov_b32_e32 v0, 0143; GCN-NEXT: v_mov_b32_e32 v1, s4144; GCN-NEXT: buffer_atomic_sub v1, v0, s[0:3], 0 idxen145; GCN-NEXT: .LBB2_2:146; GCN-NEXT: s_endpgm147.entry:148 call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)149 ret void150}151 152define amdgpu_cs void @atomic_sub_and_format(<4 x i32> inreg %arg) {153; IR-LABEL: define amdgpu_cs void @atomic_sub_and_format(154; IR-SAME: <4 x i32> inreg [[ARG:%.*]]) {155; IR-NEXT: [[_ENTRY:.*:]]156; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)157; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32158; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32159; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32160; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)161; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])162; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])163; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32164; IR-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0165; IR-NEXT: br i1 [[TMP8]], label %[[TMP9:.*]], label %[[BB11:.*]]166; IR: [[TMP9]]:167; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 [[TMP7]], <4 x i32> [[ARG]], i32 0, i32 0, i32 0, i32 0)168; IR-NEXT: br label %[[BB11]]169; IR: [[BB11]]:170; IR-NEXT: [[TMP12:%.*]] = phi i32 [ poison, [[DOTENTRY:%.*]] ], [ [[TMP10]], %[[TMP9]] ]171; IR-NEXT: [[TMP13:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP12]])172; IR-NEXT: [[TMP14:%.*]] = sub i32 [[TMP13]], [[TMP5]]173; IR-NEXT: call void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32> [[ARG]], <4 x i32> [[ARG]], i32 [[TMP14]], i32 0, i32 0, i32 0)174; IR-NEXT: ret void175;176; GCN-LABEL: atomic_sub_and_format:177; GCN: ; %bb.0: ; %.entry178; GCN-NEXT: s_mov_b64 s[6:7], exec179; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0180; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0181; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0182; GCN-NEXT: ; implicit-def: $vgpr1183; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc184; GCN-NEXT: s_cbranch_execz .LBB3_2185; GCN-NEXT: ; %bb.1:186; GCN-NEXT: s_bcnt1_i32_b64 s6, s[6:7]187; GCN-NEXT: v_mov_b32_e32 v1, s6188; GCN-NEXT: v_mov_b32_e32 v2, 0189; GCN-NEXT: buffer_atomic_sub v1, v2, s[0:3], 0 idxen glc190; GCN-NEXT: .LBB3_2:191; GCN-NEXT: s_or_b64 exec, exec, s[4:5]192; GCN-NEXT: s_waitcnt vmcnt(0)193; GCN-NEXT: v_readfirstlane_b32 s4, v1194; GCN-NEXT: v_sub_i32_e32 v4, vcc, s4, v0195; GCN-NEXT: s_waitcnt expcnt(0)196; GCN-NEXT: v_mov_b32_e32 v0, s0197; GCN-NEXT: v_mov_b32_e32 v1, s1198; GCN-NEXT: v_mov_b32_e32 v2, s2199; GCN-NEXT: v_mov_b32_e32 v3, s3200; GCN-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen201; GCN-NEXT: s_endpgm202.entry:203 %a = call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)204 call void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32> %arg, <4 x i32> %arg, i32 %a, i32 0, i32 0, i32 0)205 ret void206}207 208define amdgpu_cs void @atomic_xor(<4 x i32> inreg %arg) {209; IR-LABEL: define amdgpu_cs void @atomic_xor(210; IR-SAME: <4 x i32> inreg [[ARG:%.*]]) {211; IR-NEXT: [[_ENTRY:.*:]]212; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)213; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32214; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32215; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32216; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)217; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])218; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])219; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32220; IR-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], 1221; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0222; IR-NEXT: br i1 [[TMP9]], label %[[BB10:.*]], label %[[BB12:.*]]223; IR: [[BB10]]:224; IR-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 [[TMP8]], <4 x i32> [[ARG]], i32 0, i32 0, i32 0, i32 0)225; IR-NEXT: br label %[[BB12]]226; IR: [[BB12]]:227; IR-NEXT: ret void228;229; GCN-LABEL: atomic_xor:230; GCN: ; %bb.0: ; %.entry231; GCN-NEXT: s_mov_b64 s[4:5], exec232; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0233; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0234; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0235; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc236; GCN-NEXT: s_cbranch_execz .LBB4_2237; GCN-NEXT: ; %bb.1:238; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]239; GCN-NEXT: s_and_b32 s4, s4, 1240; GCN-NEXT: v_mov_b32_e32 v0, 0241; GCN-NEXT: v_mov_b32_e32 v1, s4242; GCN-NEXT: buffer_atomic_xor v1, v0, s[0:3], 0 idxen243; GCN-NEXT: .LBB4_2:244; GCN-NEXT: s_endpgm245.entry:246 call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)247 ret void248}249 250define amdgpu_cs void @atomic_xor_and_format(<4 x i32> inreg %arg) {251; IR-LABEL: define amdgpu_cs void @atomic_xor_and_format(252; IR-SAME: <4 x i32> inreg [[ARG:%.*]]) {253; IR-NEXT: [[_ENTRY:.*:]]254; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)255; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32256; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32257; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32258; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)259; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])260; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])261; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32262; IR-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], 1263; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0264; IR-NEXT: br i1 [[TMP9]], label %[[TMP10:.*]], label %[[BB12:.*]]265; IR: [[TMP10]]:266; IR-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 [[TMP8]], <4 x i32> [[ARG]], i32 0, i32 0, i32 0, i32 0)267; IR-NEXT: br label %[[BB12]]268; IR: [[BB12]]:269; IR-NEXT: [[TMP13:%.*]] = phi i32 [ poison, [[DOTENTRY:%.*]] ], [ [[TMP11]], %[[TMP10]] ]270; IR-NEXT: [[TMP14:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP13]])271; IR-NEXT: [[TMP15:%.*]] = and i32 [[TMP5]], 1272; IR-NEXT: [[TMP16:%.*]] = xor i32 [[TMP14]], [[TMP15]]273; IR-NEXT: call void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32> [[ARG]], <4 x i32> [[ARG]], i32 [[TMP16]], i32 0, i32 0, i32 0)274; IR-NEXT: ret void275;276; GCN-LABEL: atomic_xor_and_format:277; GCN: ; %bb.0: ; %.entry278; GCN-NEXT: s_mov_b64 s[6:7], exec279; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0280; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0281; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0282; GCN-NEXT: ; implicit-def: $vgpr1283; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc284; GCN-NEXT: s_cbranch_execz .LBB5_2285; GCN-NEXT: ; %bb.1:286; GCN-NEXT: s_bcnt1_i32_b64 s6, s[6:7]287; GCN-NEXT: s_and_b32 s6, s6, 1288; GCN-NEXT: v_mov_b32_e32 v1, s6289; GCN-NEXT: v_mov_b32_e32 v2, 0290; GCN-NEXT: buffer_atomic_xor v1, v2, s[0:3], 0 idxen glc291; GCN-NEXT: .LBB5_2:292; GCN-NEXT: s_or_b64 exec, exec, s[4:5]293; GCN-NEXT: s_waitcnt vmcnt(0)294; GCN-NEXT: v_readfirstlane_b32 s4, v1295; GCN-NEXT: v_and_b32_e32 v0, 1, v0296; GCN-NEXT: v_xor_b32_e32 v4, s4, v0297; GCN-NEXT: s_waitcnt expcnt(0)298; GCN-NEXT: v_mov_b32_e32 v0, s0299; GCN-NEXT: v_mov_b32_e32 v1, s1300; GCN-NEXT: v_mov_b32_e32 v2, s2301; GCN-NEXT: v_mov_b32_e32 v3, s3302; GCN-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen303; GCN-NEXT: s_endpgm304.entry:305 %a = call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 1, <4 x i32> %arg, i32 0, i32 0, i32 0, i32 0)306 call void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32> %arg, <4 x i32> %arg, i32 %a, i32 0, i32 0, i32 0)307 ret void308}309 310define amdgpu_cs void @atomic_ptr_add(ptr addrspace(8) inreg %arg) {311; IR-LABEL: define amdgpu_cs void @atomic_ptr_add(312; IR-SAME: ptr addrspace(8) inreg [[ARG:%.*]]) {313; IR-NEXT: [[_ENTRY:.*:]]314; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)315; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32316; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32317; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32318; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)319; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])320; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])321; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32322; IR-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0323; IR-NEXT: br i1 [[TMP8]], label %[[BB9:.*]], label %[[BB11:.*]]324; IR: [[BB9]]:325; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add.i32(i32 [[TMP7]], ptr addrspace(8) [[ARG]], i32 0, i32 0, i32 0, i32 0)326; IR-NEXT: br label %[[BB11]]327; IR: [[BB11]]:328; IR-NEXT: ret void329;330; GCN-LABEL: atomic_ptr_add:331; GCN: ; %bb.0: ; %.entry332; GCN-NEXT: s_mov_b64 s[4:5], exec333; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0334; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0335; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0336; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc337; GCN-NEXT: s_cbranch_execz .LBB6_2338; GCN-NEXT: ; %bb.1:339; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]340; GCN-NEXT: v_mov_b32_e32 v0, 0341; GCN-NEXT: v_mov_b32_e32 v1, s4342; GCN-NEXT: buffer_atomic_add v1, v0, s[0:3], 0 idxen343; GCN-NEXT: .LBB6_2:344; GCN-NEXT: s_endpgm345.entry:346 call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add.i32(i32 1, ptr addrspace(8) %arg, i32 0, i32 0, i32 0, i32 0)347 ret void348}349 350define amdgpu_cs void @atomic_ptr_add_and_format(ptr addrspace(8) inreg %arg) {351; IR-LABEL: define amdgpu_cs void @atomic_ptr_add_and_format(352; IR-SAME: ptr addrspace(8) inreg [[ARG:%.*]]) {353; IR-NEXT: [[_ENTRY:.*:]]354; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)355; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32356; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32357; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32358; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)359; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])360; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])361; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32362; IR-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0363; IR-NEXT: br i1 [[TMP8]], label %[[TMP9:.*]], label %[[BB11:.*]]364; IR: [[TMP9]]:365; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add.i32(i32 [[TMP7]], ptr addrspace(8) [[ARG]], i32 0, i32 0, i32 0, i32 0)366; IR-NEXT: br label %[[BB11]]367; IR: [[BB11]]:368; IR-NEXT: [[TMP12:%.*]] = phi i32 [ poison, [[DOTENTRY:%.*]] ], [ [[TMP10]], %[[TMP9]] ]369; IR-NEXT: [[TMP13:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP12]])370; IR-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], [[TMP5]]371; IR-NEXT: [[ARG_INT:%.*]] = ptrtoint ptr addrspace(8) [[ARG]] to i128372; IR-NEXT: [[ARG_VEC:%.*]] = bitcast i128 [[ARG_INT]] to <4 x i32>373; IR-NEXT: call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4i32(<4 x i32> [[ARG_VEC]], ptr addrspace(8) [[ARG]], i32 [[TMP14]], i32 0, i32 0, i32 0)374; IR-NEXT: ret void375;376; GCN-LABEL: atomic_ptr_add_and_format:377; GCN: ; %bb.0: ; %.entry378; GCN-NEXT: s_mov_b64 s[6:7], exec379; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0380; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0381; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0382; GCN-NEXT: ; implicit-def: $vgpr1383; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc384; GCN-NEXT: s_cbranch_execz .LBB7_2385; GCN-NEXT: ; %bb.1:386; GCN-NEXT: s_bcnt1_i32_b64 s6, s[6:7]387; GCN-NEXT: v_mov_b32_e32 v1, s6388; GCN-NEXT: v_mov_b32_e32 v2, 0389; GCN-NEXT: buffer_atomic_add v1, v2, s[0:3], 0 idxen glc390; GCN-NEXT: .LBB7_2:391; GCN-NEXT: s_or_b64 exec, exec, s[4:5]392; GCN-NEXT: s_waitcnt vmcnt(0)393; GCN-NEXT: v_readfirstlane_b32 s4, v1394; GCN-NEXT: v_add_i32_e32 v4, vcc, s4, v0395; GCN-NEXT: s_waitcnt expcnt(0)396; GCN-NEXT: v_mov_b32_e32 v0, s0397; GCN-NEXT: v_mov_b32_e32 v1, s1398; GCN-NEXT: v_mov_b32_e32 v2, s2399; GCN-NEXT: v_mov_b32_e32 v3, s3400; GCN-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen401; GCN-NEXT: s_endpgm402.entry:403 %a = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add.i32(i32 1, ptr addrspace(8) %arg, i32 0, i32 0, i32 0, i32 0)404 %arg.int = ptrtoint ptr addrspace(8) %arg to i128405 %arg.vec = bitcast i128 %arg.int to <4 x i32>406 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4i32(<4 x i32> %arg.vec, ptr addrspace(8) %arg, i32 %a, i32 0, i32 0, i32 0)407 ret void408}409 410define amdgpu_cs void @atomic_ptr_sub(ptr addrspace(8) inreg %arg) {411; IR-LABEL: define amdgpu_cs void @atomic_ptr_sub(412; IR-SAME: ptr addrspace(8) inreg [[ARG:%.*]]) {413; IR-NEXT: [[_ENTRY:.*:]]414; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)415; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32416; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32417; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32418; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)419; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])420; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])421; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32422; IR-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0423; IR-NEXT: br i1 [[TMP8]], label %[[BB9:.*]], label %[[BB11:.*]]424; IR: [[BB9]]:425; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.sub.i32(i32 [[TMP7]], ptr addrspace(8) [[ARG]], i32 0, i32 0, i32 0, i32 0)426; IR-NEXT: br label %[[BB11]]427; IR: [[BB11]]:428; IR-NEXT: ret void429;430; GCN-LABEL: atomic_ptr_sub:431; GCN: ; %bb.0: ; %.entry432; GCN-NEXT: s_mov_b64 s[4:5], exec433; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0434; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0435; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0436; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc437; GCN-NEXT: s_cbranch_execz .LBB8_2438; GCN-NEXT: ; %bb.1:439; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]440; GCN-NEXT: v_mov_b32_e32 v0, 0441; GCN-NEXT: v_mov_b32_e32 v1, s4442; GCN-NEXT: buffer_atomic_sub v1, v0, s[0:3], 0 idxen443; GCN-NEXT: .LBB8_2:444; GCN-NEXT: s_endpgm445.entry:446 call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.sub.i32(i32 1, ptr addrspace(8) %arg, i32 0, i32 0, i32 0, i32 0)447 ret void448}449 450define amdgpu_cs void @atomic_ptr_sub_and_format(ptr addrspace(8) inreg %arg) {451; IR-LABEL: define amdgpu_cs void @atomic_ptr_sub_and_format(452; IR-SAME: ptr addrspace(8) inreg [[ARG:%.*]]) {453; IR-NEXT: [[_ENTRY:.*:]]454; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)455; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32456; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32457; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32458; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)459; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])460; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])461; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32462; IR-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0463; IR-NEXT: br i1 [[TMP8]], label %[[TMP9:.*]], label %[[BB11:.*]]464; IR: [[TMP9]]:465; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.sub.i32(i32 [[TMP7]], ptr addrspace(8) [[ARG]], i32 0, i32 0, i32 0, i32 0)466; IR-NEXT: br label %[[BB11]]467; IR: [[BB11]]:468; IR-NEXT: [[TMP12:%.*]] = phi i32 [ poison, [[DOTENTRY:%.*]] ], [ [[TMP10]], %[[TMP9]] ]469; IR-NEXT: [[TMP13:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP12]])470; IR-NEXT: [[TMP14:%.*]] = sub i32 [[TMP13]], [[TMP5]]471; IR-NEXT: [[ARG_INT:%.*]] = ptrtoint ptr addrspace(8) [[ARG]] to i128472; IR-NEXT: [[ARG_VEC:%.*]] = bitcast i128 [[ARG_INT]] to <4 x i32>473; IR-NEXT: call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4i32(<4 x i32> [[ARG_VEC]], ptr addrspace(8) [[ARG]], i32 [[TMP14]], i32 0, i32 0, i32 0)474; IR-NEXT: ret void475;476; GCN-LABEL: atomic_ptr_sub_and_format:477; GCN: ; %bb.0: ; %.entry478; GCN-NEXT: s_mov_b64 s[6:7], exec479; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0480; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0481; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0482; GCN-NEXT: ; implicit-def: $vgpr1483; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc484; GCN-NEXT: s_cbranch_execz .LBB9_2485; GCN-NEXT: ; %bb.1:486; GCN-NEXT: s_bcnt1_i32_b64 s6, s[6:7]487; GCN-NEXT: v_mov_b32_e32 v1, s6488; GCN-NEXT: v_mov_b32_e32 v2, 0489; GCN-NEXT: buffer_atomic_sub v1, v2, s[0:3], 0 idxen glc490; GCN-NEXT: .LBB9_2:491; GCN-NEXT: s_or_b64 exec, exec, s[4:5]492; GCN-NEXT: s_waitcnt vmcnt(0)493; GCN-NEXT: v_readfirstlane_b32 s4, v1494; GCN-NEXT: v_sub_i32_e32 v4, vcc, s4, v0495; GCN-NEXT: s_waitcnt expcnt(0)496; GCN-NEXT: v_mov_b32_e32 v0, s0497; GCN-NEXT: v_mov_b32_e32 v1, s1498; GCN-NEXT: v_mov_b32_e32 v2, s2499; GCN-NEXT: v_mov_b32_e32 v3, s3500; GCN-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen501; GCN-NEXT: s_endpgm502.entry:503 %a = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.sub.i32(i32 1, ptr addrspace(8) %arg, i32 0, i32 0, i32 0, i32 0)504 %arg.int = ptrtoint ptr addrspace(8) %arg to i128505 %arg.vec = bitcast i128 %arg.int to <4 x i32>506 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4i32(<4 x i32> %arg.vec, ptr addrspace(8) %arg, i32 %a, i32 0, i32 0, i32 0)507 ret void508}509 510define amdgpu_cs void @atomic_ptr_xor(ptr addrspace(8) inreg %arg) {511; IR-LABEL: define amdgpu_cs void @atomic_ptr_xor(512; IR-SAME: ptr addrspace(8) inreg [[ARG:%.*]]) {513; IR-NEXT: [[_ENTRY:.*:]]514; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)515; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32516; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32517; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32518; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)519; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])520; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])521; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32522; IR-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], 1523; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0524; IR-NEXT: br i1 [[TMP9]], label %[[BB10:.*]], label %[[BB12:.*]]525; IR: [[BB10]]:526; IR-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.xor.i32(i32 [[TMP8]], ptr addrspace(8) [[ARG]], i32 0, i32 0, i32 0, i32 0)527; IR-NEXT: br label %[[BB12]]528; IR: [[BB12]]:529; IR-NEXT: ret void530;531; GCN-LABEL: atomic_ptr_xor:532; GCN: ; %bb.0: ; %.entry533; GCN-NEXT: s_mov_b64 s[4:5], exec534; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0535; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0536; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0537; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc538; GCN-NEXT: s_cbranch_execz .LBB10_2539; GCN-NEXT: ; %bb.1:540; GCN-NEXT: s_bcnt1_i32_b64 s4, s[4:5]541; GCN-NEXT: s_and_b32 s4, s4, 1542; GCN-NEXT: v_mov_b32_e32 v0, 0543; GCN-NEXT: v_mov_b32_e32 v1, s4544; GCN-NEXT: buffer_atomic_xor v1, v0, s[0:3], 0 idxen545; GCN-NEXT: .LBB10_2:546; GCN-NEXT: s_endpgm547.entry:548 call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.xor.i32(i32 1, ptr addrspace(8) %arg, i32 0, i32 0, i32 0, i32 0)549 ret void550}551 552define amdgpu_cs void @atomic_ptr_xor_and_format(ptr addrspace(8) inreg %arg) {553; IR-LABEL: define amdgpu_cs void @atomic_ptr_xor_and_format(554; IR-SAME: ptr addrspace(8) inreg [[ARG:%.*]]) {555; IR-NEXT: [[_ENTRY:.*:]]556; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)557; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32558; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32559; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32560; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)561; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])562; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])563; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32564; IR-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], 1565; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0566; IR-NEXT: br i1 [[TMP9]], label %[[TMP10:.*]], label %[[BB12:.*]]567; IR: [[TMP10]]:568; IR-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.xor.i32(i32 [[TMP8]], ptr addrspace(8) [[ARG]], i32 0, i32 0, i32 0, i32 0)569; IR-NEXT: br label %[[BB12]]570; IR: [[BB12]]:571; IR-NEXT: [[TMP13:%.*]] = phi i32 [ poison, [[DOTENTRY:%.*]] ], [ [[TMP11]], %[[TMP10]] ]572; IR-NEXT: [[TMP14:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP13]])573; IR-NEXT: [[TMP15:%.*]] = and i32 [[TMP5]], 1574; IR-NEXT: [[TMP16:%.*]] = xor i32 [[TMP14]], [[TMP15]]575; IR-NEXT: [[ARG_INT:%.*]] = ptrtoint ptr addrspace(8) [[ARG]] to i128576; IR-NEXT: [[ARG_VEC:%.*]] = bitcast i128 [[ARG_INT]] to <4 x i32>577; IR-NEXT: call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4i32(<4 x i32> [[ARG_VEC]], ptr addrspace(8) [[ARG]], i32 [[TMP16]], i32 0, i32 0, i32 0)578; IR-NEXT: ret void579;580; GCN-LABEL: atomic_ptr_xor_and_format:581; GCN: ; %bb.0: ; %.entry582; GCN-NEXT: s_mov_b64 s[6:7], exec583; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0584; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0585; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0586; GCN-NEXT: ; implicit-def: $vgpr1587; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc588; GCN-NEXT: s_cbranch_execz .LBB11_2589; GCN-NEXT: ; %bb.1:590; GCN-NEXT: s_bcnt1_i32_b64 s6, s[6:7]591; GCN-NEXT: s_and_b32 s6, s6, 1592; GCN-NEXT: v_mov_b32_e32 v1, s6593; GCN-NEXT: v_mov_b32_e32 v2, 0594; GCN-NEXT: buffer_atomic_xor v1, v2, s[0:3], 0 idxen glc595; GCN-NEXT: .LBB11_2:596; GCN-NEXT: s_or_b64 exec, exec, s[4:5]597; GCN-NEXT: s_waitcnt vmcnt(0)598; GCN-NEXT: v_readfirstlane_b32 s4, v1599; GCN-NEXT: v_and_b32_e32 v0, 1, v0600; GCN-NEXT: v_xor_b32_e32 v4, s4, v0601; GCN-NEXT: s_waitcnt expcnt(0)602; GCN-NEXT: v_mov_b32_e32 v0, s0603; GCN-NEXT: v_mov_b32_e32 v1, s1604; GCN-NEXT: v_mov_b32_e32 v2, s2605; GCN-NEXT: v_mov_b32_e32 v3, s3606; GCN-NEXT: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen607; GCN-NEXT: s_endpgm608.entry:609 %a = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.xor.i32(i32 1, ptr addrspace(8) %arg, i32 0, i32 0, i32 0, i32 0)610 %arg.int = ptrtoint ptr addrspace(8) %arg to i128611 %arg.vec = bitcast i128 %arg.int to <4 x i32>612 call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4i32(<4 x i32> %arg.vec, ptr addrspace(8) %arg, i32 %a, i32 0, i32 0, i32 0)613 ret void614}615