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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,WAVE64 %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1031 < %s | FileCheck -check-prefixes=GCN,WAVE32 %s4 5; End to end tests for scalar vs. vector boolean legalization strategies.6 7define amdgpu_ps float @select_vgpr_sgpr_trunc_cond(i32 inreg %a, i32 %b, i32 %c) {8; WAVE64-LABEL: select_vgpr_sgpr_trunc_cond:9; WAVE64: ; %bb.0:10; WAVE64-NEXT: s_cmp_lg_u32 s0, 011; WAVE64-NEXT: s_cselect_b64 vcc, exec, 012; WAVE64-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc13; WAVE64-NEXT: ; return to shader part epilog14;15; WAVE32-LABEL: select_vgpr_sgpr_trunc_cond:16; WAVE32: ; %bb.0:17; WAVE32-NEXT: s_cmp_lg_u32 s0, 018; WAVE32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 019; WAVE32-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo20; WAVE32-NEXT: ; return to shader part epilog21 %cc = trunc i32 %a to i122 %r = select i1 %cc, i32 %b, i32 %c23 %r.f = bitcast i32 %r to float24 ret float %r.f25}26 27define amdgpu_ps float @select_vgpr_sgpr_trunc_and_cond(i32 inreg %a.0, i32 inreg %a.1, i32 %b, i32 %c) {28; WAVE64-LABEL: select_vgpr_sgpr_trunc_and_cond:29; WAVE64: ; %bb.0:30; WAVE64-NEXT: s_and_b32 s0, s0, s131; WAVE64-NEXT: s_cmp_lg_u32 s0, 032; WAVE64-NEXT: s_cselect_b64 vcc, exec, 033; WAVE64-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc34; WAVE64-NEXT: ; return to shader part epilog35;36; WAVE32-LABEL: select_vgpr_sgpr_trunc_and_cond:37; WAVE32: ; %bb.0:38; WAVE32-NEXT: s_and_b32 s0, s0, s139; WAVE32-NEXT: s_cmp_lg_u32 s0, 040; WAVE32-NEXT: s_cselect_b32 vcc_lo, exec_lo, 041; WAVE32-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo42; WAVE32-NEXT: ; return to shader part epilog43 %cc.0 = trunc i32 %a.0 to i144 %cc.1 = trunc i32 %a.1 to i145 %and = and i1 %cc.0, %cc.146 %r = select i1 %and, i32 %b, i32 %c47 %r.f = bitcast i32 %r to float48 ret float %r.f49}50 51define amdgpu_ps i32 @select_sgpr_trunc_and_cond(i32 inreg %a.0, i32 inreg %a.1, i32 inreg %b, i32 inreg %c) {52; GCN-LABEL: select_sgpr_trunc_and_cond:53; GCN: ; %bb.0:54; GCN-NEXT: s_and_b32 s0, s0, s155; GCN-NEXT: s_and_b32 s0, s0, 156; GCN-NEXT: s_cmp_lg_u32 s0, 057; GCN-NEXT: s_cselect_b32 s0, s2, s358; GCN-NEXT: ; return to shader part epilog59 %cc.0 = trunc i32 %a.0 to i160 %cc.1 = trunc i32 %a.1 to i161 %and = and i1 %cc.0, %cc.162 %r = select i1 %and, i32 %b, i32 %c63 ret i32 %r64}65 66define amdgpu_kernel void @sgpr_trunc_brcond(i32 %cond) {67; WAVE64-LABEL: sgpr_trunc_brcond:68; WAVE64: ; %bb.0: ; %entry69; WAVE64-NEXT: s_load_dword s0, s[4:5], 0x2470; WAVE64-NEXT: s_waitcnt lgkmcnt(0)71; WAVE64-NEXT: s_xor_b32 s0, s0, 172; WAVE64-NEXT: s_and_b32 s0, s0, 173; WAVE64-NEXT: s_cmp_lg_u32 s0, 074; WAVE64-NEXT: s_cbranch_scc1 .LBB3_275; WAVE64-NEXT: ; %bb.1: ; %bb076; WAVE64-NEXT: v_mov_b32_e32 v0, 077; WAVE64-NEXT: global_store_dword v[0:1], v0, off78; WAVE64-NEXT: s_waitcnt vmcnt(0)79; WAVE64-NEXT: .LBB3_2: ; %bb180; WAVE64-NEXT: v_mov_b32_e32 v0, 181; WAVE64-NEXT: global_store_dword v[0:1], v0, off82; WAVE64-NEXT: s_waitcnt vmcnt(0)83;84; WAVE32-LABEL: sgpr_trunc_brcond:85; WAVE32: ; %bb.0: ; %entry86; WAVE32-NEXT: s_load_dword s0, s[4:5], 0x2487; WAVE32-NEXT: s_waitcnt lgkmcnt(0)88; WAVE32-NEXT: s_xor_b32 s0, s0, 189; WAVE32-NEXT: s_and_b32 s0, s0, 190; WAVE32-NEXT: s_cmp_lg_u32 s0, 091; WAVE32-NEXT: s_cbranch_scc1 .LBB3_292; WAVE32-NEXT: ; %bb.1: ; %bb093; WAVE32-NEXT: v_mov_b32_e32 v0, 094; WAVE32-NEXT: global_store_dword v[0:1], v0, off95; WAVE32-NEXT: s_waitcnt_vscnt null, 0x096; WAVE32-NEXT: .LBB3_2: ; %bb197; WAVE32-NEXT: v_mov_b32_e32 v0, 198; WAVE32-NEXT: global_store_dword v[0:1], v0, off99; WAVE32-NEXT: s_waitcnt_vscnt null, 0x0100entry:101 %trunc = trunc i32 %cond to i1102 br i1 %trunc, label %bb0, label %bb1103 104bb0:105 store volatile i32 0, ptr addrspace(1) poison106 unreachable107 108bb1:109 store volatile i32 1, ptr addrspace(1) poison110 unreachable111}112 113define amdgpu_kernel void @brcond_sgpr_trunc_and(i32 %cond0, i32 %cond1) {114; WAVE64-LABEL: brcond_sgpr_trunc_and:115; WAVE64: ; %bb.0: ; %entry116; WAVE64-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24117; WAVE64-NEXT: s_waitcnt lgkmcnt(0)118; WAVE64-NEXT: s_and_b32 s0, s0, s1119; WAVE64-NEXT: s_xor_b32 s0, s0, 1120; WAVE64-NEXT: s_and_b32 s0, s0, 1121; WAVE64-NEXT: s_cmp_lg_u32 s0, 0122; WAVE64-NEXT: s_cbranch_scc1 .LBB4_2123; WAVE64-NEXT: ; %bb.1: ; %bb0124; WAVE64-NEXT: v_mov_b32_e32 v0, 0125; WAVE64-NEXT: global_store_dword v[0:1], v0, off126; WAVE64-NEXT: s_waitcnt vmcnt(0)127; WAVE64-NEXT: .LBB4_2: ; %bb1128; WAVE64-NEXT: v_mov_b32_e32 v0, 1129; WAVE64-NEXT: global_store_dword v[0:1], v0, off130; WAVE64-NEXT: s_waitcnt vmcnt(0)131;132; WAVE32-LABEL: brcond_sgpr_trunc_and:133; WAVE32: ; %bb.0: ; %entry134; WAVE32-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24135; WAVE32-NEXT: s_waitcnt lgkmcnt(0)136; WAVE32-NEXT: s_and_b32 s0, s0, s1137; WAVE32-NEXT: s_xor_b32 s0, s0, 1138; WAVE32-NEXT: s_and_b32 s0, s0, 1139; WAVE32-NEXT: s_cmp_lg_u32 s0, 0140; WAVE32-NEXT: s_cbranch_scc1 .LBB4_2141; WAVE32-NEXT: ; %bb.1: ; %bb0142; WAVE32-NEXT: v_mov_b32_e32 v0, 0143; WAVE32-NEXT: global_store_dword v[0:1], v0, off144; WAVE32-NEXT: s_waitcnt_vscnt null, 0x0145; WAVE32-NEXT: .LBB4_2: ; %bb1146; WAVE32-NEXT: v_mov_b32_e32 v0, 1147; WAVE32-NEXT: global_store_dword v[0:1], v0, off148; WAVE32-NEXT: s_waitcnt_vscnt null, 0x0149entry:150 %trunc0 = trunc i32 %cond0 to i1151 %trunc1 = trunc i32 %cond1 to i1152 %and = and i1 %trunc0, %trunc1153 br i1 %and, label %bb0, label %bb1154 155bb0:156 store volatile i32 0, ptr addrspace(1) poison157 unreachable158 159bb1:160 store volatile i32 1, ptr addrspace(1) poison161 unreachable162}163