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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a -stop-after=instruction-select < %s | FileCheck --check-prefix=GFX9 %s3 4define ptr @buffer_load_p0(ptr addrspace(8) inreg %buf) {5 ; GFX9-LABEL: name: buffer_load_p06 ; GFX9: bb.1 (%ir-block.0):7 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr198 ; GFX9-NEXT: {{ $}}9 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1610 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1711 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1812 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1913 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 014 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub315 ; GFX9-NEXT: [[BUFFER_LOAD_DWORDX2_OFFSET:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (s64) from %ir.buf, align 1, addrspace 8)16 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFSET]].sub017 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFSET]].sub118 ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]]19 ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]]20 ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr121 %ret = call ptr @llvm.amdgcn.raw.ptr.buffer.load.p0(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)22 ret ptr %ret23}24 25define void @buffer_store_p0(ptr %data, ptr addrspace(8) inreg %buf) {26 ; GFX9-LABEL: name: buffer_store_p027 ; GFX9: bb.1 (%ir-block.0):28 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0, $vgpr129 ; GFX9-NEXT: {{ $}}30 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr031 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr132 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub133 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1634 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1735 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr1836 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1937 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 038 ; GFX9-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub339 ; GFX9-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[REG_SEQUENCE]], [[REG_SEQUENCE1]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into %ir.buf, align 1, addrspace 8)40 ; GFX9-NEXT: SI_RETURN41 call void @llvm.amdgcn.raw.ptr.buffer.store.p0(ptr %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)42 ret void43}44 45define ptr addrspace(1) @buffer_load_p1(ptr addrspace(8) inreg %buf) {46 ; GFX9-LABEL: name: buffer_load_p147 ; GFX9: bb.1 (%ir-block.0):48 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr1949 ; GFX9-NEXT: {{ $}}50 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1651 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1752 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1853 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1954 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 055 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub356 ; GFX9-NEXT: [[BUFFER_LOAD_DWORDX2_OFFSET:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (s64) from %ir.buf, align 1, addrspace 8)57 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFSET]].sub058 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFSET]].sub159 ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]]60 ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]]61 ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr162 %ret = call ptr addrspace(1) @llvm.amdgcn.raw.ptr.buffer.load.p1(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)63 ret ptr addrspace(1) %ret64}65 66define void @buffer_store_p1(ptr addrspace(1) %data, ptr addrspace(8) inreg %buf) {67 ; GFX9-LABEL: name: buffer_store_p168 ; GFX9: bb.1 (%ir-block.0):69 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0, $vgpr170 ; GFX9-NEXT: {{ $}}71 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr072 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr173 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub174 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1675 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1776 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr1877 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1978 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 079 ; GFX9-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub380 ; GFX9-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[REG_SEQUENCE]], [[REG_SEQUENCE1]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into %ir.buf, align 1, addrspace 8)81 ; GFX9-NEXT: SI_RETURN82 call void @llvm.amdgcn.raw.ptr.buffer.store.p1(ptr addrspace(1) %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)83 ret void84}85 86define ptr addrspace(4) @buffer_load_p4(ptr addrspace(8) inreg %buf) {87 ; GFX9-LABEL: name: buffer_load_p488 ; GFX9: bb.1 (%ir-block.0):89 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr1990 ; GFX9-NEXT: {{ $}}91 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1692 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1793 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1894 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1995 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 096 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub397 ; GFX9-NEXT: [[BUFFER_LOAD_DWORDX2_OFFSET:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (s64) from %ir.buf, align 1, addrspace 8)98 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFSET]].sub099 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_OFFSET]].sub1100 ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]]101 ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]]102 ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1103 %ret = call ptr addrspace(4) @llvm.amdgcn.raw.ptr.buffer.load.p4(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)104 ret ptr addrspace(4) %ret105}106 107define void @buffer_store_p4(ptr addrspace(4) %data, ptr addrspace(8) inreg %buf) {108 ; GFX9-LABEL: name: buffer_store_p4109 ; GFX9: bb.1 (%ir-block.0):110 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0, $vgpr1111 ; GFX9-NEXT: {{ $}}112 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0113 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1114 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1115 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr16116 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr17117 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr18118 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr19119 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0120 ; GFX9-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3121 ; GFX9-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[REG_SEQUENCE]], [[REG_SEQUENCE1]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into %ir.buf, align 1, addrspace 8)122 ; GFX9-NEXT: SI_RETURN123 call void @llvm.amdgcn.raw.ptr.buffer.store.p4(ptr addrspace(4) %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)124 ret void125}126 127define ptr addrspace(5) @buffer_load_p5(ptr addrspace(8) inreg %buf) {128 ; GFX9-LABEL: name: buffer_load_p5129 ; GFX9: bb.1 (%ir-block.0):130 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19131 ; GFX9-NEXT: {{ $}}132 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr16133 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr17134 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18135 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr19136 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0137 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3138 ; GFX9-NEXT: [[BUFFER_LOAD_DWORD_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (s32) from %ir.buf, align 1, addrspace 8)139 ; GFX9-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]140 ; GFX9-NEXT: SI_RETURN implicit $vgpr0141 %ret = call ptr addrspace(5) @llvm.amdgcn.raw.ptr.buffer.load.p5(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)142 ret ptr addrspace(5) %ret143}144 145define void @buffer_store_p5(ptr addrspace(5) %data, ptr addrspace(8) inreg %buf) {146 ; GFX9-LABEL: name: buffer_store_p5147 ; GFX9: bb.1 (%ir-block.0):148 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0149 ; GFX9-NEXT: {{ $}}150 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0151 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr16152 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr17153 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr18154 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr19155 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0156 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3157 ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (s32) into %ir.buf, align 1, addrspace 8)158 ; GFX9-NEXT: SI_RETURN159 call void @llvm.amdgcn.raw.ptr.buffer.store.p5(ptr addrspace(5) %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)160 ret void161}162 163define <2 x ptr addrspace(1)> @buffer_load_v2p1(ptr addrspace(8) inreg %buf) {164 ; GFX9-LABEL: name: buffer_load_v2p1165 ; GFX9: bb.1 (%ir-block.0):166 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19167 ; GFX9-NEXT: {{ $}}168 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr16169 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr17170 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18171 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr19172 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0173 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3174 ; GFX9-NEXT: [[BUFFER_LOAD_DWORDX4_OFFSET:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x s64>) from %ir.buf, align 1, addrspace 8)175 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub0176 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub1177 ; GFX9-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub2178 ; GFX9-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub3179 ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]]180 ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]]181 ; GFX9-NEXT: $vgpr2 = COPY [[COPY6]]182 ; GFX9-NEXT: $vgpr3 = COPY [[COPY7]]183 ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3184 %ret = call <2 x ptr addrspace(1)> @llvm.amdgcn.raw.ptr.buffer.load.v2p1(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)185 ret <2 x ptr addrspace(1)> %ret186}187 188define void @buffer_store_v2p5(<2 x ptr addrspace(1)> %data, ptr addrspace(8) inreg %buf) {189 ; GFX9-LABEL: name: buffer_store_v2p5190 ; GFX9: bb.1 (%ir-block.0):191 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0, $vgpr1, $vgpr2, $vgpr3192 ; GFX9-NEXT: {{ $}}193 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0194 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1195 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2196 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3197 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1198 ; GFX9-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1199 ; GFX9-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3200 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr16201 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr17202 ; GFX9-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr18203 ; GFX9-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr19204 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0205 ; GFX9-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3206 ; GFX9-NEXT: BUFFER_STORE_DWORDX4_OFFSET_exact [[REG_SEQUENCE2]], [[REG_SEQUENCE3]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x s64>) into %ir.buf, align 1, addrspace 8)207 ; GFX9-NEXT: SI_RETURN208 call void @llvm.amdgcn.raw.ptr.buffer.store.v2p1(<2 x ptr addrspace(1)> %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)209 ret void210}211 212define <3 x ptr addrspace(5)> @buffer_load_v3p5(ptr addrspace(8) inreg %buf) {213 ; GFX9-LABEL: name: buffer_load_v3p5214 ; GFX9: bb.1 (%ir-block.0):215 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19216 ; GFX9-NEXT: {{ $}}217 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr16218 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr17219 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18220 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr19221 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0222 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3223 ; GFX9-NEXT: [[BUFFER_LOAD_DWORDX3_OFFSET:%[0-9]+]]:vreg_96_align2 = BUFFER_LOAD_DWORDX3_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x s32>) from %ir.buf, align 1, addrspace 8)224 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFSET]].sub0225 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFSET]].sub1226 ; GFX9-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_OFFSET]].sub2227 ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]]228 ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]]229 ; GFX9-NEXT: $vgpr2 = COPY [[COPY6]]230 ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2231 %ret = call <3 x ptr addrspace(5)> @llvm.amdgcn.raw.ptr.buffer.load.v3p5(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)232 ret <3 x ptr addrspace(5)> %ret233}234 235define void @buffer_store_v3p5(<3 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %buf) {236 ; GFX9-LABEL: name: buffer_store_v3p5237 ; GFX9: bb.1 (%ir-block.0):238 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0, $vgpr1, $vgpr2239 ; GFX9-NEXT: {{ $}}240 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0241 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1242 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2243 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2244 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr16245 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr17246 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr18247 ; GFX9-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr19248 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0249 ; GFX9-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3250 ; GFX9-NEXT: BUFFER_STORE_DWORDX3_OFFSET_exact [[REG_SEQUENCE]], [[REG_SEQUENCE1]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x s32>) into %ir.buf, align 1, addrspace 8)251 ; GFX9-NEXT: SI_RETURN252 call void @llvm.amdgcn.raw.ptr.buffer.store.v3p5(<3 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)253 ret void254}255 256define <4 x ptr addrspace(5)> @buffer_load_v4p5(ptr addrspace(8) inreg %buf) {257 ; GFX9-LABEL: name: buffer_load_v4p5258 ; GFX9: bb.1 (%ir-block.0):259 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19260 ; GFX9-NEXT: {{ $}}261 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr16262 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr17263 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18264 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr19265 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0266 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3267 ; GFX9-NEXT: [[BUFFER_LOAD_DWORDX4_OFFSET:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_OFFSET [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>) from %ir.buf, align 1, addrspace 8)268 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub0269 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub1270 ; GFX9-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub2271 ; GFX9-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFSET]].sub3272 ; GFX9-NEXT: $vgpr0 = COPY [[COPY4]]273 ; GFX9-NEXT: $vgpr1 = COPY [[COPY5]]274 ; GFX9-NEXT: $vgpr2 = COPY [[COPY6]]275 ; GFX9-NEXT: $vgpr3 = COPY [[COPY7]]276 ; GFX9-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3277 %ret = call <4 x ptr addrspace(5)> @llvm.amdgcn.raw.ptr.buffer.load.v4p5(ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)278 ret <4 x ptr addrspace(5)> %ret279}280 281define void @buffer_store_v4p5(<4 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %buf) {282 ; GFX9-LABEL: name: buffer_store_v4p5283 ; GFX9: bb.1 (%ir-block.0):284 ; GFX9-NEXT: liveins: $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr0, $vgpr1, $vgpr2, $vgpr3285 ; GFX9-NEXT: {{ $}}286 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0287 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1288 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2289 ; GFX9-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3290 ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3291 ; GFX9-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr16292 ; GFX9-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr17293 ; GFX9-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr18294 ; GFX9-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr19295 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0296 ; GFX9-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3297 ; GFX9-NEXT: BUFFER_STORE_DWORDX4_OFFSET_exact [[REG_SEQUENCE]], [[REG_SEQUENCE1]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x s32>) into %ir.buf, align 1, addrspace 8)298 ; GFX9-NEXT: SI_RETURN299 call void @llvm.amdgcn.raw.ptr.buffer.store.v4p5(<4 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %buf, i32 0, i32 0, i32 0)300 ret void301}302