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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s3; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX12 %s4 5define float @test_fmed3_f32_known_nnan_ieee_true(float %a) #0 {6; GFX10-LABEL: test_fmed3_f32_known_nnan_ieee_true:7; GFX10: ; %bb.0:8; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9; GFX10-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp10; GFX10-NEXT: s_setpc_b64 s[30:31]11;12; GFX12-LABEL: test_fmed3_f32_known_nnan_ieee_true:13; GFX12: ; %bb.0:14; GFX12-NEXT: s_wait_loadcnt_dscnt 0x015; GFX12-NEXT: s_wait_expcnt 0x016; GFX12-NEXT: s_wait_samplecnt 0x017; GFX12-NEXT: s_wait_bvhcnt 0x018; GFX12-NEXT: s_wait_kmcnt 0x019; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp20; GFX12-NEXT: s_setpc_b64 s[30:31]21 %fmul = fmul float %a, 2.022 %fmed = call nnan float @llvm.amdgcn.fmed3.f32(float %fmul, float 0.0, float 1.0)23 ret float %fmed24}25 26define half @test_fmed3_f16_known_nnan_ieee_false(half %a) #1 {27; GFX10-LABEL: test_fmed3_f16_known_nnan_ieee_false:28; GFX10: ; %bb.0:29; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)30; GFX10-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp31; GFX10-NEXT: s_setpc_b64 s[30:31]32;33; GFX12-LABEL: test_fmed3_f16_known_nnan_ieee_false:34; GFX12: ; %bb.0:35; GFX12-NEXT: s_wait_loadcnt_dscnt 0x036; GFX12-NEXT: s_wait_expcnt 0x037; GFX12-NEXT: s_wait_samplecnt 0x038; GFX12-NEXT: s_wait_bvhcnt 0x039; GFX12-NEXT: s_wait_kmcnt 0x040; GFX12-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp41; GFX12-NEXT: s_setpc_b64 s[30:31]42 %fmul = fmul half %a, 2.043 %fmed = call nnan half @llvm.amdgcn.fmed3.f16(half %fmul, half 0.0, half 1.0)44 ret half %fmed45}46 47; %fmin is known non-SNaN because fmin inputs are fcanonicalized48define float @test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true(float %a) #2 {49; GFX10-LABEL: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true:50; GFX10: ; %bb.0:51; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)52; GFX10-NEXT: v_max_f32_e32 v0, v0, v053; GFX10-NEXT: v_min_f32_e64 v0, 0x41200000, v0 clamp54; GFX10-NEXT: s_setpc_b64 s[30:31]55;56; GFX12-LABEL: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true:57; GFX12: ; %bb.0:58; GFX12-NEXT: s_wait_loadcnt_dscnt 0x059; GFX12-NEXT: s_wait_expcnt 0x060; GFX12-NEXT: s_wait_samplecnt 0x061; GFX12-NEXT: s_wait_bvhcnt 0x062; GFX12-NEXT: s_wait_kmcnt 0x063; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v064; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)65; GFX12-NEXT: v_min_num_f32_e64 v0, 0x41200000, v0 clamp66; GFX12-NEXT: s_setpc_b64 s[30:31]67 %fmin = call float @llvm.minnum.f32(float %a, float 10.0)68 %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmin, float 0.0, float 1.0)69 ret float %fmed70}71 72; input may be SNaN. It's safe to clamp since third operand in fmed3 is 0.073define float @test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp_true(float %a) #2 {74; GFX10-LABEL: test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp_true:75; GFX10: ; %bb.0:76; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)77; GFX10-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp78; GFX10-NEXT: s_setpc_b64 s[30:31]79;80; GFX12-LABEL: test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp_true:81; GFX12: ; %bb.0:82; GFX12-NEXT: s_wait_loadcnt_dscnt 0x083; GFX12-NEXT: s_wait_expcnt 0x084; GFX12-NEXT: s_wait_samplecnt 0x085; GFX12-NEXT: s_wait_bvhcnt 0x086; GFX12-NEXT: s_wait_kmcnt 0x087; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp88; GFX12-NEXT: s_setpc_b64 s[30:31]89 %fmul = fmul float %a, 2.090 %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmul, float 1.0, float 0.0)91 ret float %fmed92}93 94; global nnan function attribute always forces clamp combine95 96define float @test_fmed3_global_nnan(float %a) #3 {97; GFX10-LABEL: test_fmed3_global_nnan:98; GFX10: ; %bb.0:99; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)100; GFX10-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp101; GFX10-NEXT: s_setpc_b64 s[30:31]102;103; GFX12-LABEL: test_fmed3_global_nnan:104; GFX12: ; %bb.0:105; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0106; GFX12-NEXT: s_wait_expcnt 0x0107; GFX12-NEXT: s_wait_samplecnt 0x0108; GFX12-NEXT: s_wait_bvhcnt 0x0109; GFX12-NEXT: s_wait_kmcnt 0x0110; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp111; GFX12-NEXT: s_setpc_b64 s[30:31]112 %fmul = fmul float %a, 2.0113 %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmul, float 0.0, float 1.0)114 ret float %fmed115}116 117; ------------------------------------------------------------------------------118; Negative patterns119; ------------------------------------------------------------------------------120 121; ieee=false requires known never NaN input122define float @test_fmed3_f32_maybe_NaN_ieee_false(float %a) #1 {123; GFX10-LABEL: test_fmed3_f32_maybe_NaN_ieee_false:124; GFX10: ; %bb.0:125; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)126; GFX10-NEXT: v_mul_f32_e32 v0, 2.0, v0127; GFX10-NEXT: v_med3_f32 v0, v0, 1.0, 0128; GFX10-NEXT: s_setpc_b64 s[30:31]129;130; GFX12-LABEL: test_fmed3_f32_maybe_NaN_ieee_false:131; GFX12: ; %bb.0:132; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0133; GFX12-NEXT: s_wait_expcnt 0x0134; GFX12-NEXT: s_wait_samplecnt 0x0135; GFX12-NEXT: s_wait_bvhcnt 0x0136; GFX12-NEXT: s_wait_kmcnt 0x0137; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp138; GFX12-NEXT: s_setpc_b64 s[30:31]139 %fmul = fmul float %a, 2.0140 %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmul, float 1.0, float 0.0)141 ret float %fmed142}143 144; ieee=true input is known non-SNaN but dx10_clamp=false145define float @test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false(float %a) #4 {146; GFX10-LABEL: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false:147; GFX10: ; %bb.0:148; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)149; GFX10-NEXT: v_max_f32_e32 v0, v0, v0150; GFX10-NEXT: v_min_f32_e32 v0, 0x41200000, v0151; GFX10-NEXT: v_med3_f32 v0, v0, 0, 1.0152; GFX10-NEXT: s_setpc_b64 s[30:31]153;154; GFX12-LABEL: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false:155; GFX12: ; %bb.0:156; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0157; GFX12-NEXT: s_wait_expcnt 0x0158; GFX12-NEXT: s_wait_samplecnt 0x0159; GFX12-NEXT: s_wait_bvhcnt 0x0160; GFX12-NEXT: s_wait_kmcnt 0x0161; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0162; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)163; GFX12-NEXT: v_min_num_f32_e64 v0, 0x41200000, v0 clamp164; GFX12-NEXT: s_setpc_b64 s[30:31]165 %fmin = call float @llvm.minnum.f32(float %a, float 10.0)166 %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmin, float 0.0, float 1.0)167 ret float %fmed168}169 170; ieee=true dx10_clamp=true but input may be SNaN, clamp requires third operand in fmed3 to be 0.0171define float @test_fmed3_maybe_SNaN_input_ieee_true_dx10clamp_true(float %a) #2 {172; GFX10-LABEL: test_fmed3_maybe_SNaN_input_ieee_true_dx10clamp_true:173; GFX10: ; %bb.0:174; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)175; GFX10-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp176; GFX10-NEXT: s_setpc_b64 s[30:31]177;178; GFX12-LABEL: test_fmed3_maybe_SNaN_input_ieee_true_dx10clamp_true:179; GFX12: ; %bb.0:180; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0181; GFX12-NEXT: s_wait_expcnt 0x0182; GFX12-NEXT: s_wait_samplecnt 0x0183; GFX12-NEXT: s_wait_bvhcnt 0x0184; GFX12-NEXT: s_wait_kmcnt 0x0185; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp186; GFX12-NEXT: s_setpc_b64 s[30:31]187 %fmul = fmul float %a, 2.0188 %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmul, float 0.0, float 1.0)189 ret float %fmed190}191 192declare half @llvm.amdgcn.fmed3.f16(half, half, half)193declare float @llvm.amdgcn.fmed3.f32(float, float, float)194declare float @llvm.minnum.f32(float, float)195 196attributes #0 = {"amdgpu-ieee"="true"}197attributes #1 = {"amdgpu-ieee"="false"}198attributes #2 = {"amdgpu-ieee"="true" "amdgpu-dx10-clamp"="true"}199attributes #3 = {"no-nans-fp-math"="true"}200attributes #4 = {"amdgpu-ieee"="true" "amdgpu-dx10-clamp"="false"}201