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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: narrow_ashr_s64_32_s64amt6tracksRegLiveness: true7body: |8 bb.0:9 liveins: $vgpr0_vgpr110 11 ; CHECK-LABEL: name: narrow_ashr_s64_32_s64amt12 ; CHECK: liveins: $vgpr0_vgpr113 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr115 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)16 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3117 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)18 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[ASHR]](s32)19 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)20 %0:_(s64) = COPY $vgpr0_vgpr121 %1:_(s64) = G_CONSTANT i64 3222 %2:_(s64) = G_ASHR %0, %123 $vgpr0_vgpr1 = COPY %224...25 26---27name: narrow_ashr_s64_3228tracksRegLiveness: true29body: |30 bb.0:31 liveins: $vgpr0_vgpr132 33 ; CHECK-LABEL: name: narrow_ashr_s64_3234 ; CHECK: liveins: $vgpr0_vgpr135 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr137 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)38 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3139 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)40 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[ASHR]](s32)41 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)42 %0:_(s64) = COPY $vgpr0_vgpr143 %1:_(s32) = G_CONSTANT i32 3244 %2:_(s64) = G_ASHR %0, %145 $vgpr0_vgpr1 = COPY %246...47 48---49name: narrow_ashr_s64_3350tracksRegLiveness: true51body: |52 bb.0:53 liveins: $vgpr0_vgpr154 55 ; CHECK-LABEL: name: narrow_ashr_s64_3356 ; CHECK: liveins: $vgpr0_vgpr157 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr159 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)60 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3161 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)62 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 163 ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C1]](s32)64 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR1]](s32), [[ASHR]](s32)65 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)66 %0:_(s64) = COPY $vgpr0_vgpr167 %1:_(s32) = G_CONSTANT i32 3368 %2:_(s64) = G_ASHR %0, %169 $vgpr0_vgpr1 = COPY %270...71 72---73name: narrow_ashr_s64_3174tracksRegLiveness: true75body: |76 bb.0:77 liveins: $vgpr0_vgpr178 79 ; CHECK-LABEL: name: narrow_ashr_s64_3180 ; CHECK: liveins: $vgpr0_vgpr181 ; CHECK-NEXT: {{ $}}82 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr183 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3184 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)85 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](s64)86 %0:_(s64) = COPY $vgpr0_vgpr187 %1:_(s32) = G_CONSTANT i32 3188 %2:_(s64) = G_ASHR %0, %189 $vgpr0_vgpr1 = COPY %290...91 92---93name: narrow_ashr_s64_6394tracksRegLiveness: true95body: |96 bb.0:97 liveins: $vgpr0_vgpr198 99 ; CHECK-LABEL: name: narrow_ashr_s64_63100 ; CHECK: liveins: $vgpr0_vgpr1101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1103 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)104 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31105 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)106 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)107 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)108 %0:_(s64) = COPY $vgpr0_vgpr1109 %1:_(s32) = G_CONSTANT i32 63110 %2:_(s64) = G_ASHR %0, %1111 $vgpr0_vgpr1 = COPY %2112...113 114---115name: narrow_ashr_s64_64116tracksRegLiveness: true117body: |118 bb.0:119 liveins: $vgpr0_vgpr1120 121 ; CHECK-LABEL: name: narrow_ashr_s64_64122 ; CHECK: liveins: $vgpr0_vgpr1123 ; CHECK-NEXT: {{ $}}124 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF125 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[DEF]](s64)126 %0:_(s64) = COPY $vgpr0_vgpr1127 %1:_(s32) = G_CONSTANT i32 64128 %2:_(s64) = G_ASHR %0, %1129 $vgpr0_vgpr1 = COPY %2130...131 132---133name: narrow_ashr_s64_65134tracksRegLiveness: true135body: |136 bb.0:137 liveins: $vgpr0_vgpr1138 139 ; CHECK-LABEL: name: narrow_ashr_s64_65140 ; CHECK: liveins: $vgpr0_vgpr1141 ; CHECK-NEXT: {{ $}}142 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF143 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[DEF]](s64)144 %0:_(s64) = COPY $vgpr0_vgpr1145 %1:_(s32) = G_CONSTANT i32 65146 %2:_(s64) = G_ASHR %0, %1147 $vgpr0_vgpr1 = COPY %2148...149 150---151name: narrow_ashr_s32_16152tracksRegLiveness: true153body: |154 bb.0:155 liveins: $vgpr0156 157 ; CHECK-LABEL: name: narrow_ashr_s32_16158 ; CHECK: liveins: $vgpr0159 ; CHECK-NEXT: {{ $}}160 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0161 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16162 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)163 ; CHECK-NEXT: $vgpr0 = COPY [[ASHR]](s32)164 %0:_(s32) = COPY $vgpr0165 %1:_(s32) = G_CONSTANT i32 16166 %2:_(s32) = G_ASHR %0, %1167 $vgpr0 = COPY %2168...169 170---171name: narrow_ashr_s32_17172tracksRegLiveness: true173body: |174 bb.0:175 liveins: $vgpr0176 177 ; CHECK-LABEL: name: narrow_ashr_s32_17178 ; CHECK: liveins: $vgpr0179 ; CHECK-NEXT: {{ $}}180 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0181 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17182 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)183 ; CHECK-NEXT: $vgpr0 = COPY [[ASHR]](s32)184 %0:_(s32) = COPY $vgpr0185 %1:_(s32) = G_CONSTANT i32 17186 %2:_(s32) = G_ASHR %0, %1187 $vgpr0 = COPY %2188...189 190---191name: narrow_ashr_v2s32_17192tracksRegLiveness: true193body: |194 bb.0:195 liveins: $vgpr0_vgpr1196 197 ; CHECK-LABEL: name: narrow_ashr_v2s32_17198 ; CHECK: liveins: $vgpr0_vgpr1199 ; CHECK-NEXT: {{ $}}200 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1201 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17202 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)203 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<2 x s32>) = G_ASHR [[COPY]], [[BUILD_VECTOR]](<2 x s32>)204 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ASHR]](<2 x s32>)205 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1206 %1:_(s32) = G_CONSTANT i32 17207 %2:_(<2 x s32>) = G_BUILD_VECTOR %1, %1208 %3:_(<2 x s32>) = G_ASHR %0, %2209 $vgpr0_vgpr1 = COPY %3210...211