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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -fp-contract=fast < %s | FileCheck -check-prefix=GFX10-CONTRACT %s5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s6 7; fold (fadd (fma x, y, (fpext (fmul u, v))), z) -> (fma x, y, (fma (fpext u), (fpext v), z))8define amdgpu_vs float @test_f16_f32_add_fma_ext_mul(float %x, float %y, float %z, half %u, half %v) {9; GFX9-DENORM-LABEL: test_f16_f32_add_fma_ext_mul:10; GFX9-DENORM: ; %bb.0: ; %.entry11; GFX9-DENORM-NEXT: v_mad_mix_f32 v2, v3, v4, v2 op_sel_hi:[1,1,0]12; GFX9-DENORM-NEXT: v_mac_f32_e32 v2, v0, v113; GFX9-DENORM-NEXT: v_mov_b32_e32 v0, v214; GFX9-DENORM-NEXT: ; return to shader part epilog15;16; GFX10-LABEL: test_f16_f32_add_fma_ext_mul:17; GFX10: ; %bb.0: ; %.entry18; GFX10-NEXT: v_mul_f16_e32 v3, v3, v419; GFX10-NEXT: v_fma_mix_f32 v0, v0, v1, v3 op_sel_hi:[0,0,1]20; GFX10-NEXT: v_add_f32_e32 v0, v0, v221; GFX10-NEXT: ; return to shader part epilog22;23; GFX10-CONTRACT-LABEL: test_f16_f32_add_fma_ext_mul:24; GFX10-CONTRACT: ; %bb.0: ; %.entry25; GFX10-CONTRACT-NEXT: v_mul_f16_e32 v3, v3, v426; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v0, v1, v3 op_sel_hi:[0,0,1]27; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v228; GFX10-CONTRACT-NEXT: ; return to shader part epilog29;30; GFX10-DENORM-LABEL: test_f16_f32_add_fma_ext_mul:31; GFX10-DENORM: ; %bb.0: ; %.entry32; GFX10-DENORM-NEXT: v_mul_f16_e32 v3, v3, v433; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, v1, v3 op_sel_hi:[0,0,1]34; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v235; GFX10-DENORM-NEXT: ; return to shader part epilog36.entry:37 %a = fmul half %u, %v38 %b = fpext half %a to float39 %c = call float @llvm.fmuladd.f32(float %x, float %y, float %b)40 %d = fadd float %c, %z41 ret float %d42}43 44; fold (fadd (fpext (fma x, y, (fmul u, v))), z) -> (fma (fpext x), (fpext y), (fma (fpext u), (fpext v), z))45define amdgpu_vs float @test_f16_f32_add_ext_fma_mul(half %x, half %y, float %z, half %u, half %v) {46; GFX9-DENORM-LABEL: test_f16_f32_add_ext_fma_mul:47; GFX9-DENORM: ; %bb.0: ; %.entry48; GFX9-DENORM-NEXT: v_mad_mix_f32 v2, v3, v4, v2 op_sel_hi:[1,1,0]49; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]50; GFX9-DENORM-NEXT: ; return to shader part epilog51;52; GFX10-LABEL: test_f16_f32_add_ext_fma_mul:53; GFX10: ; %bb.0: ; %.entry54; GFX10-NEXT: v_mul_f16_e32 v3, v3, v455; GFX10-NEXT: v_fmac_f16_e32 v3, v0, v156; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v357; GFX10-NEXT: v_add_f32_e32 v0, v0, v258; GFX10-NEXT: ; return to shader part epilog59;60; GFX10-CONTRACT-LABEL: test_f16_f32_add_ext_fma_mul:61; GFX10-CONTRACT: ; %bb.0: ; %.entry62; GFX10-CONTRACT-NEXT: v_mul_f16_e32 v3, v3, v463; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v3, v0, v164; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v0, v365; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v266; GFX10-CONTRACT-NEXT: ; return to shader part epilog67;68; GFX10-DENORM-LABEL: test_f16_f32_add_ext_fma_mul:69; GFX10-DENORM: ; %bb.0: ; %.entry70; GFX10-DENORM-NEXT: v_mul_f16_e32 v3, v3, v471; GFX10-DENORM-NEXT: v_mul_f16_e32 v0, v0, v172; GFX10-DENORM-NEXT: v_add_f16_e32 v0, v0, v373; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v074; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v275; GFX10-DENORM-NEXT: ; return to shader part epilog76.entry:77 %a = fmul half %u, %v78 %b = call half @llvm.fmuladd.f16(half %x, half %y, half %a)79 %c = fpext half %b to float80 %d = fadd float %c, %z81 ret float %d82}83 84; fold (fadd x, (fma y, z, (fpext (fmul u, v))) -> (fma y, z, (fma (fpext u), (fpext v), x))85define amdgpu_vs float @test_f16_f32_add_fma_ext_mul_rhs(float %x, float %y, float %z, half %u, half %v) {86; GFX9-DENORM-LABEL: test_f16_f32_add_fma_ext_mul_rhs:87; GFX9-DENORM: ; %bb.0: ; %.entry88; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v3, v4, v0 op_sel_hi:[1,1,0]89; GFX9-DENORM-NEXT: v_mac_f32_e32 v0, v1, v290; GFX9-DENORM-NEXT: ; return to shader part epilog91;92; GFX10-LABEL: test_f16_f32_add_fma_ext_mul_rhs:93; GFX10: ; %bb.0: ; %.entry94; GFX10-NEXT: v_mul_f16_e32 v3, v3, v495; GFX10-NEXT: v_fma_mix_f32 v1, v1, v2, v3 op_sel_hi:[0,0,1]96; GFX10-NEXT: v_add_f32_e32 v0, v0, v197; GFX10-NEXT: ; return to shader part epilog98;99; GFX10-CONTRACT-LABEL: test_f16_f32_add_fma_ext_mul_rhs:100; GFX10-CONTRACT: ; %bb.0: ; %.entry101; GFX10-CONTRACT-NEXT: v_mul_f16_e32 v3, v3, v4102; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v1, v1, v2, v3 op_sel_hi:[0,0,1]103; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v1104; GFX10-CONTRACT-NEXT: ; return to shader part epilog105;106; GFX10-DENORM-LABEL: test_f16_f32_add_fma_ext_mul_rhs:107; GFX10-DENORM: ; %bb.0: ; %.entry108; GFX10-DENORM-NEXT: v_mul_f16_e32 v3, v3, v4109; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, v1, v2, v3 op_sel_hi:[0,0,1]110; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v1111; GFX10-DENORM-NEXT: ; return to shader part epilog112.entry:113 %a = fmul half %u, %v114 %b = fpext half %a to float115 %c = call float @llvm.fmuladd.f32(float %y, float %z, float %b)116 %d = fadd float %x, %c117 ret float %d118}119 120; fold (fadd x, (fpext (fma y, z, (fmul u, v))) -> (fma (fpext y), (fpext z), (fma (fpext u), (fpext v), x))121define amdgpu_vs float @test_f16_f32_add_ext_fma_mul_rhs(float %x, half %y, half %z, half %u, half %v) {122; GFX9-DENORM-LABEL: test_f16_f32_add_ext_fma_mul_rhs:123; GFX9-DENORM: ; %bb.0: ; %.entry124; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v3, v4, v0 op_sel_hi:[1,1,0]125; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v1, v2, v0 op_sel_hi:[1,1,0]126; GFX9-DENORM-NEXT: ; return to shader part epilog127;128; GFX10-LABEL: test_f16_f32_add_ext_fma_mul_rhs:129; GFX10: ; %bb.0: ; %.entry130; GFX10-NEXT: v_mul_f16_e32 v3, v3, v4131; GFX10-NEXT: v_fmac_f16_e32 v3, v1, v2132; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v3133; GFX10-NEXT: v_add_f32_e32 v0, v0, v1134; GFX10-NEXT: ; return to shader part epilog135;136; GFX10-CONTRACT-LABEL: test_f16_f32_add_ext_fma_mul_rhs:137; GFX10-CONTRACT: ; %bb.0: ; %.entry138; GFX10-CONTRACT-NEXT: v_mul_f16_e32 v3, v3, v4139; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v3, v1, v2140; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v1, v3141; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v1142; GFX10-CONTRACT-NEXT: ; return to shader part epilog143;144; GFX10-DENORM-LABEL: test_f16_f32_add_ext_fma_mul_rhs:145; GFX10-DENORM: ; %bb.0: ; %.entry146; GFX10-DENORM-NEXT: v_mul_f16_e32 v3, v3, v4147; GFX10-DENORM-NEXT: v_mul_f16_e32 v1, v1, v2148; GFX10-DENORM-NEXT: v_add_f16_e32 v1, v1, v3149; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1150; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v1151; GFX10-DENORM-NEXT: ; return to shader part epilog152.entry:153 %a = fmul half %u, %v154 %b = call half @llvm.fmuladd.f16(half %y, half %z, half %a)155 %c = fpext half %b to float156 %d = fadd float %x, %c157 ret float %d158}159 160; fold (fadd (fma x, y, (fpext (fmul u, v))), z) -> (fma x, y, (fma (fpext u), (fpext v), z))161define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_fma_ext_mul(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x half> %u, <4 x half> %v) {162; GFX9-DENORM-LABEL: test_v4f16_v4f32_add_fma_ext_mul:163; GFX9-DENORM: ; %bb.0: ; %.entry164; GFX9-DENORM-NEXT: v_pk_mul_f16 v12, v12, v14165; GFX9-DENORM-NEXT: v_pk_mul_f16 v13, v13, v15166; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v0, v4, v12 op_sel_hi:[0,0,1]167; GFX9-DENORM-NEXT: v_mad_mix_f32 v1, v1, v5, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]168; GFX9-DENORM-NEXT: v_mad_mix_f32 v2, v2, v6, v13 op_sel_hi:[0,0,1]169; GFX9-DENORM-NEXT: v_mad_mix_f32 v3, v3, v7, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]170; GFX9-DENORM-NEXT: v_add_f32_e32 v0, v0, v8171; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v9172; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v2, v10173; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v3, v11174; GFX9-DENORM-NEXT: ; return to shader part epilog175;176; GFX10-LABEL: test_v4f16_v4f32_add_fma_ext_mul:177; GFX10: ; %bb.0: ; %.entry178; GFX10-NEXT: v_pk_mul_f16 v12, v12, v14179; GFX10-NEXT: v_pk_mul_f16 v13, v13, v15180; GFX10-NEXT: v_fma_mix_f32 v0, v0, v4, v12 op_sel_hi:[0,0,1]181; GFX10-NEXT: v_fma_mix_f32 v1, v1, v5, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]182; GFX10-NEXT: v_fma_mix_f32 v2, v2, v6, v13 op_sel_hi:[0,0,1]183; GFX10-NEXT: v_fma_mix_f32 v3, v3, v7, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]184; GFX10-NEXT: v_add_f32_e32 v0, v0, v8185; GFX10-NEXT: v_add_f32_e32 v1, v1, v9186; GFX10-NEXT: v_add_f32_e32 v2, v2, v10187; GFX10-NEXT: v_add_f32_e32 v3, v3, v11188; GFX10-NEXT: ; return to shader part epilog189;190; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_fma_ext_mul:191; GFX10-CONTRACT: ; %bb.0: ; %.entry192; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v12, v12, v14193; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v13, v13, v15194; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v0, v4, v12 op_sel_hi:[0,0,1]195; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v1, v1, v5, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]196; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v2, v2, v6, v13 op_sel_hi:[0,0,1]197; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v3, v3, v7, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]198; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v8199; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v1, v9200; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v2, v10201; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v3, v11202; GFX10-CONTRACT-NEXT: ; return to shader part epilog203;204; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_fma_ext_mul:205; GFX10-DENORM: ; %bb.0: ; %.entry206; GFX10-DENORM-NEXT: v_pk_mul_f16 v12, v12, v14207; GFX10-DENORM-NEXT: v_pk_mul_f16 v13, v13, v15208; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, v4, v12 op_sel_hi:[0,0,1]209; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, v1, v5, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]210; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v2, v6, v13 op_sel_hi:[0,0,1]211; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v3, v7, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]212; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v8213; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v9214; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v2, v10215; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v3, v11216; GFX10-DENORM-NEXT: ; return to shader part epilog217.entry:218 %a = fmul <4 x half> %u, %v219 %b = fpext <4 x half> %a to <4 x float>220 %c = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %b)221 %d = fadd <4 x float> %c, %z222 ret <4 x float> %d223}224 225; fold (fadd (fpext (fma x, y, (fmul u, v))), z) -> (fma (fpext x), (fpext y), (fma (fpext u), (fpext v), z))226define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_ext_fma_mul(<4 x half> %x, <4 x half> %y, <4 x float> %z, <4 x half> %u, <4 x half> %v) {227; GFX9-DENORM-LABEL: test_v4f16_v4f32_add_ext_fma_mul:228; GFX9-DENORM: ; %bb.0: ; %.entry229; GFX9-DENORM-NEXT: v_pk_mul_f16 v8, v8, v10230; GFX9-DENORM-NEXT: v_pk_mul_f16 v9, v9, v11231; GFX9-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2232; GFX9-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3233; GFX9-DENORM-NEXT: v_pk_add_f16 v0, v0, v8234; GFX9-DENORM-NEXT: v_pk_add_f16 v1, v1, v9235; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v0236; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1237; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v1238; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1239; GFX9-DENORM-NEXT: v_add_f32_e32 v0, v2, v4240; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v3, v5241; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v8, v6242; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v9, v7243; GFX9-DENORM-NEXT: ; return to shader part epilog244;245; GFX10-LABEL: test_v4f16_v4f32_add_ext_fma_mul:246; GFX10: ; %bb.0: ; %.entry247; GFX10-NEXT: v_pk_mul_f16 v8, v8, v10248; GFX10-NEXT: v_pk_mul_f16 v9, v9, v11249; GFX10-NEXT: v_pk_fma_f16 v0, v0, v2, v8250; GFX10-NEXT: v_pk_fma_f16 v1, v1, v3, v9251; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0252; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1253; GFX10-NEXT: v_cvt_f32_f16_e32 v8, v1254; GFX10-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1255; GFX10-NEXT: v_add_f32_e32 v0, v2, v4256; GFX10-NEXT: v_add_f32_e32 v1, v3, v5257; GFX10-NEXT: v_add_f32_e32 v2, v8, v6258; GFX10-NEXT: v_add_f32_e32 v3, v9, v7259; GFX10-NEXT: ; return to shader part epilog260;261; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_ext_fma_mul:262; GFX10-CONTRACT: ; %bb.0: ; %.entry263; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v8, v8, v10264; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v9, v9, v11265; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v0, v0, v2, v8266; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v1, v1, v3, v9267; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v2, v0268; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1269; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v8, v1270; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1271; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v2, v4272; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v3, v5273; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v8, v6274; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v9, v7275; GFX10-CONTRACT-NEXT: ; return to shader part epilog276;277; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_ext_fma_mul:278; GFX10-DENORM: ; %bb.0: ; %.entry279; GFX10-DENORM-NEXT: v_pk_mul_f16 v8, v8, v10280; GFX10-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2281; GFX10-DENORM-NEXT: v_pk_mul_f16 v2, v9, v11282; GFX10-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3283; GFX10-DENORM-NEXT: v_pk_add_f16 v0, v0, v8284; GFX10-DENORM-NEXT: v_pk_add_f16 v1, v1, v2285; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v0286; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1287; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v1288; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1289; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v2, v4290; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v3, v5291; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v8, v6292; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v9, v7293; GFX10-DENORM-NEXT: ; return to shader part epilog294.entry:295 %a = fmul <4 x half> %u, %v296 %b = call <4 x half> @llvm.fmuladd.v4f16(<4 x half> %x, <4 x half> %y, <4 x half> %a)297 %c = fpext <4 x half> %b to <4 x float>298 %d = fadd <4 x float> %c, %z299 ret <4 x float> %d300}301 302; fold (fadd x, (fma y, z, (fpext (fmul u, v))) -> (fma y, z, (fma (fpext u), (fpext v), x))303define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_fma_ext_mul_rhs(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x half> %u, <4 x half> %v) {304; GFX9-DENORM-LABEL: test_v4f16_v4f32_add_fma_ext_mul_rhs:305; GFX9-DENORM: ; %bb.0: ; %.entry306; GFX9-DENORM-NEXT: v_pk_mul_f16 v12, v12, v14307; GFX9-DENORM-NEXT: v_pk_mul_f16 v13, v13, v15308; GFX9-DENORM-NEXT: v_mad_mix_f32 v4, v4, v8, v12 op_sel_hi:[0,0,1]309; GFX9-DENORM-NEXT: v_mad_mix_f32 v5, v5, v9, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]310; GFX9-DENORM-NEXT: v_mad_mix_f32 v6, v6, v10, v13 op_sel_hi:[0,0,1]311; GFX9-DENORM-NEXT: v_mad_mix_f32 v7, v7, v11, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]312; GFX9-DENORM-NEXT: v_add_f32_e32 v0, v0, v4313; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v5314; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v2, v6315; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v3, v7316; GFX9-DENORM-NEXT: ; return to shader part epilog317;318; GFX10-LABEL: test_v4f16_v4f32_add_fma_ext_mul_rhs:319; GFX10: ; %bb.0: ; %.entry320; GFX10-NEXT: v_pk_mul_f16 v12, v12, v14321; GFX10-NEXT: v_pk_mul_f16 v13, v13, v15322; GFX10-NEXT: v_fma_mix_f32 v4, v4, v8, v12 op_sel_hi:[0,0,1]323; GFX10-NEXT: v_fma_mix_f32 v5, v5, v9, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]324; GFX10-NEXT: v_fma_mix_f32 v6, v6, v10, v13 op_sel_hi:[0,0,1]325; GFX10-NEXT: v_fma_mix_f32 v7, v7, v11, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]326; GFX10-NEXT: v_add_f32_e32 v0, v0, v4327; GFX10-NEXT: v_add_f32_e32 v1, v1, v5328; GFX10-NEXT: v_add_f32_e32 v2, v2, v6329; GFX10-NEXT: v_add_f32_e32 v3, v3, v7330; GFX10-NEXT: ; return to shader part epilog331;332; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_fma_ext_mul_rhs:333; GFX10-CONTRACT: ; %bb.0: ; %.entry334; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v12, v12, v14335; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v13, v13, v15336; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v4, v4, v8, v12 op_sel_hi:[0,0,1]337; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v5, v5, v9, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]338; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v6, v6, v10, v13 op_sel_hi:[0,0,1]339; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v7, v7, v11, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]340; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v4341; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v1, v5342; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v2, v6343; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v3, v7344; GFX10-CONTRACT-NEXT: ; return to shader part epilog345;346; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_fma_ext_mul_rhs:347; GFX10-DENORM: ; %bb.0: ; %.entry348; GFX10-DENORM-NEXT: v_pk_mul_f16 v12, v12, v14349; GFX10-DENORM-NEXT: v_pk_mul_f16 v13, v13, v15350; GFX10-DENORM-NEXT: v_fma_mix_f32 v4, v4, v8, v12 op_sel_hi:[0,0,1]351; GFX10-DENORM-NEXT: v_fma_mix_f32 v5, v5, v9, v12 op_sel:[0,0,1] op_sel_hi:[0,0,1]352; GFX10-DENORM-NEXT: v_fma_mix_f32 v6, v6, v10, v13 op_sel_hi:[0,0,1]353; GFX10-DENORM-NEXT: v_fma_mix_f32 v7, v7, v11, v13 op_sel:[0,0,1] op_sel_hi:[0,0,1]354; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v4355; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v5356; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v2, v6357; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v3, v7358; GFX10-DENORM-NEXT: ; return to shader part epilog359.entry:360 %a = fmul <4 x half> %u, %v361 %b = fpext <4 x half> %a to <4 x float>362 %c = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y, <4 x float> %z, <4 x float> %b)363 %d = fadd <4 x float> %x, %c364 ret <4 x float> %d365}366 367; fold (fadd x, (fpext (fma y, z, (fmul u, v))) -> (fma (fpext y), (fpext z), (fma (fpext u), (fpext v), x))368define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_ext_fma_mul_rhs(<4 x float> %x, <4 x half> %y, <4 x half> %z, <4 x half> %u, <4 x half> %v) {369; GFX9-DENORM-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs:370; GFX9-DENORM: ; %bb.0: ; %.entry371; GFX9-DENORM-NEXT: v_pk_mul_f16 v8, v8, v10372; GFX9-DENORM-NEXT: v_pk_mul_f16 v9, v9, v11373; GFX9-DENORM-NEXT: v_pk_mul_f16 v4, v4, v6374; GFX9-DENORM-NEXT: v_pk_mul_f16 v5, v5, v7375; GFX9-DENORM-NEXT: v_pk_add_f16 v4, v4, v8376; GFX9-DENORM-NEXT: v_pk_add_f16 v5, v5, v9377; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v6, v4378; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1379; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v5380; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1381; GFX9-DENORM-NEXT: v_add_f32_e32 v0, v0, v6382; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v4383; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v2, v7384; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v3, v5385; GFX9-DENORM-NEXT: ; return to shader part epilog386;387; GFX10-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs:388; GFX10: ; %bb.0: ; %.entry389; GFX10-NEXT: v_pk_mul_f16 v8, v8, v10390; GFX10-NEXT: v_pk_mul_f16 v9, v9, v11391; GFX10-NEXT: v_pk_fma_f16 v4, v4, v6, v8392; GFX10-NEXT: v_pk_fma_f16 v5, v5, v7, v9393; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v4394; GFX10-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1395; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v5396; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1397; GFX10-NEXT: v_add_f32_e32 v0, v0, v6398; GFX10-NEXT: v_add_f32_e32 v1, v1, v4399; GFX10-NEXT: v_add_f32_e32 v2, v2, v7400; GFX10-NEXT: v_add_f32_e32 v3, v3, v5401; GFX10-NEXT: ; return to shader part epilog402;403; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs:404; GFX10-CONTRACT: ; %bb.0: ; %.entry405; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v8, v8, v10406; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v9, v9, v11407; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v4, v4, v6, v8408; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v5, v5, v7, v9409; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v6, v4410; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1411; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v7, v5412; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1413; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v6414; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v1, v4415; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v2, v7416; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v3, v5417; GFX10-CONTRACT-NEXT: ; return to shader part epilog418;419; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs:420; GFX10-DENORM: ; %bb.0: ; %.entry421; GFX10-DENORM-NEXT: v_pk_mul_f16 v8, v8, v10422; GFX10-DENORM-NEXT: v_pk_mul_f16 v4, v4, v6423; GFX10-DENORM-NEXT: v_pk_mul_f16 v6, v9, v11424; GFX10-DENORM-NEXT: v_pk_mul_f16 v5, v5, v7425; GFX10-DENORM-NEXT: v_pk_add_f16 v4, v4, v8426; GFX10-DENORM-NEXT: v_pk_add_f16 v5, v5, v6427; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v6, v4428; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1429; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v5430; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1431; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v6432; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v4433; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v2, v7434; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v3, v5435; GFX10-DENORM-NEXT: ; return to shader part epilog436.entry:437 %a = fmul <4 x half> %u, %v438 %b = call <4 x half> @llvm.fmuladd.v4f16(<4 x half> %y, <4 x half> %z, <4 x half> %a)439 %c = fpext <4 x half> %b to <4 x float>440 %d = fadd <4 x float> %x, %c441 ret <4 x float> %d442}443 444define amdgpu_ps float @test_matching_source_from_unmerge(ptr addrspace(3) %aptr, float %b) {445; GFX9-DENORM-LABEL: test_matching_source_from_unmerge:446; GFX9-DENORM: ; %bb.0: ; %.entry447; GFX9-DENORM-NEXT: ds_read_b64 v[2:3], v0448; GFX9-DENORM-NEXT: s_waitcnt lgkmcnt(0)449; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v2, v3, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]450; GFX9-DENORM-NEXT: ; return to shader part epilog451;452; GFX10-LABEL: test_matching_source_from_unmerge:453; GFX10: ; %bb.0: ; %.entry454; GFX10-NEXT: ds_read_b64 v[2:3], v0455; GFX10-NEXT: s_waitcnt lgkmcnt(0)456; GFX10-NEXT: v_fma_mix_f32 v0, v2, v3, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]457; GFX10-NEXT: ; return to shader part epilog458;459; GFX10-CONTRACT-LABEL: test_matching_source_from_unmerge:460; GFX10-CONTRACT: ; %bb.0: ; %.entry461; GFX10-CONTRACT-NEXT: ds_read_b64 v[2:3], v0462; GFX10-CONTRACT-NEXT: s_waitcnt lgkmcnt(0)463; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v2, v3, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]464; GFX10-CONTRACT-NEXT: ; return to shader part epilog465;466; GFX10-DENORM-LABEL: test_matching_source_from_unmerge:467; GFX10-DENORM: ; %bb.0: ; %.entry468; GFX10-DENORM-NEXT: ds_read_b64 v[2:3], v0469; GFX10-DENORM-NEXT: s_waitcnt lgkmcnt(0)470; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v2, v3, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]471; GFX10-DENORM-NEXT: ; return to shader part epilog472.entry:473 %a = load <4 x half>, ptr addrspace(3) %aptr, align 16474 %a_f32 = fpext <4 x half> %a to <4 x float>475 %.a3_f32 = extractelement <4 x float> %a_f32, i64 3476 %.a1_f32 = extractelement <4 x float> %a_f32, i64 1477 %res = call float @llvm.fmuladd.f32(float %.a1_f32, float %.a3_f32, float %b)478 ret float %res479}480 481declare float @llvm.fmuladd.f32(float, float, float) #0482declare half @llvm.fmuladd.f16(half, half, half) #0483declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0484declare <4 x half> @llvm.fmuladd.v4f16(<4 x half>, <4 x half>, <4 x half>) #0485 486attributes #0 = { nounwind readnone }487