888 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK4 5---6name: test_fminnum7body: |8 bb.0:9 liveins: $vgpr0, $vgpr110 11 ; CHECK-LABEL: name: test_fminnum12 ; CHECK: liveins: $vgpr0, $vgpr113 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr015 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr116 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]17 ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]18 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[FNEG]], [[FNEG1]]19 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)20 %0:_(s32) = COPY $vgpr021 %1:_(s32) = COPY $vgpr122 %2:_(s32) = G_FMINNUM %0, %123 %3:_(s32) = G_FNEG %224 $vgpr0 = COPY %3(s32)25 26...27---28name: test_fmaxnum29body: |30 bb.0:31 liveins: $vgpr0, $vgpr132 33 ; CHECK-LABEL: name: test_fmaxnum34 ; CHECK: liveins: $vgpr0, $vgpr135 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr037 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr138 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]39 ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]40 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[FNEG]], [[FNEG1]]41 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)42 %0:_(s32) = COPY $vgpr043 %1:_(s32) = COPY $vgpr144 %2:_(s32) = G_FMAXNUM %0, %145 %3:_(s32) = G_FNEG %246 $vgpr0 = COPY %3(s32)47 48...49---50name: test_fminnum_ieee51body: |52 bb.0:53 liveins: $vgpr0, $vgpr154 55 ; CHECK-LABEL: name: test_fminnum_ieee56 ; CHECK: liveins: $vgpr0, $vgpr157 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr059 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr160 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]61 ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]62 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FNEG]], [[FNEG1]]63 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)64 %0:_(s32) = COPY $vgpr065 %1:_(s32) = COPY $vgpr166 %2:_(s32) = G_FMINNUM_IEEE %0, %167 %3:_(s32) = G_FNEG %268 $vgpr0 = COPY %3(s32)69 70...71---72name: test_fmaxnum_ieee73body: |74 bb.0:75 liveins: $vgpr0, $vgpr176 77 ; CHECK-LABEL: name: test_fmaxnum_ieee78 ; CHECK: liveins: $vgpr0, $vgpr179 ; CHECK-NEXT: {{ $}}80 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr081 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr182 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]83 ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]84 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FNEG]], [[FNEG1]]85 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)86 %0:_(s32) = COPY $vgpr087 %1:_(s32) = COPY $vgpr188 %2:_(s32) = G_FMAXNUM_IEEE %0, %189 %3:_(s32) = G_FNEG %290 $vgpr0 = COPY %3(s32)91 92...93---94name: test_amdgpu_fmin_legacy95body: |96 bb.0:97 liveins: $vgpr0, $vgpr198 99 ; CHECK-LABEL: name: test_amdgpu_fmin_legacy100 ; CHECK: liveins: $vgpr0, $vgpr1101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0103 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1104 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]105 ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]106 ; CHECK-NEXT: [[AMDGPU_FMAX_LEGACY:%[0-9]+]]:_(s32) = G_AMDGPU_FMAX_LEGACY [[FNEG]], [[FNEG1]]107 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMAX_LEGACY]](s32)108 %0:_(s32) = COPY $vgpr0109 %1:_(s32) = COPY $vgpr1110 %2:_(s32) = G_AMDGPU_FMIN_LEGACY %0, %1111 %3:_(s32) = G_FNEG %2112 $vgpr0 = COPY %3(s32)113 114...115---116name: test_amdgpu_fmax_legacy117body: |118 bb.0:119 liveins: $vgpr0, $vgpr1120 121 ; CHECK-LABEL: name: test_amdgpu_fmax_legacy122 ; CHECK: liveins: $vgpr0, $vgpr1123 ; CHECK-NEXT: {{ $}}124 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0125 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1126 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]127 ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]128 ; CHECK-NEXT: [[AMDGPU_FMIN_LEGACY:%[0-9]+]]:_(s32) = G_AMDGPU_FMIN_LEGACY [[FNEG]], [[FNEG1]]129 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMIN_LEGACY]](s32)130 %0:_(s32) = COPY $vgpr0131 %1:_(s32) = COPY $vgpr1132 %2:_(s32) = G_AMDGPU_FMAX_LEGACY %0, %1133 %3:_(s32) = G_FNEG %2134 $vgpr0 = COPY %3(s32)135 136...137---138name: test_fadd139body: |140 bb.0:141 liveins: $vgpr0, $vgpr1142 143 ; CHECK-LABEL: name: test_fadd144 ; CHECK: liveins: $vgpr0, $vgpr1145 ; CHECK-NEXT: {{ $}}146 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0147 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1148 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]149 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[FNEG]], [[COPY1]]150 ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)151 %0:_(s32) = COPY $vgpr0152 %1:_(s32) = COPY $vgpr1153 %2:_(s32) = nsz G_FADD %0, %1154 %3:_(s32) = G_FNEG %2155 $vgpr0 = COPY %3(s32)156 157...158---159name: test_fsub160body: |161 bb.0:162 liveins: $vgpr0, $vgpr1163 164 ; CHECK-LABEL: name: test_fsub165 ; CHECK: liveins: $vgpr0, $vgpr1166 ; CHECK-NEXT: {{ $}}167 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0168 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1169 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[COPY1]], [[COPY]]170 ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32)171 %0:_(s32) = COPY $vgpr0172 %1:_(s32) = COPY $vgpr1173 %2:_(s32) = nsz G_FSUB %0, %1174 %3:_(s32) = G_FNEG %2175 $vgpr0 = COPY %3(s32)176 177...178---179name: test_fma180body: |181 bb.0:182 liveins: $vgpr0, $vgpr1, $vgpr2183 184 ; CHECK-LABEL: name: test_fma185 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2186 ; CHECK-NEXT: {{ $}}187 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0188 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1189 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2190 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]191 ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY2]]192 ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = nsz G_FMA [[COPY]], [[FNEG]], [[FNEG1]]193 ; CHECK-NEXT: $vgpr0 = COPY [[FMA]](s32)194 %0:_(s32) = COPY $vgpr0195 %1:_(s32) = COPY $vgpr1196 %2:_(s32) = COPY $vgpr2197 %3:_(s32) = nsz G_FMA %0, %1, %2198 %4:_(s32) = G_FNEG %3199 $vgpr0 = COPY %4(s32)200 201...202---203name: test_fmad204body: |205 bb.0:206 liveins: $vgpr0, $vgpr1, $vgpr2207 208 ; CHECK-LABEL: name: test_fmad209 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2210 ; CHECK-NEXT: {{ $}}211 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0212 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1213 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2214 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]215 ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY2]]216 ; CHECK-NEXT: [[FMAD:%[0-9]+]]:_(s32) = nsz G_FMAD [[COPY]], [[FNEG]], [[FNEG1]]217 ; CHECK-NEXT: $vgpr0 = COPY [[FMAD]](s32)218 %0:_(s32) = COPY $vgpr0219 %1:_(s32) = COPY $vgpr1220 %2:_(s32) = COPY $vgpr2221 %3:_(s32) = nsz G_FMAD %0, %1, %2222 %4:_(s32) = G_FNEG %3223 $vgpr0 = COPY %4(s32)224 225...226---227name: test_fmul228body: |229 bb.0:230 liveins: $vgpr0, $vgpr1231 232 ; CHECK-LABEL: name: test_fmul233 ; CHECK: liveins: $vgpr0, $vgpr1234 ; CHECK-NEXT: {{ $}}235 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0236 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1237 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]238 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[FNEG]]239 ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32)240 %0:_(s32) = COPY $vgpr0241 %1:_(s32) = COPY $vgpr1242 %2:_(s32) = G_FMUL %0, %1243 %3:_(s32) = G_FNEG %2244 $vgpr0 = COPY %3(s32)245 246...247---248name: test_fpext249body: |250 bb.0:251 liveins: $vgpr0252 253 ; CHECK-LABEL: name: test_fpext254 ; CHECK: liveins: $vgpr0255 ; CHECK-NEXT: {{ $}}256 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0257 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)258 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[TRUNC]]259 ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG]](s16)260 ; CHECK-NEXT: $vgpr0 = COPY [[FPEXT]](s32)261 %0:_(s32) = COPY $vgpr0262 %1:_(s16) = G_TRUNC %0(s32)263 %2:_(s32) = G_FPEXT %1(s16)264 %3:_(s32) = G_FNEG %2265 $vgpr0 = COPY %3(s32)266 267...268---269name: test_intrinsic_trunc270body: |271 bb.0:272 liveins: $vgpr0273 274 ; CHECK-LABEL: name: test_intrinsic_trunc275 ; CHECK: liveins: $vgpr0276 ; CHECK-NEXT: {{ $}}277 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0278 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]279 ; CHECK-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FNEG]]280 ; CHECK-NEXT: $vgpr0 = COPY [[INTRINSIC_TRUNC]](s32)281 %0:_(s32) = COPY $vgpr0282 %1:_(s32) = G_INTRINSIC_TRUNC %0283 %2:_(s32) = G_FNEG %1284 $vgpr0 = COPY %2(s32)285 286...287---288name: test_frint289body: |290 bb.0:291 liveins: $vgpr0292 293 ; CHECK-LABEL: name: test_frint294 ; CHECK: liveins: $vgpr0295 ; CHECK-NEXT: {{ $}}296 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0297 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]298 ; CHECK-NEXT: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FNEG]]299 ; CHECK-NEXT: $vgpr0 = COPY [[FRINT]](s32)300 %0:_(s32) = COPY $vgpr0301 %1:_(s32) = G_FRINT %0302 %2:_(s32) = G_FNEG %1303 $vgpr0 = COPY %2(s32)304 305...306---307name: test_fnearbyint308body: |309 bb.0:310 liveins: $vgpr0311 312 ; CHECK-LABEL: name: test_fnearbyint313 ; CHECK: liveins: $vgpr0314 ; CHECK-NEXT: {{ $}}315 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0316 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]317 ; CHECK-NEXT: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FNEG]]318 ; CHECK-NEXT: $vgpr0 = COPY [[FNEARBYINT]](s32)319 %0:_(s32) = COPY $vgpr0320 %1:_(s32) = G_FNEARBYINT %0321 %2:_(s32) = G_FNEG %1322 $vgpr0 = COPY %2(s32)323 324...325---326name: test_intrinsic_round327body: |328 bb.0:329 liveins: $vgpr0330 331 ; CHECK-LABEL: name: test_intrinsic_round332 ; CHECK: liveins: $vgpr0333 ; CHECK-NEXT: {{ $}}334 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0335 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]336 ; CHECK-NEXT: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FNEG]]337 ; CHECK-NEXT: $vgpr0 = COPY [[INTRINSIC_ROUND]](s32)338 %0:_(s32) = COPY $vgpr0339 %1:_(s32) = G_INTRINSIC_ROUND %0340 %2:_(s32) = G_FNEG %1341 $vgpr0 = COPY %2(s32)342 343...344---345name: test_intrinsic_roundeven346body: |347 bb.0:348 liveins: $vgpr0349 350 ; CHECK-LABEL: name: test_intrinsic_roundeven351 ; CHECK: liveins: $vgpr0352 ; CHECK-NEXT: {{ $}}353 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0354 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]355 ; CHECK-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FNEG]]356 ; CHECK-NEXT: $vgpr0 = COPY [[INTRINSIC_ROUNDEVEN]](s32)357 %0:_(s32) = COPY $vgpr0358 %1:_(s32) = G_INTRINSIC_ROUNDEVEN %0359 %2:_(s32) = G_FNEG %1360 $vgpr0 = COPY %2(s32)361 362...363---364name: test_fsin365body: |366 bb.0:367 liveins: $vgpr0368 369 ; CHECK-LABEL: name: test_fsin370 ; CHECK: liveins: $vgpr0371 ; CHECK-NEXT: {{ $}}372 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0373 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]374 ; CHECK-NEXT: [[FSIN:%[0-9]+]]:_(s32) = G_FSIN [[FNEG]]375 ; CHECK-NEXT: $vgpr0 = COPY [[FSIN]](s32)376 %0:_(s32) = COPY $vgpr0377 %1:_(s32) = G_FSIN %0378 %2:_(s32) = G_FNEG %1379 $vgpr0 = COPY %2(s32)380 381...382---383name: test_fcanonicalize384body: |385 bb.0:386 liveins: $vgpr0387 388 ; CHECK-LABEL: name: test_fcanonicalize389 ; CHECK: liveins: $vgpr0390 ; CHECK-NEXT: {{ $}}391 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0392 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]393 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[FNEG]]394 ; CHECK-NEXT: $vgpr0 = COPY [[FCANONICALIZE]](s32)395 %0:_(s32) = COPY $vgpr0396 %1:_(s32) = G_FCANONICALIZE %0397 %2:_(s32) = G_FNEG %1398 $vgpr0 = COPY %2(s32)399 400...401---402name: test_amdgcn_rcp_iflag403body: |404 bb.0:405 liveins: $vgpr0406 407 ; CHECK-LABEL: name: test_amdgcn_rcp_iflag408 ; CHECK: liveins: $vgpr0409 ; CHECK-NEXT: {{ $}}410 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0411 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]412 ; CHECK-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FNEG]](s32)413 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_RCP_IFLAG]](s32)414 %0:_(s32) = COPY $vgpr0415 %1:_(s32) = G_AMDGPU_RCP_IFLAG %0416 %2:_(s32) = G_FNEG %1417 $vgpr0 = COPY %2(s32)418 419...420---421name: test_fptrunc422body: |423 bb.0:424 liveins: $vgpr0_vgpr1425 ; CHECK-LABEL: name: test_fptrunc426 ; CHECK: liveins: $vgpr0_vgpr1427 ; CHECK-NEXT: {{ $}}428 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1429 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY]]430 ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FNEG]](s64)431 ; CHECK-NEXT: $vgpr0 = COPY [[FPTRUNC]](s32)432 %0:_(s64) = COPY $vgpr0_vgpr1433 %1:_(s32) = G_FPTRUNC %0:_(s64)434 %2:_(s32) = G_FNEG %1:_435 $vgpr0 = COPY %2:_(s32)436 437...438---439name: test_amdgcn_rcp440body: |441 bb.0:442 liveins: $vgpr0443 444 ; CHECK-LABEL: name: test_amdgcn_rcp445 ; CHECK: liveins: $vgpr0446 ; CHECK-NEXT: {{ $}}447 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0448 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]449 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FNEG]](s32)450 ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)451 %0:_(s32) = COPY $vgpr0452 %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0(s32)453 %2:_(s32) = G_FNEG %1454 $vgpr0 = COPY %2(s32)455 456...457---458name: test_amdgcn_rcp_legacy459body: |460 bb.0:461 liveins: $vgpr0462 463 ; CHECK-LABEL: name: test_amdgcn_rcp_legacy464 ; CHECK: liveins: $vgpr0465 ; CHECK-NEXT: {{ $}}466 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0467 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]468 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), [[FNEG]](s32)469 ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)470 %0:_(s32) = COPY $vgpr0471 %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), %0(s32)472 %2:_(s32) = G_FNEG %1473 $vgpr0 = COPY %2(s32)474 475...476---477name: test_amdgcn_sin478body: |479 bb.0:480 liveins: $vgpr0481 482 ; CHECK-LABEL: name: test_amdgcn_sin483 ; CHECK: liveins: $vgpr0484 ; CHECK-NEXT: {{ $}}485 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0486 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]487 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FNEG]](s32)488 ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)489 %0:_(s32) = COPY $vgpr0490 %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0(s32)491 %2:_(s32) = G_FNEG %1492 $vgpr0 = COPY %2(s32)493 494...495---496name: test_fmul_legacy497body: |498 bb.0:499 liveins: $vgpr0, $vgpr1500 501 ; CHECK-LABEL: name: test_fmul_legacy502 ; CHECK: liveins: $vgpr0, $vgpr1503 ; CHECK-NEXT: {{ $}}504 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0505 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1506 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]507 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[COPY]](s32), [[FNEG]](s32)508 ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)509 %0:_(s32) = COPY $vgpr0510 %1:_(s32) = COPY $vgpr1511 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), %0(s32), %1(s32)512 %3:_(s32) = G_FNEG %2513 $vgpr0 = COPY %3(s32)514 515...516---517name: test_fmed3518body: |519 bb.0:520 liveins: $vgpr0, $vgpr1, $vgpr2521 522 ; CHECK-LABEL: name: test_fmed3523 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2524 ; CHECK-NEXT: {{ $}}525 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0526 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1527 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2528 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]529 ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]530 ; CHECK-NEXT: [[FNEG2:%[0-9]+]]:_(s32) = G_FNEG [[COPY2]]531 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), [[FNEG]](s32), [[FNEG1]](s32), [[FNEG2]](s32)532 ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)533 %0:_(s32) = COPY $vgpr0534 %1:_(s32) = COPY $vgpr1535 %2:_(s32) = COPY $vgpr2536 %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0(s32), %1(s32), %2(s32)537 %4:_(s32) = G_FNEG %3538 $vgpr0 = COPY %4(s32)539 540...541---542name: test_amdgcn_fma_legacy543body: |544 bb.0:545 liveins: $vgpr0, $vgpr1, $vgpr2546 547 ; CHECK-LABEL: name: test_amdgcn_fma_legacy548 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2549 ; CHECK-NEXT: {{ $}}550 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0551 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1552 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2553 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]554 ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY2]]555 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fma.legacy), [[COPY]](s32), [[FNEG]](s32), [[FNEG1]](s32)556 ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32)557 %0:_(s32) = COPY $vgpr0558 %1:_(s32) = COPY $vgpr1559 %2:_(s32) = COPY $vgpr2560 %3:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fma.legacy), %0(s32), %1(s32), %2(s32)561 %4:_(s32) = G_FNEG %3562 $vgpr0 = COPY %4(s32)563 564...565 566# Don't fold fneg for fadd, fsub, fma, fmad or fma_legacy without nsz567---568name: test_fadd_sz569body: |570 bb.0:571 liveins: $vgpr0, $vgpr1572 573 ; CHECK-LABEL: name: test_fadd_sz574 ; CHECK: liveins: $vgpr0, $vgpr1575 ; CHECK-NEXT: {{ $}}576 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0577 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1578 ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]579 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FADD]]580 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)581 %0:_(s32) = COPY $vgpr0582 %1:_(s32) = COPY $vgpr1583 %2:_(s32) = G_FADD %0, %1584 %3:_(s32) = G_FNEG %2585 $vgpr0 = COPY %3(s32)586 587...588---589name: test_fsub_sz590body: |591 bb.0:592 liveins: $vgpr0, $vgpr1593 594 ; CHECK-LABEL: name: test_fsub_sz595 ; CHECK: liveins: $vgpr0, $vgpr1596 ; CHECK-NEXT: {{ $}}597 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0598 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1599 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]600 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FSUB]]601 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)602 %0:_(s32) = COPY $vgpr0603 %1:_(s32) = COPY $vgpr1604 %2:_(s32) = G_FSUB %0, %1605 %3:_(s32) = G_FNEG %2606 $vgpr0 = COPY %3(s32)607 608...609---610name: test_fma_sz611body: |612 bb.0:613 liveins: $vgpr0, $vgpr1, $vgpr2614 615 ; CHECK-LABEL: name: test_fma_sz616 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2617 ; CHECK-NEXT: {{ $}}618 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0619 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1620 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2621 ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]622 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMA]]623 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)624 %0:_(s32) = COPY $vgpr0625 %1:_(s32) = COPY $vgpr1626 %2:_(s32) = COPY $vgpr2627 %3:_(s32) = G_FMA %0, %1, %2628 %4:_(s32) = G_FNEG %3629 $vgpr0 = COPY %4(s32)630 631...632---633name: test_fmad_sz634body: |635 bb.0:636 liveins: $vgpr0, $vgpr1, $vgpr2637 638 ; CHECK-LABEL: name: test_fmad_sz639 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2640 ; CHECK-NEXT: {{ $}}641 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0642 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1643 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2644 ; CHECK-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]645 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMAD]]646 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)647 %0:_(s32) = COPY $vgpr0648 %1:_(s32) = COPY $vgpr1649 %2:_(s32) = COPY $vgpr2650 %3:_(s32) = G_FMAD %0, %1, %2651 %4:_(s32) = G_FNEG %3652 $vgpr0 = COPY %4(s32)653 654...655---656name: test_amdgcn_fma_legacy_sz657body: |658 bb.0:659 liveins: $vgpr0, $vgpr1, $vgpr2660 661 ; CHECK-LABEL: name: test_amdgcn_fma_legacy_sz662 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2663 ; CHECK-NEXT: {{ $}}664 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0665 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1666 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2667 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fma.legacy), [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)668 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]669 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)670 %0:_(s32) = COPY $vgpr0671 %1:_(s32) = COPY $vgpr1672 %2:_(s32) = COPY $vgpr2673 %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fma.legacy), %0(s32), %1(s32), %2(s32)674 %4:_(s32) = G_FNEG %3675 $vgpr0 = COPY %4(s32)676 677...678 679# Don't negate 0 for minnum, maxnum680---681name: test_fminnum_zero682body: |683 bb.0:684 liveins: $vgpr0685 ; CHECK-LABEL: name: test_fminnum_zero686 ; CHECK: liveins: $vgpr0687 ; CHECK-NEXT: {{ $}}688 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0689 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00690 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[C]]691 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMINNUM]]692 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)693 %0:_(s32) = COPY $vgpr0694 %1:_(s32) = G_FCONSTANT float 0.000000e+00695 %2:_(s32) = G_FMINNUM %0:_, %1:_696 %3:_(s32) = G_FNEG %2:_697 $vgpr0 = COPY %3:_(s32)698 699...700 701# On VI and above don't negate 1.0 / (0.5 * pi)702---703name: test_fminnum_inv2pi_half704body: |705 bb.0:706 liveins: $vgpr0707 ; CHECK-LABEL: name: test_fminnum_inv2pi_half708 ; CHECK: liveins: $vgpr0709 ; CHECK-NEXT: {{ $}}710 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0711 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)712 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118713 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s16) = G_FMINNUM [[TRUNC]], [[C]]714 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FMINNUM]]715 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FNEG]](s16)716 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)717 %0:_(s32) = COPY $vgpr0718 %1:_(s16) = G_TRUNC %0:_(s32)719 %2:_(s16) = G_FCONSTANT half 0xH3118720 %3:_(s16) = G_FMINNUM %1:_, %2:_721 %4:_(s16) = G_FNEG %3:_722 %5:_(s32) = G_ANYEXT %4:_(s16)723 $vgpr0 = COPY %5:_(s32)724 725...726---727name: test_fminnum_inv2pi_float728body: |729 bb.0:730 liveins: $vgpr0731 ; CHECK-LABEL: name: test_fminnum_inv2pi_float732 ; CHECK: liveins: $vgpr0733 ; CHECK-NEXT: {{ $}}734 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0735 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000736 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[C]]737 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMINNUM]]738 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)739 %0:_(s32) = COPY $vgpr0740 %1:_(s32) = G_FCONSTANT float 0x3FC45F3060000000741 %2:_(s32) = G_FMINNUM %0:_, %1:_742 %3:_(s32) = G_FNEG %2:_743 $vgpr0 = COPY %3:_(s32)744 745...746---747name: test_fminnum_inv2pi_double748body: |749 bb.0:750 liveins: $vgpr0_vgpr1751 ; CHECK-LABEL: name: test_fminnum_inv2pi_double752 ; CHECK: liveins: $vgpr0_vgpr1753 ; CHECK-NEXT: {{ $}}754 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1755 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C882756 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s64) = G_FMINNUM [[COPY]], [[C]]757 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[FMINNUM]]758 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FNEG]](s64)759 %0:_(s64) = COPY $vgpr0_vgpr1760 %1:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C882761 %2:_(s64) = G_FMINNUM %0:_, %1:_762 %3:_(s64) = G_FNEG %2:_763 $vgpr0_vgpr1 = COPY %3:_(s64)764 765...766 767#Don't fold when where instruction count will not decrease.768---769name: test_use_both770body: |771 bb.0:772 liveins: $vgpr0, $vgpr1, $vgpr2773 774 ; CHECK-LABEL: name: test_use_both775 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2776 ; CHECK-NEXT: {{ $}}777 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0778 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1779 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2780 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]781 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]782 ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FNEG]], [[COPY2]]783 ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32)784 ; CHECK-NEXT: $vgpr1 = COPY [[FNEG]](s32)785 ; CHECK-NEXT: $vgpr2 = COPY [[FMUL1]](s32)786 %0:_(s32) = COPY $vgpr0787 %1:_(s32) = COPY $vgpr1788 %2:_(s32) = COPY $vgpr2789 %3:_(s32) = G_FMUL %0, %1790 %4:_(s32) = G_FNEG %3791 %5:_(s32) = G_FMUL %4, %2792 $vgpr0 = COPY %3:_(s32)793 $vgpr1 = COPY %4:_(s32)794 $vgpr2 = COPY %5:_(s32)795 796...797 798#Don't fold when where instruction count will not decrease.799---800name: test_use_both2801body: |802 bb.0:803 liveins: $vgpr0, $vgpr1804 805 ; CHECK-LABEL: name: test_use_both2806 ; CHECK: liveins: $vgpr0, $vgpr1807 ; CHECK-NEXT: {{ $}}808 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0809 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1810 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]811 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]812 ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32)813 ; CHECK-NEXT: $vgpr1 = COPY [[FNEG]](s32)814 %0:_(s32) = COPY $vgpr0815 %1:_(s32) = COPY $vgpr1816 %2:_(s32) = G_FMUL %0, %1817 %3:_(s32) = G_FNEG %2818 $vgpr0 = COPY %2:_(s32)819 $vgpr1 = COPY %3:_(s32)820 821...822 823---824name: multiple_uses_of_fneg825body: |826 bb.0:827 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3828 829 ; CHECK-LABEL: name: multiple_uses_of_fneg830 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3831 ; CHECK-NEXT: {{ $}}832 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0833 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1834 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2835 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3836 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]837 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[FNEG]]838 ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FMUL]], [[COPY2]]839 ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL]], [[COPY3]]840 ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32)841 ; CHECK-NEXT: $vgpr1 = COPY [[FMUL1]](s32)842 ; CHECK-NEXT: $vgpr2 = COPY [[FMUL2]](s32)843 %0:_(s32) = COPY $vgpr0844 %1:_(s32) = COPY $vgpr1845 %2:_(s32) = COPY $vgpr2846 %3:_(s32) = COPY $vgpr3847 848 %4:_(s32) = G_FMUL %0, %1849 %5:_(s32) = G_FNEG %4850 %6:_(s32) = G_FMUL %5, %2851 %7:_(s32) = G_FMUL %5, %3852 853 $vgpr0 = COPY %5:_(s32)854 $vgpr1 = COPY %6:_(s32)855 $vgpr2 = COPY %7:_(s32)856 857...858 859# Check if new fneg is inserted at the appropriate place860---861name: fneg_src_has_multiple_uses862body: |863 bb.0:864 liveins: $vgpr0, $vgpr1, $vgpr2865 866 ; CHECK-LABEL: name: fneg_src_has_multiple_uses867 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2868 ; CHECK-NEXT: {{ $}}869 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0870 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1871 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2872 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]]873 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[FNEG]]874 ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]]875 ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FNEG1]], [[COPY2]]876 ; CHECK-NEXT: $vgpr0 = COPY [[FMUL1]](s32)877 ; CHECK-NEXT: $vgpr1 = COPY [[FMUL]](s32)878 %0:_(s32) = COPY $vgpr0879 %1:_(s32) = COPY $vgpr1880 %2:_(s32) = COPY $vgpr2881 %3:_(s32) = G_FMUL %0:_, %1:_882 %4:_(s32) = G_FMUL %3:_, %2:_883 %5:_(s32) = G_FNEG %3:_884 $vgpr0 = COPY %4:_(s32)885 $vgpr1 = COPY %5:_(s32)886 887...888