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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: fshl_i326tracksRegLiveness: true7body: |8 bb.0:9 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr310 11 ; CHECK-LABEL: name: fshl_i3212 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr313 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: %a:_(s32) = COPY $vgpr015 ; CHECK-NEXT: %b:_(s32) = COPY $vgpr116 ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr217 ; CHECK-NEXT: %or:_(s32) = G_FSHL %a, %b, %amt(s32)18 ; CHECK-NEXT: $vgpr3 = COPY %or(s32)19 %a:_(s32) = COPY $vgpr020 %b:_(s32) = COPY $vgpr121 %amt:_(s32) = COPY $vgpr222 %bw:_(s32) = G_CONSTANT i32 3223 %shl:_(s32) = G_SHL %a, %amt24 %sub:_(s32) = G_SUB %bw, %amt25 %lshr:_(s32) = G_LSHR %b, %sub26 %or:_(s32) = G_OR %shl, %lshr27 $vgpr3 = COPY %or28...29 30---31name: fshl_v2i3232tracksRegLiveness: true33body: |34 bb.0:35 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr736 37 ; CHECK-LABEL: name: fshl_v2i3238 ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr739 ; CHECK-NEXT: {{ $}}40 ; CHECK-NEXT: %a:_(<2 x s32>) = COPY $vgpr0_vgpr141 ; CHECK-NEXT: %b:_(<2 x s32>) = COPY $vgpr2_vgpr342 ; CHECK-NEXT: %amt:_(<2 x s32>) = COPY $vgpr4_vgpr543 ; CHECK-NEXT: %or:_(<2 x s32>) = G_FSHL %a, %b, %amt(<2 x s32>)44 ; CHECK-NEXT: $vgpr6_vgpr7 = COPY %or(<2 x s32>)45 %a:_(<2 x s32>) = COPY $vgpr0_vgpr146 %b:_(<2 x s32>) = COPY $vgpr2_vgpr347 %amt:_(<2 x s32>) = COPY $vgpr4_vgpr548 %scalar_bw:_(s32) = G_CONSTANT i32 3249 %bw:_(<2 x s32>) = G_BUILD_VECTOR %scalar_bw, %scalar_bw50 %shl:_(<2 x s32>) = G_SHL %a, %amt51 %sub:_(<2 x s32>) = G_SUB %bw, %amt52 %lshr:_(<2 x s32>) = G_LSHR %b, %sub53 %or:_(<2 x s32>) = G_OR %shl, %lshr54 $vgpr6_vgpr7 = COPY %or55...56 57---58name: fshl_commute_i3259tracksRegLiveness: true60body: |61 bb.0:62 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr363 64 ; CHECK-LABEL: name: fshl_commute_i3265 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr366 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: %a:_(s32) = COPY $vgpr068 ; CHECK-NEXT: %b:_(s32) = COPY $vgpr169 ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr270 ; CHECK-NEXT: %or:_(s32) = G_FSHL %a, %b, %amt(s32)71 ; CHECK-NEXT: $vgpr3 = COPY %or(s32)72 %a:_(s32) = COPY $vgpr073 %b:_(s32) = COPY $vgpr174 %amt:_(s32) = COPY $vgpr275 %bw:_(s32) = G_CONSTANT i32 3276 %shl:_(s32) = G_SHL %a, %amt77 %sub:_(s32) = G_SUB %bw, %amt78 %lshr:_(s32) = G_LSHR %b, %sub79 %or:_(s32) = G_OR %lshr, %shl80 $vgpr3 = COPY %or81...82 83---84name: fshr_i3285tracksRegLiveness: true86body: |87 bb.0:88 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr389 90 ; CHECK-LABEL: name: fshr_i3291 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr392 ; CHECK-NEXT: {{ $}}93 ; CHECK-NEXT: %a:_(s32) = COPY $vgpr094 ; CHECK-NEXT: %b:_(s32) = COPY $vgpr195 ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr296 ; CHECK-NEXT: %or:_(s32) = G_FSHR %a, %b, %amt(s32)97 ; CHECK-NEXT: $vgpr3 = COPY %or(s32)98 %a:_(s32) = COPY $vgpr099 %b:_(s32) = COPY $vgpr1100 %amt:_(s32) = COPY $vgpr2101 %bw:_(s32) = G_CONSTANT i32 32102 %lshr:_(s32) = G_LSHR %b, %amt103 %sub:_(s32) = G_SUB %bw, %amt104 %shl:_(s32) = G_SHL %a, %sub105 %or:_(s32) = G_OR %shl, %lshr106 $vgpr3 = COPY %or107...108 109---110name: fsh_i32_const111tracksRegLiveness: true112body: |113 bb.0:114 liveins: $vgpr0, $vgpr1, $vgpr2115 116 ; CHECK-LABEL: name: fsh_i32_const117 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2118 ; CHECK-NEXT: {{ $}}119 ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0120 ; CHECK-NEXT: %b:_(s32) = COPY $vgpr1121 ; CHECK-NEXT: %amt1:_(s32) = G_CONSTANT i32 12122 ; CHECK-NEXT: %or:_(s32) = G_FSHR %a, %b, %amt1(s32)123 ; CHECK-NEXT: $vgpr2 = COPY %or(s32)124 %a:_(s32) = COPY $vgpr0125 %b:_(s32) = COPY $vgpr1126 %amt0:_(s32) = G_CONSTANT i32 20127 %amt1:_(s32) = G_CONSTANT i32 12128 %shl:_(s32) = G_SHL %a, %amt0129 %lshr:_(s32) = G_LSHR %b, %amt1130 %or:_(s32) = G_OR %shl, %lshr131 $vgpr2 = COPY %or132...133 134---135name: fsh_v2i32_const136tracksRegLiveness: true137body: |138 bb.0:139 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5140 141 ; CHECK-LABEL: name: fsh_v2i32_const142 ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5143 ; CHECK-NEXT: {{ $}}144 ; CHECK-NEXT: %a:_(<2 x s32>) = COPY $vgpr0_vgpr1145 ; CHECK-NEXT: %b:_(<2 x s32>) = COPY $vgpr2_vgpr3146 ; CHECK-NEXT: %scalar_amt1:_(s32) = G_CONSTANT i32 12147 ; CHECK-NEXT: %amt1:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt1(s32), %scalar_amt1(s32)148 ; CHECK-NEXT: %or:_(<2 x s32>) = G_FSHR %a, %b, %amt1(<2 x s32>)149 ; CHECK-NEXT: $vgpr4_vgpr5 = COPY %or(<2 x s32>)150 %a:_(<2 x s32>) = COPY $vgpr0_vgpr1151 %b:_(<2 x s32>) = COPY $vgpr2_vgpr3152 %scalar_amt0:_(s32) = G_CONSTANT i32 20153 %amt0:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt0, %scalar_amt0154 %scalar_amt1:_(s32) = G_CONSTANT i32 12155 %amt1:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt1, %scalar_amt1156 %shl:_(<2 x s32>) = G_SHL %a, %amt0157 %lshr:_(<2 x s32>) = G_LSHR %b, %amt1158 %or:_(<2 x s32>) = G_OR %shl, %lshr159 $vgpr4_vgpr5 = COPY %or160...161 162---163name: fsh_i32_bad_const164tracksRegLiveness: true165body: |166 bb.0:167 liveins: $vgpr0, $vgpr1, $vgpr2168 169 ; CHECK-LABEL: name: fsh_i32_bad_const170 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2171 ; CHECK-NEXT: {{ $}}172 ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0173 ; CHECK-NEXT: %b:_(s32) = COPY $vgpr1174 ; CHECK-NEXT: %amt0:_(s32) = G_CONSTANT i32 20175 ; CHECK-NEXT: %amt1:_(s32) = G_CONSTANT i32 11176 ; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt0(s32)177 ; CHECK-NEXT: %lshr:_(s32) = G_LSHR %b, %amt1(s32)178 ; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr179 ; CHECK-NEXT: $vgpr2 = COPY %or(s32)180 %a:_(s32) = COPY $vgpr0181 %b:_(s32) = COPY $vgpr1182 %amt0:_(s32) = G_CONSTANT i32 20183 %amt1:_(s32) = G_CONSTANT i32 11184 %shl:_(s32) = G_SHL %a, %amt0185 %lshr:_(s32) = G_LSHR %b, %amt1186 %or:_(s32) = G_OR %shl, %lshr187 $vgpr2 = COPY %or188...189 190---191name: fshl_i32_bad_bw192tracksRegLiveness: true193body: |194 bb.0:195 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3196 197 ; CHECK-LABEL: name: fshl_i32_bad_bw198 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3199 ; CHECK-NEXT: {{ $}}200 ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0201 ; CHECK-NEXT: %b:_(s32) = COPY $vgpr1202 ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr2203 ; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 31204 ; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)205 ; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt206 ; CHECK-NEXT: %lshr:_(s32) = G_LSHR %b, %sub(s32)207 ; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr208 ; CHECK-NEXT: $vgpr3 = COPY %or(s32)209 %a:_(s32) = COPY $vgpr0210 %b:_(s32) = COPY $vgpr1211 %amt:_(s32) = COPY $vgpr2212 %bw:_(s32) = G_CONSTANT i32 31213 %shl:_(s32) = G_SHL %a, %amt214 %sub:_(s32) = G_SUB %bw, %amt215 %lshr:_(s32) = G_LSHR %b, %sub216 %or:_(s32) = G_OR %shl, %lshr217 $vgpr3 = COPY %or218...219 220---221name: fshl_i32_bad_amt_reg222tracksRegLiveness: true223body: |224 bb.0:225 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4226 227 ; CHECK-LABEL: name: fshl_i32_bad_amt_reg228 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4229 ; CHECK-NEXT: {{ $}}230 ; CHECK-NEXT: %a:_(s32) = COPY $vgpr0231 ; CHECK-NEXT: %b:_(s32) = COPY $vgpr1232 ; CHECK-NEXT: %amt:_(s32) = COPY $vgpr2233 ; CHECK-NEXT: %amt1:_(s32) = COPY $vgpr3234 ; CHECK-NEXT: %bw:_(s32) = G_CONSTANT i32 32235 ; CHECK-NEXT: %shl:_(s32) = G_SHL %a, %amt(s32)236 ; CHECK-NEXT: %sub:_(s32) = G_SUB %bw, %amt1237 ; CHECK-NEXT: %lshr:_(s32) = G_LSHR %b, %sub(s32)238 ; CHECK-NEXT: %or:_(s32) = G_OR %shl, %lshr239 ; CHECK-NEXT: $vgpr4 = COPY %or(s32)240 %a:_(s32) = COPY $vgpr0241 %b:_(s32) = COPY $vgpr1242 %amt:_(s32) = COPY $vgpr2243 %amt1:_(s32) = COPY $vgpr3244 %bw:_(s32) = G_CONSTANT i32 32245 %shl:_(s32) = G_SHL %a, %amt246 %sub:_(s32) = G_SUB %bw, %amt1247 %lshr:_(s32) = G_LSHR %b, %sub248 %or:_(s32) = G_OR %shl, %lshr249 $vgpr4 = COPY %or250...251