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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: test_const_const_16tracksRegLiveness: true7body: |8 bb.0:9 ; CHECK-LABEL: name: test_const_const_110 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25511 ; CHECK-NEXT: $sgpr0 = COPY [[C]](s32)12 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr013 %0:_(s32) = G_CONSTANT i32 25514 %1:_(s32) = G_CONSTANT i32 1515 %2:_(s32) = G_OR %0(s32), %1(s32)16 $sgpr0 = COPY %2(s32)17 SI_RETURN_TO_EPILOG implicit $sgpr018...19 20---21name: test_const_const_222tracksRegLiveness: true23body: |24 bb.0:25 ; CHECK-LABEL: name: test_const_const_226 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25527 ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)28 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr029 %0:_(s32) = G_CONSTANT i32 1530 %1:_(s32) = G_CONSTANT i32 25531 %2:_(s32) = G_OR %0(s32), %1(s32)32 $vgpr0 = COPY %2(s32)33 SI_RETURN_TO_EPILOG implicit $vgpr034...35 36---37name: test_const_const_338tracksRegLiveness: true39body: |40 bb.0:41 ; CHECK-LABEL: name: test_const_const_342 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 143165576543 ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)44 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr045 %0:_(s32) = G_CONSTANT i32 143165576546 %1:_(s32) = G_CONSTANT i32 114532461247 %2:_(s32) = G_OR %1(s32), %0(s32)48 $vgpr0 = COPY %2(s32)49 SI_RETURN_TO_EPILOG implicit $vgpr050...51 52---53name: test_or_or54tracksRegLiveness: true55body: |56 bb.0:57 liveins: $vgpr058 59 ; CHECK-LABEL: name: test_or_or60 ; CHECK: liveins: $vgpr061 ; CHECK-NEXT: {{ $}}62 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr063 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25564 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]65 ; CHECK-NEXT: $vgpr0 = COPY [[OR]](s32)66 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr067 %0:_(s32) = COPY $vgpr068 %1:_(s32) = G_CONSTANT i32 25569 %2:_(s32) = G_CONSTANT i32 1570 %3:_(s32) = G_OR %0, %1(s32)71 %4:_(s32) = G_OR %3, %272 $vgpr0 = COPY %4(s32)73 SI_RETURN_TO_EPILOG implicit $vgpr074...75 76---77name: test_shl_xor_or78tracksRegLiveness: true79body: |80 bb.0:81 liveins: $sgpr082 83 ; CHECK-LABEL: name: test_shl_xor_or84 ; CHECK: liveins: $sgpr085 ; CHECK-NEXT: {{ $}}86 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr087 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 588 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -189 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)90 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]91 ; CHECK-NEXT: $sgpr0 = COPY [[XOR]](s32)92 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr093 %0:_(s32) = COPY $sgpr094 %1:_(s32) = G_CONSTANT i32 595 %2:_(s32) = G_CONSTANT i32 -196 %3:_(s32) = G_CONSTANT i32 3197 %4:_(s32) = G_SHL %0, %1(s32)98 %5:_(s32) = G_XOR %4(s32), %2(s32)99 %6:_(s32) = G_OR %5(s32), %3(s32)100 $sgpr0 = COPY %6(s32)101 SI_RETURN_TO_EPILOG implicit $sgpr0102...103 104---105name: test_lshr_xor_or106tracksRegLiveness: true107body: |108 bb.0:109 liveins: $vgpr0110 111 ; CHECK-LABEL: name: test_lshr_xor_or112 ; CHECK: liveins: $vgpr0113 ; CHECK-NEXT: {{ $}}114 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0115 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5116 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1117 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)118 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[LSHR]], [[C1]]119 ; CHECK-NEXT: $vgpr0 = COPY [[XOR]](s32)120 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0121 %0:_(s32) = COPY $vgpr0122 %1:_(s32) = G_CONSTANT i32 5123 %2:_(s32) = G_CONSTANT i32 -1124 %3:_(s32) = G_CONSTANT i32 4160749568125 %4:_(s32) = G_LSHR %0, %1(s32)126 %5:_(s32) = G_XOR %4(s32), %2(s32)127 %6:_(s32) = G_OR %5(s32), %3(s32)128 $vgpr0 = COPY %6(s32)129 SI_RETURN_TO_EPILOG implicit $vgpr0130...131 132---133name: test_or_non_const134tracksRegLiveness: true135body: |136 bb.0:137 liveins: $sgpr0, $sgpr1138 139 ; CHECK-LABEL: name: test_or_non_const140 ; CHECK: liveins: $sgpr0, $sgpr1141 ; CHECK-NEXT: {{ $}}142 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0143 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16144 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1145 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)146 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[LSHR]], [[C1]]147 ; CHECK-NEXT: $sgpr0 = COPY [[XOR]](s32)148 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0149 %0:_(s32) = COPY $sgpr0150 %1:_(s32) = COPY $sgpr1151 %2:_(s32) = G_CONSTANT i32 16152 %3:_(s32) = G_CONSTANT i32 -1153 %4:_(s32) = G_CONSTANT i32 4294901760154 %5:_(s32) = G_LSHR %0, %2(s32)155 %6:_(s32) = G_XOR %5, %3(s32)156 %7:_(s32) = G_AND %1, %4(s32)157 %8:_(s32) = G_OR %6, %7158 $sgpr0 = COPY %8(s32)159 SI_RETURN_TO_EPILOG implicit $sgpr0160...161---162name: vector_const_splat_const_splat163tracksRegLiveness: true164body: |165 bb.0:166 ; CHECK-LABEL: name: vector_const_splat_const_splat167 ; CHECK: %mask:_(s16) = G_CONSTANT i16 255168 ; CHECK-NEXT: %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask(s16), %mask(s16)169 ; CHECK-NEXT: $vgpr0 = COPY %c2(<2 x s16>)170 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0171 %mask:_(s16) = G_CONSTANT i16 255172 %fifteen:_(s16) = G_CONSTANT i16 15173 %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen, %fifteen174 %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask, %mask175 %and:_(<2 x s16>) = G_OR %c1(<2 x s16>), %c2(<2 x s16>)176 $vgpr0 = COPY %and(<2 x s16>)177 SI_RETURN_TO_EPILOG implicit $vgpr0178...179---180name: vector_const_valid_not_splat181tracksRegLiveness: true182body: |183 bb.0:184 ; CHECK-LABEL: name: vector_const_valid_not_splat185 ; CHECK: %mask:_(s16) = G_CONSTANT i16 255186 ; CHECK-NEXT: %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask(s16), %mask(s16)187 ; CHECK-NEXT: $vgpr0 = COPY %c2(<2 x s16>)188 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0189 %fifteen:_(s16) = G_CONSTANT i16 15190 %sixteen:_(s16) = G_CONSTANT i16 16191 %mask:_(s16) = G_CONSTANT i16 255192 %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen, %sixteen193 %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask, %mask194 %and:_(<2 x s16>) = G_OR %c1(<2 x s16>), %c2(<2 x s16>)195 $vgpr0 = COPY %and(<2 x s16>)196 SI_RETURN_TO_EPILOG implicit $vgpr0197...198---199name: vector_dont_combine_const_too_wide200tracksRegLiveness: true201body: |202 bb.0:203 ; CHECK-LABEL: name: vector_dont_combine_const_too_wide204 ; CHECK: %fifteen:_(s16) = G_CONSTANT i16 15205 ; CHECK-NEXT: %too_wide:_(s16) = G_CONSTANT i16 257206 ; CHECK-NEXT: %mask:_(s16) = G_CONSTANT i16 255207 ; CHECK-NEXT: %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen(s16), %too_wide(s16)208 ; CHECK-NEXT: %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask(s16), %mask(s16)209 ; CHECK-NEXT: %and:_(<2 x s16>) = G_OR %c1, %c2210 ; CHECK-NEXT: $vgpr0 = COPY %and(<2 x s16>)211 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0212 %fifteen:_(s16) = G_CONSTANT i16 15213 %too_wide:_(s16) = G_CONSTANT i16 257214 %mask:_(s16) = G_CONSTANT i16 255215 %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen, %too_wide216 %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask, %mask217 %and:_(<2 x s16>) = G_OR %c1(<2 x s16>), %c2(<2 x s16>)218 $vgpr0 = COPY %and(<2 x s16>)219 SI_RETURN_TO_EPILOG implicit $vgpr0220...221