231 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: test_const_const6tracksRegLiveness: true7body: |8 bb.0:9 ; CHECK-LABEL: name: test_const_const10 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1511 ; CHECK-NEXT: $sgpr0 = COPY [[C]](s32)12 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr013 %0:_(s32) = G_CONSTANT i32 1514 %1:_(s32) = G_CONSTANT i32 25515 %2:_(s32) = G_AND %0(s32), %1(s32)16 $sgpr0 = COPY %2(s32)17 SI_RETURN_TO_EPILOG implicit $sgpr018...19 20---21name: test_const_const_222tracksRegLiveness: true23body: |24 bb.0:25 ; CHECK-LABEL: name: test_const_const_226 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1527 ; CHECK-NEXT: $sgpr0 = COPY [[C]](s32)28 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr029 %0:_(s32) = G_CONSTANT i32 25530 %1:_(s32) = G_CONSTANT i32 1531 %2:_(s32) = G_AND %0(s32), %1(s32)32 $sgpr0 = COPY %2(s32)33 SI_RETURN_TO_EPILOG implicit $sgpr034...35 36---37name: test_const_const_338tracksRegLiveness: true39body: |40 bb.0:41 ; CHECK-LABEL: name: test_const_const_342 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -143165576643 ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)44 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr045 %0:_(s32) = G_CONSTANT i32 286331153046 %1:_(s32) = G_CONSTANT i32 400863614247 %2:_(s32) = G_AND %0(s32), %1(s32)48 $vgpr0 = COPY %2(s32)49 SI_RETURN_TO_EPILOG implicit $vgpr050...51 52---53name: test_and_and54tracksRegLiveness: true55body: |56 bb.0:57 liveins: $vgpr058 59 ; CHECK-LABEL: name: test_and_and60 ; CHECK: liveins: $vgpr061 ; CHECK-NEXT: {{ $}}62 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr063 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1564 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]65 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)66 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr067 %0:_(s32) = COPY $vgpr068 %1:_(s32) = G_CONSTANT i32 1569 %2:_(s32) = G_CONSTANT i32 25570 %3:_(s32) = G_AND %0, %1(s32)71 %4:_(s32) = G_AND %3, %272 $vgpr0 = COPY %4(s32)73 SI_RETURN_TO_EPILOG implicit $vgpr074...75 76---77name: test_shl_and78tracksRegLiveness: true79body: |80 bb.0:81 liveins: $sgpr082 83 ; CHECK-LABEL: name: test_shl_and84 ; CHECK: liveins: $sgpr085 ; CHECK-NEXT: {{ $}}86 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr087 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 588 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)89 ; CHECK-NEXT: $sgpr0 = COPY [[SHL]](s32)90 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr091 %0:_(s32) = COPY $sgpr092 %1:_(s32) = G_CONSTANT i32 593 %2:_(s32) = G_CONSTANT i32 429496726494 %3:_(s32) = G_SHL %0, %1(s32)95 %4:_(s32) = G_AND %3, %296 $sgpr0 = COPY %4(s32)97 SI_RETURN_TO_EPILOG implicit $sgpr098...99 100---101name: test_lshr_and102tracksRegLiveness: true103body: |104 bb.0:105 liveins: $vgpr0106 107 ; CHECK-LABEL: name: test_lshr_and108 ; CHECK: liveins: $vgpr0109 ; CHECK-NEXT: {{ $}}110 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0111 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5112 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)113 ; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](s32)114 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0115 %0:_(s32) = COPY $vgpr0116 %1:_(s32) = G_CONSTANT i32 5117 %2:_(s32) = G_CONSTANT i32 134217727118 %3:_(s32) = G_LSHR %0, %1(s32)119 %4:_(s32) = G_AND %3, %2120 $vgpr0 = COPY %4(s32)121 SI_RETURN_TO_EPILOG implicit $vgpr0122...123 124---125name: test_and_non_const126tracksRegLiveness: true127body: |128 bb.0:129 liveins: $sgpr0, $sgpr1130 131 ; CHECK-LABEL: name: test_and_non_const132 ; CHECK: liveins: $sgpr0, $sgpr1133 ; CHECK-NEXT: {{ $}}134 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0135 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16136 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)137 ; CHECK-NEXT: $sgpr0 = COPY [[LSHR]](s32)138 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0139 %0:_(s32) = COPY $sgpr0140 %1:_(s32) = COPY $sgpr1141 %2:_(s32) = G_CONSTANT i32 16142 %3:_(s32) = G_CONSTANT i32 65535143 %4:_(s32) = G_OR %1, %3144 %5:_(s32) = G_LSHR %0, %2(s32)145 %6:_(s32) = G_AND %5, %4146 $sgpr0 = COPY %6(s32)147 SI_RETURN_TO_EPILOG implicit $sgpr0148...149---150name: test_sext_inreg151tracksRegLiveness: true152body: |153 bb.0:154 ; CHECK-LABEL: name: test_sext_inreg155 ; CHECK: %cst_1:_(s32) = G_CONSTANT i32 -5156 ; CHECK-NEXT: $sgpr0 = COPY %cst_1(s32)157 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0158 %cst_1:_(s32) = G_CONSTANT i32 -5159 160 ; 000 ... 1011161 %cst_11:_(s32) = G_CONSTANT i32 11162 163 ; Sext from the 4th bit -> 111 ... 1011 = -5164 %sext_inreg_11:_(s32) = G_SEXT_INREG %cst_11, 4165 166 %and:_(s32) = G_AND %cst_1(s32), %sext_inreg_11(s32)167 $sgpr0 = COPY %and(s32)168 SI_RETURN_TO_EPILOG implicit $sgpr0169...170---171name: vector_const_splat_const_splat172tracksRegLiveness: true173body: |174 bb.0:175 ; CHECK-LABEL: name: vector_const_splat_const_splat176 ; CHECK: %fifteen:_(s16) = G_CONSTANT i16 15177 ; CHECK-NEXT: %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen(s16), %fifteen(s16)178 ; CHECK-NEXT: $vgpr0 = COPY %c1(<2 x s16>)179 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0180 %fifteen:_(s16) = G_CONSTANT i16 15181 %mask:_(s16) = G_CONSTANT i16 255182 %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen, %fifteen183 %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask, %mask184 %and:_(<2 x s16>) = G_AND %c1(<2 x s16>), %c2(<2 x s16>)185 $vgpr0 = COPY %and(<2 x s16>)186 SI_RETURN_TO_EPILOG implicit $vgpr0187...188---189name: vector_const_valid_not_splat190tracksRegLiveness: true191body: |192 bb.0:193 ; CHECK-LABEL: name: vector_const_valid_not_splat194 ; CHECK: %fifteen:_(s16) = G_CONSTANT i16 15195 ; CHECK-NEXT: %sixteen:_(s16) = G_CONSTANT i16 16196 ; CHECK-NEXT: %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen(s16), %sixteen(s16)197 ; CHECK-NEXT: $vgpr0 = COPY %c1(<2 x s16>)198 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0199 %fifteen:_(s16) = G_CONSTANT i16 15200 %sixteen:_(s16) = G_CONSTANT i16 16201 %mask:_(s16) = G_CONSTANT i16 255202 %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen, %sixteen203 %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask, %mask204 %and:_(<2 x s16>) = G_AND %c1(<2 x s16>), %c2(<2 x s16>)205 $vgpr0 = COPY %and(<2 x s16>)206 SI_RETURN_TO_EPILOG implicit $vgpr0207...208---209name: vector_dont_combine_const_too_wide210tracksRegLiveness: true211body: |212 bb.0:213 ; CHECK-LABEL: name: vector_dont_combine_const_too_wide214 ; CHECK: %fifteen:_(s16) = G_CONSTANT i16 15215 ; CHECK-NEXT: %too_wide:_(s16) = G_CONSTANT i16 257216 ; CHECK-NEXT: %mask:_(s16) = G_CONSTANT i16 255217 ; CHECK-NEXT: %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen(s16), %too_wide(s16)218 ; CHECK-NEXT: %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask(s16), %mask(s16)219 ; CHECK-NEXT: %and:_(<2 x s16>) = G_AND %c1, %c2220 ; CHECK-NEXT: $vgpr0 = COPY %and(<2 x s16>)221 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0222 %fifteen:_(s16) = G_CONSTANT i16 15223 %too_wide:_(s16) = G_CONSTANT i16 257224 %mask:_(s16) = G_CONSTANT i16 255225 %c1:_(<2 x s16>) = G_BUILD_VECTOR %fifteen, %too_wide226 %c2:_(<2 x s16>) = G_BUILD_VECTOR %mask, %mask227 %and:_(<2 x s16>) = G_AND %c1(<2 x s16>), %c2(<2 x s16>)228 $vgpr0 = COPY %and(<2 x s16>)229 SI_RETURN_TO_EPILOG implicit $vgpr0230...231