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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s3 4---5name: inreg8_inreg166tracksRegLiveness: true7body: |8 bb.0:9 liveins: $vgpr010 ; CHECK-LABEL: name: inreg8_inreg1611 ; CHECK: liveins: $vgpr012 ; CHECK-NEXT: {{ $}}13 ; CHECK-NEXT: %copy:_(s32) = COPY $vgpr014 ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %copy, 815 ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)16 %copy:_(s32) = COPY $vgpr017 %inreg:_(s32) = G_SEXT_INREG %copy, 818 %inreg1:_(s32) = G_SEXT_INREG %inreg, 1619 $vgpr0 = COPY %inreg120...21 22---23name: inreg16_inreg1624tracksRegLiveness: true25body: |26 bb.0:27 liveins: $vgpr028 ; CHECK-LABEL: name: inreg16_inreg1629 ; CHECK: liveins: $vgpr030 ; CHECK-NEXT: {{ $}}31 ; CHECK-NEXT: %copy:_(s32) = COPY $vgpr032 ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %copy, 1633 ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)34 %copy:_(s32) = COPY $vgpr035 %inreg:_(s32) = G_SEXT_INREG %copy, 1636 %inreg1:_(s32) = G_SEXT_INREG %inreg, 1637 $vgpr0 = COPY %inreg138...39 40---41name: inreg16_inreg842tracksRegLiveness: true43body: |44 bb.0:45 liveins: $vgpr046 ; CHECK-LABEL: name: inreg16_inreg847 ; CHECK: liveins: $vgpr048 ; CHECK-NEXT: {{ $}}49 ; CHECK-NEXT: %copy:_(s32) = COPY $vgpr050 ; CHECK-NEXT: %inreg1:_(s32) = G_SEXT_INREG %copy, 851 ; CHECK-NEXT: $vgpr0 = COPY %inreg1(s32)52 %copy:_(s32) = COPY $vgpr053 %inreg:_(s32) = G_SEXT_INREG %copy, 1654 %inreg1:_(s32) = G_SEXT_INREG %inreg, 855 $vgpr0 = COPY %inreg156...57 58---59name: inreg16_inreg32_64bit60tracksRegLiveness: true61body: |62 bb.0:63 liveins: $vgpr0_vgpr164 ; CHECK-LABEL: name: inreg16_inreg32_64bit65 ; CHECK: liveins: $vgpr0_vgpr166 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: %copy:_(s64) = COPY $vgpr0_vgpr168 ; CHECK-NEXT: %inreg:_(s64) = G_SEXT_INREG %copy, 1669 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY %inreg(s64)70 %copy:_(s64) = COPY $vgpr0_vgpr171 %inreg:_(s64) = G_SEXT_INREG %copy, 1672 %inreg1:_(s64) = G_SEXT_INREG %inreg, 3273 $vgpr0_vgpr1 = COPY %inreg174...75 76---77name: inreg32_inreg32_64bit78tracksRegLiveness: true79body: |80 bb.0:81 liveins: $vgpr0_vgpr182 ; CHECK-LABEL: name: inreg32_inreg32_64bit83 ; CHECK: liveins: $vgpr0_vgpr184 ; CHECK-NEXT: {{ $}}85 ; CHECK-NEXT: %copy:_(s64) = COPY $vgpr0_vgpr186 ; CHECK-NEXT: %inreg:_(s64) = G_SEXT_INREG %copy, 3287 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY %inreg(s64)88 %copy:_(s64) = COPY $vgpr0_vgpr189 %inreg:_(s64) = G_SEXT_INREG %copy, 3290 %inreg1:_(s64) = G_SEXT_INREG %inreg, 3291 $vgpr0_vgpr1 = COPY %inreg192...93 94---95name: inreg32_inreg16_64bit96tracksRegLiveness: true97body: |98 bb.0:99 liveins: $vgpr0_vgpr1100 ; CHECK-LABEL: name: inreg32_inreg16_64bit101 ; CHECK: liveins: $vgpr0_vgpr1102 ; CHECK-NEXT: {{ $}}103 ; CHECK-NEXT: %copy:_(s64) = COPY $vgpr0_vgpr1104 ; CHECK-NEXT: %inreg1:_(s64) = G_SEXT_INREG %copy, 16105 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY %inreg1(s64)106 %copy:_(s64) = COPY $vgpr0_vgpr1107 %inreg:_(s64) = G_SEXT_INREG %copy, 32108 %inreg1:_(s64) = G_SEXT_INREG %inreg, 16109 $vgpr0_vgpr1 = COPY %inreg1110...111 112---113name: vector_inreg8_inreg16114tracksRegLiveness: true115body: |116 bb.0:117 liveins: $vgpr0_vgpr1_vgpr2_vgpr3118 ; CHECK-LABEL: name: vector_inreg8_inreg16119 ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3122 ; CHECK-NEXT: %inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 8123 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg(<4 x s32>)124 %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3125 %inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 8126 %inreg1:_(<4 x s32>) = G_SEXT_INREG %inreg, 16127 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg1128...129 130---131name: vector_inreg16_inreg16132tracksRegLiveness: true133body: |134 bb.0:135 liveins: $vgpr0_vgpr1_vgpr2_vgpr3136 ; CHECK-LABEL: name: vector_inreg16_inreg16137 ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3138 ; CHECK-NEXT: {{ $}}139 ; CHECK-NEXT: %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3140 ; CHECK-NEXT: %inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 16141 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg(<4 x s32>)142 %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3143 %inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 16144 %inreg1:_(<4 x s32>) = G_SEXT_INREG %inreg, 16145 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg1146...147 148---149name: vector_inreg16_inreg8150tracksRegLiveness: true151body: |152 bb.0:153 liveins: $vgpr0_vgpr1_vgpr2_vgpr3154 ; CHECK-LABEL: name: vector_inreg16_inreg8155 ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3156 ; CHECK-NEXT: {{ $}}157 ; CHECK-NEXT: %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3158 ; CHECK-NEXT: %inreg1:_(<4 x s32>) = G_SEXT_INREG %copy, 8159 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg1(<4 x s32>)160 %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3161 %inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 16162 %inreg1:_(<4 x s32>) = G_SEXT_INREG %inreg, 8163 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg1164...165