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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 %s -o - | FileCheck -check-prefix=GCN %s3 4define amdgpu_cs float @div_sqrt(float inreg %arg1) {5; GCN-LABEL: div_sqrt:6; GCN: ; %bb.0: ; %.entry7; GCN-NEXT: v_mul_f32_e64 v0, 0x4f800000, s08; GCN-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0xf800000, s09; GCN-NEXT: v_cndmask_b32_e32 v0, s0, v0, vcc_lo10; GCN-NEXT: v_sqrt_f32_e32 v1, v011; GCN-NEXT: v_add_nc_u32_e32 v2, -1, v112; GCN-NEXT: v_add_nc_u32_e32 v3, 1, v113; GCN-NEXT: v_fma_f32 v4, -v2, v1, v014; GCN-NEXT: v_fma_f32 v5, -v3, v1, v015; GCN-NEXT: v_cmp_ge_f32_e64 s0, 0, v416; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s017; GCN-NEXT: v_cmp_lt_f32_e64 s0, 0, v518; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s019; GCN-NEXT: v_mul_f32_e32 v2, 0x37800000, v120; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo21; GCN-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x26022; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo23; GCN-NEXT: v_rcp_f32_e32 v0, v024; GCN-NEXT: ; return to shader part epilog25.entry:26 %a = call float @llvm.sqrt.f32(float %arg1)27 %b = fdiv afn float 1.000000e+00, %a28 ret float %b29}30 31define amdgpu_cs float @sqrt_div(float inreg %arg1) {32; GCN-LABEL: sqrt_div:33; GCN: ; %bb.0: ; %.entry34; GCN-NEXT: v_rcp_f32_e32 v0, s035; GCN-NEXT: v_mul_f32_e32 v1, 0x4f800000, v036; GCN-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v037; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo38; GCN-NEXT: v_sqrt_f32_e32 v1, v039; GCN-NEXT: v_add_nc_u32_e32 v2, -1, v140; GCN-NEXT: v_add_nc_u32_e32 v3, 1, v141; GCN-NEXT: v_fma_f32 v4, -v2, v1, v042; GCN-NEXT: v_fma_f32 v5, -v3, v1, v043; GCN-NEXT: v_cmp_ge_f32_e64 s0, 0, v444; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s045; GCN-NEXT: v_cmp_lt_f32_e64 s0, 0, v546; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s047; GCN-NEXT: v_mul_f32_e32 v2, 0x37800000, v148; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo49; GCN-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x26050; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo51; GCN-NEXT: ; return to shader part epilog52.entry:53 %a = fdiv afn float 1.000000e+00, %arg154 %b = call float @llvm.sqrt.f32(float %a)55 ret float %b56}57 58define amdgpu_cs float @rcp_sqrt(float inreg %arg1) {59; GCN-LABEL: rcp_sqrt:60; GCN: ; %bb.0: ; %.entry61; GCN-NEXT: v_mul_f32_e64 v0, 0x4f800000, s062; GCN-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0xf800000, s063; GCN-NEXT: v_cndmask_b32_e32 v0, s0, v0, vcc_lo64; GCN-NEXT: v_sqrt_f32_e32 v1, v065; GCN-NEXT: v_add_nc_u32_e32 v2, -1, v166; GCN-NEXT: v_add_nc_u32_e32 v3, 1, v167; GCN-NEXT: v_fma_f32 v4, -v2, v1, v068; GCN-NEXT: v_fma_f32 v5, -v3, v1, v069; GCN-NEXT: v_cmp_ge_f32_e64 s0, 0, v470; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s071; GCN-NEXT: v_cmp_lt_f32_e64 s0, 0, v572; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s073; GCN-NEXT: v_mul_f32_e32 v2, 0x37800000, v174; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo75; GCN-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x26076; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo77; GCN-NEXT: v_rcp_f32_e32 v0, v078; GCN-NEXT: ; return to shader part epilog79.entry:80 %a = call float @llvm.sqrt.f32(float %arg1)81 %b = call float @llvm.amdgcn.rcp.f32(float %a)82 ret float %b83}84 85define amdgpu_cs float @sqrt_rcp(float inreg %arg1) {86; GCN-LABEL: sqrt_rcp:87; GCN: ; %bb.0: ; %.entry88; GCN-NEXT: v_rcp_f32_e32 v0, s089; GCN-NEXT: v_mul_f32_e32 v1, 0x4f800000, v090; GCN-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v091; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo92; GCN-NEXT: v_sqrt_f32_e32 v1, v093; GCN-NEXT: v_add_nc_u32_e32 v2, -1, v194; GCN-NEXT: v_add_nc_u32_e32 v3, 1, v195; GCN-NEXT: v_fma_f32 v4, -v2, v1, v096; GCN-NEXT: v_fma_f32 v5, -v3, v1, v097; GCN-NEXT: v_cmp_ge_f32_e64 s0, 0, v498; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s099; GCN-NEXT: v_cmp_lt_f32_e64 s0, 0, v5100; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0101; GCN-NEXT: v_mul_f32_e32 v2, 0x37800000, v1102; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo103; GCN-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260104; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo105; GCN-NEXT: ; return to shader part epilog106.entry:107 %a = call float @llvm.amdgcn.rcp.f32(float %arg1)108 %b = call float @llvm.sqrt.f32(float %a)109 ret float %b110}111 112define amdgpu_cs float @div_sqrt_contract(float inreg %arg1) {113; GCN-LABEL: div_sqrt_contract:114; GCN: ; %bb.0: ; %.entry115; GCN-NEXT: v_mul_f32_e64 v0, 0x4f800000, s0116; GCN-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0xf800000, s0117; GCN-NEXT: v_cndmask_b32_e32 v0, s0, v0, vcc_lo118; GCN-NEXT: v_sqrt_f32_e32 v1, v0119; GCN-NEXT: v_add_nc_u32_e32 v2, -1, v1120; GCN-NEXT: v_add_nc_u32_e32 v3, 1, v1121; GCN-NEXT: v_fma_f32 v4, -v2, v1, v0122; GCN-NEXT: v_fma_f32 v5, -v3, v1, v0123; GCN-NEXT: v_cmp_ge_f32_e64 s0, 0, v4124; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s0125; GCN-NEXT: v_cmp_lt_f32_e64 s0, 0, v5126; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0127; GCN-NEXT: v_mul_f32_e32 v2, 0x37800000, v1128; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo129; GCN-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260130; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo131; GCN-NEXT: v_rcp_f32_e32 v0, v0132; GCN-NEXT: ; return to shader part epilog133.entry:134 %a = call contract float @llvm.sqrt.f32(float %arg1)135 %b = fdiv afn contract float 1.000000e+00, %a136 ret float %b137}138 139define amdgpu_cs float @sqrt_div_contract(float inreg %arg1) {140; GCN-LABEL: sqrt_div_contract:141; GCN: ; %bb.0: ; %.entry142; GCN-NEXT: v_rcp_f32_e32 v0, s0143; GCN-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0144; GCN-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0145; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo146; GCN-NEXT: v_sqrt_f32_e32 v1, v0147; GCN-NEXT: v_add_nc_u32_e32 v2, -1, v1148; GCN-NEXT: v_add_nc_u32_e32 v3, 1, v1149; GCN-NEXT: v_fma_f32 v4, -v2, v1, v0150; GCN-NEXT: v_fma_f32 v5, -v3, v1, v0151; GCN-NEXT: v_cmp_ge_f32_e64 s0, 0, v4152; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s0153; GCN-NEXT: v_cmp_lt_f32_e64 s0, 0, v5154; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0155; GCN-NEXT: v_mul_f32_e32 v2, 0x37800000, v1156; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo157; GCN-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260158; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo159; GCN-NEXT: ; return to shader part epilog160.entry:161 %a = fdiv afn contract float 1.000000e+00, %arg1162 %b = call contract float @llvm.sqrt.f32(float %a)163 ret float %b164}165 166define amdgpu_cs float @rcp_sqrt_contract(float inreg %arg1) {167; GCN-LABEL: rcp_sqrt_contract:168; GCN: ; %bb.0: ; %.entry169; GCN-NEXT: v_mul_f32_e64 v0, 0x4f800000, s0170; GCN-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0xf800000, s0171; GCN-NEXT: v_cndmask_b32_e32 v0, s0, v0, vcc_lo172; GCN-NEXT: v_sqrt_f32_e32 v1, v0173; GCN-NEXT: v_add_nc_u32_e32 v2, -1, v1174; GCN-NEXT: v_add_nc_u32_e32 v3, 1, v1175; GCN-NEXT: v_fma_f32 v4, -v2, v1, v0176; GCN-NEXT: v_fma_f32 v5, -v3, v1, v0177; GCN-NEXT: v_cmp_ge_f32_e64 s0, 0, v4178; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s0179; GCN-NEXT: v_cmp_lt_f32_e64 s0, 0, v5180; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0181; GCN-NEXT: v_mul_f32_e32 v2, 0x37800000, v1182; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo183; GCN-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260184; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo185; GCN-NEXT: v_rcp_f32_e32 v0, v0186; GCN-NEXT: ; return to shader part epilog187.entry:188 %a = call contract float @llvm.sqrt.f32(float %arg1)189 %b = call contract float @llvm.amdgcn.rcp.f32(float %a)190 ret float %b191}192 193define amdgpu_cs float @sqrt_rcp_contract(float inreg %arg1) {194; GCN-LABEL: sqrt_rcp_contract:195; GCN: ; %bb.0: ; %.entry196; GCN-NEXT: v_rcp_f32_e32 v0, s0197; GCN-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0198; GCN-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0199; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo200; GCN-NEXT: v_sqrt_f32_e32 v1, v0201; GCN-NEXT: v_add_nc_u32_e32 v2, -1, v1202; GCN-NEXT: v_add_nc_u32_e32 v3, 1, v1203; GCN-NEXT: v_fma_f32 v4, -v2, v1, v0204; GCN-NEXT: v_fma_f32 v5, -v3, v1, v0205; GCN-NEXT: v_cmp_ge_f32_e64 s0, 0, v4206; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s0207; GCN-NEXT: v_cmp_lt_f32_e64 s0, 0, v5208; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0209; GCN-NEXT: v_mul_f32_e32 v2, 0x37800000, v1210; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo211; GCN-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260212; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo213; GCN-NEXT: ; return to shader part epilog214.entry:215 %a = call contract float @llvm.amdgcn.rcp.f32(float %arg1)216 %b = call contract float @llvm.sqrt.f32(float %a)217 ret float %b218}219 220declare float @llvm.sqrt.f32(float)221declare float @llvm.amdgcn.rcp.f32(float)222