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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn < %s | FileCheck %s3 4define amdgpu_cs i32 @test_shl_1(i32 inreg %arg1) {5; CHECK-LABEL: test_shl_1:6; CHECK: ; %bb.0: ; %.entry7; CHECK-NEXT: s_lshl_b32 s0, s0, 58; CHECK-NEXT: ; return to shader part epilog9.entry:10 %z1 = shl i32 %arg1, 211 %z2 = shl i32 %z1, 312 ret i32 %z213}14 15define amdgpu_cs i32 @test_shl_2(i32 inreg %arg1) {16; CHECK-LABEL: test_shl_2:17; CHECK: ; %bb.0: ; %.entry18; CHECK-NEXT: s_lshl_b32 s0, s0, 1019; CHECK-NEXT: ; return to shader part epilog20.entry:21 %z1 = shl i32 %arg1, 122 %z2 = shl i32 %z1, 223 %z3 = shl i32 %z2, 324 %z4 = shl i32 %z3, 425 ret i32 %z426}27 28define amdgpu_cs i32 @test_shl_i32(i32 inreg %arg1) {29; CHECK-LABEL: test_shl_i32:30; CHECK: ; %bb.0: ; %.entry31; CHECK-NEXT: s_mov_b32 s0, 032; CHECK-NEXT: ; return to shader part epilog33.entry:34 %z1 = shl i32 %arg1, 1035 %z2 = shl i32 %z1, 1036 %z3 = shl i32 %z2, 1037 %z4 = shl i32 %z3, 1038 ret i32 %z439}40 41define amdgpu_cs i64 @test_shl_i64(i64 inreg %arg1) {42; CHECK-LABEL: test_shl_i64:43; CHECK: ; %bb.0: ; %.entry44; CHECK-NEXT: s_mov_b32 s0, 045; CHECK-NEXT: s_mov_b32 s1, 046; CHECK-NEXT: ; return to shader part epilog47.entry:48 %z1 = shl i64 %arg1, 1049 %z2 = shl i64 %z1, 1050 %z3 = shl i64 %z2, 1051 %z4 = shl i64 %z3, 1052 %z5 = shl i64 %z4, 1053 %z6 = shl i64 %z5, 1054 %z7 = shl i64 %z6, 1055 ret i64 %z756}57 58define amdgpu_cs i32 @test_ashr_1(i32 inreg %arg1) {59; CHECK-LABEL: test_ashr_1:60; CHECK: ; %bb.0: ; %.entry61; CHECK-NEXT: s_ashr_i32 s0, s0, 562; CHECK-NEXT: ; return to shader part epilog63.entry:64 %z1 = ashr i32 %arg1, 265 %z2 = ashr i32 %z1, 366 ret i32 %z267}68 69define amdgpu_cs i32 @test_ashr_2(i32 inreg %arg1) {70; CHECK-LABEL: test_ashr_2:71; CHECK: ; %bb.0: ; %.entry72; CHECK-NEXT: s_ashr_i32 s0, s0, 1073; CHECK-NEXT: ; return to shader part epilog74.entry:75 %z1 = ashr i32 %arg1, 176 %z2 = ashr i32 %z1, 277 %z3 = ashr i32 %z2, 378 %z4 = ashr i32 %z3, 479 ret i32 %z480}81 82define amdgpu_cs i32 @test_ashr_i32(i32 inreg %arg1) {83; CHECK-LABEL: test_ashr_i32:84; CHECK: ; %bb.0: ; %.entry85; CHECK-NEXT: s_ashr_i32 s0, s0, 3186; CHECK-NEXT: ; return to shader part epilog87.entry:88 %z1 = ashr i32 %arg1, 1089 %z2 = ashr i32 %z1, 1090 %z3 = ashr i32 %z2, 1091 %z4 = ashr i32 %z3, 1092 ret i32 %z493}94 95define amdgpu_cs i64 @test_ashr_i64(i64 inreg %arg1) {96; CHECK-LABEL: test_ashr_i64:97; CHECK: ; %bb.0: ; %.entry98; CHECK-NEXT: s_ashr_i32 s0, s1, 3199; CHECK-NEXT: s_mov_b32 s1, s0100; CHECK-NEXT: ; return to shader part epilog101.entry:102 %z1 = ashr i64 %arg1, 10103 %z2 = ashr i64 %z1, 10104 %z3 = ashr i64 %z2, 10105 %z4 = ashr i64 %z3, 10106 %z5 = ashr i64 %z4, 10107 %z6 = ashr i64 %z5, 10108 %z7 = ashr i64 %z6, 10109 ret i64 %z7110}111 112define amdgpu_cs i32 @test_lshr_1(i32 inreg %arg1) {113; CHECK-LABEL: test_lshr_1:114; CHECK: ; %bb.0: ; %.entry115; CHECK-NEXT: s_lshr_b32 s0, s0, 5116; CHECK-NEXT: ; return to shader part epilog117.entry:118 %z1 = lshr i32 %arg1, 2119 %z2 = lshr i32 %z1, 3120 ret i32 %z2121}122 123define amdgpu_cs i32 @test_lshr_2(i32 inreg %arg1) {124; CHECK-LABEL: test_lshr_2:125; CHECK: ; %bb.0: ; %.entry126; CHECK-NEXT: s_lshr_b32 s0, s0, 10127; CHECK-NEXT: ; return to shader part epilog128.entry:129 %z1 = lshr i32 %arg1, 1130 %z2 = lshr i32 %z1, 2131 %z3 = lshr i32 %z2, 3132 %z4 = lshr i32 %z3, 4133 ret i32 %z4134}135 136define amdgpu_cs i32 @test_lshr_i32(i32 inreg %arg1) {137; CHECK-LABEL: test_lshr_i32:138; CHECK: ; %bb.0: ; %.entry139; CHECK-NEXT: s_mov_b32 s0, 0140; CHECK-NEXT: ; return to shader part epilog141.entry:142 %z1 = lshr i32 %arg1, 10143 %z2 = lshr i32 %z1, 10144 %z3 = lshr i32 %z2, 10145 %z4 = lshr i32 %z3, 10146 ret i32 %z4147}148 149define amdgpu_cs i64 @test_lshr_i64(i64 inreg %arg1) {150; CHECK-LABEL: test_lshr_i64:151; CHECK: ; %bb.0: ; %.entry152; CHECK-NEXT: s_mov_b32 s0, 0153; CHECK-NEXT: s_mov_b32 s1, 0154; CHECK-NEXT: ; return to shader part epilog155.entry:156 %z1 = lshr i64 %arg1, 10157 %z2 = lshr i64 %z1, 10158 %z3 = lshr i64 %z2, 10159 %z4 = lshr i64 %z3, 10160 %z5 = lshr i64 %z4, 10161 %z6 = lshr i64 %z5, 10162 %z7 = lshr i64 %z6, 10163 ret i64 %z7164}165