344 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn < %s | FileCheck %s3 4define amdgpu_cs i32 @test_shl_and_1(i32 inreg %arg1) {5; CHECK-LABEL: test_shl_and_1:6; CHECK: ; %bb.0: ; %.entry7; CHECK-NEXT: s_lshl_b32 s0, s0, 48; CHECK-NEXT: ; return to shader part epilog9.entry:10 %z1 = shl i32 %arg1, 211 %z2 = and i32 %z1, 107374182012 %z3 = shl i32 %z2, 213 ret i32 %z314}15 16define amdgpu_cs i32 @test_shl_and_2(i32 inreg %arg1) {17; CHECK-LABEL: test_shl_and_2:18; CHECK: ; %bb.0: ; %.entry19; CHECK-NEXT: s_lshl_b32 s0, s0, 820; CHECK-NEXT: ; return to shader part epilog21.entry:22 %z1 = shl i32 %arg1, 523 %z2 = and i32 %z1, 53687088024 %z3 = shl i32 %z2, 325 ret i32 %z326}27 28define amdgpu_cs i32 @test_shl_and_3(i32 inreg %arg1) {29; CHECK-LABEL: test_shl_and_3:30; CHECK: ; %bb.0: ; %.entry31; CHECK-NEXT: s_lshl_b32 s0, s0, 532; CHECK-NEXT: s_and_b32 s0, s0, 0x7ffffff033; CHECK-NEXT: ; return to shader part epilog34.entry:35 %z1 = shl i32 %arg1, 336 %z2 = and i32 %z1, 53687090837 %z3 = shl i32 %z2, 238 ret i32 %z339}40 41define amdgpu_cs i32 @test_lshr_and_1(i32 inreg %arg1) {42; CHECK-LABEL: test_lshr_and_1:43; CHECK: ; %bb.0: ; %.entry44; CHECK-NEXT: s_lshr_b32 s0, s0, 445; CHECK-NEXT: ; return to shader part epilog46.entry:47 %z1 = lshr i32 %arg1, 248 %z2 = and i32 %z1, 107374182049 %z3 = lshr i32 %z2, 250 ret i32 %z351}52 53define amdgpu_cs i32 @test_lshr_and_2(i32 inreg %arg1) {54; CHECK-LABEL: test_lshr_and_2:55; CHECK: ; %bb.0: ; %.entry56; CHECK-NEXT: s_lshr_b32 s0, s0, 857; CHECK-NEXT: s_and_b32 s0, s0, 0x3fffffc58; CHECK-NEXT: ; return to shader part epilog59.entry:60 %z1 = lshr i32 %arg1, 561 %z2 = and i32 %z1, 53687088062 %z3 = lshr i32 %z2, 363 ret i32 %z364}65 66define amdgpu_cs i32 @test_lshr_and_3(i32 inreg %arg1) {67; CHECK-LABEL: test_lshr_and_3:68; CHECK: ; %bb.0: ; %.entry69; CHECK-NEXT: s_lshr_b32 s0, s0, 570; CHECK-NEXT: ; return to shader part epilog71.entry:72 %z1 = lshr i32 %arg1, 373 %z2 = and i32 %z1, 53687090874 %z3 = lshr i32 %z2, 275 ret i32 %z376}77 78define amdgpu_cs i32 @test_ashr_and_1(i32 inreg %arg1) {79; CHECK-LABEL: test_ashr_and_1:80; CHECK: ; %bb.0: ; %.entry81; CHECK-NEXT: s_ashr_i32 s0, s0, 482; CHECK-NEXT: s_and_b32 s0, s0, 0xfffffff83; CHECK-NEXT: ; return to shader part epilog84.entry:85 %z1 = ashr i32 %arg1, 286 %z2 = and i32 %z1, 107374182087 %z3 = ashr i32 %z2, 288 ret i32 %z389}90 91define amdgpu_cs i32 @test_ashr_and_2(i32 inreg %arg1) {92; CHECK-LABEL: test_ashr_and_2:93; CHECK: ; %bb.0: ; %.entry94; CHECK-NEXT: s_ashr_i32 s0, s0, 895; CHECK-NEXT: s_and_b32 s0, s0, 0x3fffffc96; CHECK-NEXT: ; return to shader part epilog97.entry:98 %z1 = ashr i32 %arg1, 599 %z2 = and i32 %z1, 536870880100 %z3 = ashr i32 %z2, 3101 ret i32 %z3102}103 104define amdgpu_cs i32 @test_ashr_and_3(i32 inreg %arg1) {105; CHECK-LABEL: test_ashr_and_3:106; CHECK: ; %bb.0: ; %.entry107; CHECK-NEXT: s_ashr_i32 s0, s0, 5108; CHECK-NEXT: s_and_b32 s0, s0, 0x7ffffff109; CHECK-NEXT: ; return to shader part epilog110.entry:111 %z1 = ashr i32 %arg1, 3112 %z2 = and i32 %z1, 536870908113 %z3 = ashr i32 %z2, 2114 ret i32 %z3115}116 117define amdgpu_cs i32 @test_shl_or_1(i32 inreg %arg1) {118; CHECK-LABEL: test_shl_or_1:119; CHECK: ; %bb.0: ; %.entry120; CHECK-NEXT: s_lshl_b32 s0, s0, 4121; CHECK-NEXT: s_or_b32 s0, s0, 12122; CHECK-NEXT: ; return to shader part epilog123.entry:124 %z1 = shl i32 %arg1, 2125 %z2 = or i32 %z1, 3221225475126 %z3 = shl i32 %z2, 2127 ret i32 %z3128}129 130define amdgpu_cs i32 @test_shl_or_2(i32 inreg %arg1) {131; CHECK-LABEL: test_shl_or_2:132; CHECK: ; %bb.0: ; %.entry133; CHECK-NEXT: s_lshl_b32 s0, s0, 8134; CHECK-NEXT: s_or_b32 s0, s0, 0xfffffc00135; CHECK-NEXT: ; return to shader part epilog136.entry:137 %z1 = shl i32 %arg1, 3138 %z2 = or i32 %z1, 536870880139 %z3 = shl i32 %z2, 5140 ret i32 %z3141}142 143define amdgpu_cs i32 @test_shl_or_3(i32 inreg %arg1) {144; CHECK-LABEL: test_shl_or_3:145; CHECK: ; %bb.0: ; %.entry146; CHECK-NEXT: s_lshl_b32 s0, s0, 5147; CHECK-NEXT: s_or_b32 s0, s0, 0x7fffff80148; CHECK-NEXT: ; return to shader part epilog149.entry:150 %z1 = shl i32 %arg1, 2151 %z2 = or i32 %z1, 268435440152 %z3 = shl i32 %z2, 3153 ret i32 %z3154}155 156define amdgpu_cs i32 @test_lshr_or_1(i32 inreg %arg1) {157; CHECK-LABEL: test_lshr_or_1:158; CHECK: ; %bb.0: ; %.entry159; CHECK-NEXT: s_lshr_b32 s0, s0, 4160; CHECK-NEXT: ; return to shader part epilog161.entry:162 %z1 = lshr i32 %arg1, 2163 %z2 = or i32 %z1, 3164 %z3 = lshr i32 %z2, 2165 ret i32 %z3166}167 168define amdgpu_cs i32 @test_lshr_or_2(i32 inreg %arg1) {169; CHECK-LABEL: test_lshr_or_2:170; CHECK: ; %bb.0: ; %.entry171; CHECK-NEXT: s_mov_b32 s0, 0xffffff172; CHECK-NEXT: ; return to shader part epilog173.entry:174 %z1 = lshr i32 %arg1, 3175 %z2 = or i32 %z1, 536870880176 %z3 = lshr i32 %z2, 5177 ret i32 %z3178}179 180define amdgpu_cs i32 @test_lshr_or_3(i32 inreg %arg1) {181; CHECK-LABEL: test_lshr_or_3:182; CHECK: ; %bb.0: ; %.entry183; CHECK-NEXT: s_lshr_b32 s0, s0, 5184; CHECK-NEXT: s_or_b32 s0, s0, 0x1fffffe185; CHECK-NEXT: ; return to shader part epilog186.entry:187 %z1 = lshr i32 %arg1, 2188 %z2 = or i32 %z1, 268435440189 %z3 = lshr i32 %z2, 3190 ret i32 %z3191}192 193define amdgpu_cs i32 @test_ashr_or_1(i32 inreg %arg1) {194; CHECK-LABEL: test_ashr_or_1:195; CHECK: ; %bb.0: ; %.entry196; CHECK-NEXT: s_ashr_i32 s0, s0, 4197; CHECK-NEXT: ; return to shader part epilog198.entry:199 %z1 = ashr i32 %arg1, 2200 %z2 = or i32 %z1, 3201 %z3 = ashr i32 %z2, 2202 ret i32 %z3203}204 205define amdgpu_cs i32 @test_ashr_or_2(i32 inreg %arg1) {206; CHECK-LABEL: test_ashr_or_2:207; CHECK: ; %bb.0: ; %.entry208; CHECK-NEXT: s_ashr_i32 s0, s0, 8209; CHECK-NEXT: s_or_b32 s0, s0, 0xffffff210; CHECK-NEXT: ; return to shader part epilog211.entry:212 %z1 = ashr i32 %arg1, 3213 %z2 = or i32 %z1, 536870880214 %z3 = ashr i32 %z2, 5215 ret i32 %z3216}217 218define amdgpu_cs i32 @test_ashr_or_3(i32 inreg %arg1) {219; CHECK-LABEL: test_ashr_or_3:220; CHECK: ; %bb.0: ; %.entry221; CHECK-NEXT: s_ashr_i32 s0, s0, 5222; CHECK-NEXT: s_or_b32 s0, s0, 0x1fffffe223; CHECK-NEXT: ; return to shader part epilog224.entry:225 %z1 = ashr i32 %arg1, 2226 %z2 = or i32 %z1, 268435440227 %z3 = ashr i32 %z2, 3228 ret i32 %z3229}230 231define amdgpu_cs i32 @test_shl_xor_1(i32 inreg %arg1) {232; CHECK-LABEL: test_shl_xor_1:233; CHECK: ; %bb.0: ; %.entry234; CHECK-NEXT: s_lshl_b32 s0, s0, 4235; CHECK-NEXT: s_xor_b32 s0, s0, -16236; CHECK-NEXT: ; return to shader part epilog237.entry:238 %z1 = shl i32 %arg1, 2239 %z2 = xor i32 %z1, 1073741820240 %z3 = shl i32 %z2, 2241 ret i32 %z3242}243 244define amdgpu_cs i32 @test_shl_xor_2(i32 inreg %arg1) {245; CHECK-LABEL: test_shl_xor_2:246; CHECK: ; %bb.0: ; %.entry247; CHECK-NEXT: s_lshl_b32 s0, s0, 6248; CHECK-NEXT: ; return to shader part epilog249.entry:250 %z1 = shl i32 %arg1, 1251 %z2 = xor i32 %z1, 4160749568252 %z3 = shl i32 %z2, 5253 ret i32 %z3254}255 256define amdgpu_cs i32 @test_shl_xor_3(i32 inreg %arg1) {257; CHECK-LABEL: test_shl_xor_3:258; CHECK: ; %bb.0: ; %.entry259; CHECK-NEXT: s_lshl_b32 s0, s0, 5260; CHECK-NEXT: s_xor_b32 s0, s0, 56261; CHECK-NEXT: ; return to shader part epilog262.entry:263 %z1 = shl i32 %arg1, 2264 %z2 = xor i32 %z1, 3221225479265 %z3 = shl i32 %z2, 3266 ret i32 %z3267}268 269define amdgpu_cs i32 @test_lshr_xor_1(i32 inreg %arg1) {270; CHECK-LABEL: test_lshr_xor_1:271; CHECK: ; %bb.0: ; %.entry272; CHECK-NEXT: s_lshr_b32 s0, s0, 4273; CHECK-NEXT: s_xor_b32 s0, s0, 0xfffffff274; CHECK-NEXT: ; return to shader part epilog275.entry:276 %z1 = lshr i32 %arg1, 2277 %z2 = xor i32 %z1, 1073741820278 %z3 = lshr i32 %z2, 2279 ret i32 %z3280}281 282define amdgpu_cs i32 @test_lshr_xor_2(i32 inreg %arg1) {283; CHECK-LABEL: test_lshr_xor_2:284; CHECK: ; %bb.0: ; %.entry285; CHECK-NEXT: s_lshr_b32 s0, s0, 6286; CHECK-NEXT: ; return to shader part epilog287.entry:288 %z1 = lshr i32 %arg1, 1289 %z2 = xor i32 %z1, 31290 %z3 = lshr i32 %z2, 5291 ret i32 %z3292}293 294define amdgpu_cs i32 @test_lshr_xor_3(i32 inreg %arg1) {295; CHECK-LABEL: test_lshr_xor_3:296; CHECK: ; %bb.0: ; %.entry297; CHECK-NEXT: s_lshr_b32 s0, s0, 5298; CHECK-NEXT: s_xor_b32 s0, s0, 0x18000000299; CHECK-NEXT: ; return to shader part epilog300.entry:301 %z1 = lshr i32 %arg1, 2302 %z2 = xor i32 %z1, 3221225479303 %z3 = lshr i32 %z2, 3304 ret i32 %z3305}306 307define amdgpu_cs i32 @test_ashr_xor_1(i32 inreg %arg1) {308; CHECK-LABEL: test_ashr_xor_1:309; CHECK: ; %bb.0: ; %.entry310; CHECK-NEXT: s_ashr_i32 s0, s0, 4311; CHECK-NEXT: s_xor_b32 s0, s0, 0xfffffff312; CHECK-NEXT: ; return to shader part epilog313.entry:314 %z1 = ashr i32 %arg1, 2315 %z2 = xor i32 %z1, 1073741820316 %z3 = ashr i32 %z2, 2317 ret i32 %z3318}319 320define amdgpu_cs i32 @test_ashr_xor_2(i32 inreg %arg1) {321; CHECK-LABEL: test_ashr_xor_2:322; CHECK: ; %bb.0: ; %.entry323; CHECK-NEXT: s_ashr_i32 s0, s0, 6324; CHECK-NEXT: ; return to shader part epilog325.entry:326 %z1 = ashr i32 %arg1, 1327 %z2 = xor i32 %z1, 31328 %z3 = ashr i32 %z2, 5329 ret i32 %z3330}331 332define amdgpu_cs i32 @test_ashr_xor_3(i32 inreg %arg1) {333; CHECK-LABEL: test_ashr_xor_3:334; CHECK: ; %bb.0: ; %.entry335; CHECK-NEXT: s_ashr_i32 s0, s0, 5336; CHECK-NEXT: s_xor_b32 s0, s0, 0xf8000000337; CHECK-NEXT: ; return to shader part epilog338.entry:339 %z1 = ashr i32 %arg1, 2340 %z2 = xor i32 %z1, 3221225479341 %z3 = ashr i32 %z2, 3342 ret i32 %z3343}344