209 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner %s -o - | FileCheck %s3 4---5name: combine_ashr6tracksRegLiveness: true7body: |8 bb.0:9 liveins: $vgpr0, $vgpr1, $vgpr3110 11 liveins: $vgpr0, $vgpr112 13 ; CHECK-LABEL: name: combine_ashr14 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr115 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr017 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr118 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)19 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 020 ; CHECK-NEXT: G_STORE [[C]](s32), [[MV]](p0) :: (store (s32))21 ; CHECK-NEXT: SI_RETURN22 %0:_(s32) = COPY $vgpr023 %1:_(s32) = COPY $vgpr124 %2:_(p0) = G_MERGE_VALUES %0(s32), %1(s32)25 %3:_(s32) = G_CONSTANT i32 1026 %4:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)27 %5:_(s32) = G_ASHR %4, %3(s32)28 G_STORE %5(s32), %2(p0) :: (store (s32))29 SI_RETURN30 31...32---33name: combine_lshr34tracksRegLiveness: true35body: |36 bb.0:37 liveins: $vgpr0, $vgpr1, $vgpr3138 39 liveins: $vgpr0, $vgpr140 41 ; CHECK-LABEL: name: combine_lshr42 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr143 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr045 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr146 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)47 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 048 ; CHECK-NEXT: G_STORE [[C]](s32), [[MV]](p0) :: (store (s32))49 ; CHECK-NEXT: SI_RETURN50 %0:_(s32) = COPY $vgpr051 %1:_(s32) = COPY $vgpr152 %2:_(p0) = G_MERGE_VALUES %0(s32), %1(s32)53 %3:_(s32) = G_CONSTANT i32 1054 %4:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)55 %5:_(s32) = G_LSHR %4, %3(s32)56 G_STORE %5(s32), %2(p0) :: (store (s32))57 SI_RETURN58 59...60---61name: combine_shl62tracksRegLiveness: true63body: |64 bb.0:65 liveins: $vgpr0, $vgpr1, $vgpr3166 67 liveins: $vgpr0, $vgpr168 69 ; CHECK-LABEL: name: combine_shl70 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr171 ; CHECK-NEXT: {{ $}}72 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr073 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr174 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)75 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 076 ; CHECK-NEXT: G_STORE [[C]](s32), [[MV]](p0) :: (store (s32))77 ; CHECK-NEXT: SI_RETURN78 %0:_(s32) = COPY $vgpr079 %1:_(s32) = COPY $vgpr180 %2:_(p0) = G_MERGE_VALUES %0(s32), %1(s32)81 %3:_(s32) = G_CONSTANT i32 1682 %4:_(s32) = G_CONSTANT i32 429490176083 %5:_(s32) = G_SHL %4, %3(s32)84 G_STORE %5(s32), %2(p0) :: (store (s32))85 SI_RETURN86 87...88---89name: combine_ashr290tracksRegLiveness: true91body: |92 bb.0:93 liveins: $vgpr0, $vgpr1, $vgpr3194 95 liveins: $vgpr0, $vgpr196 97 ; CHECK-LABEL: name: combine_ashr298 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr199 ; CHECK-NEXT: {{ $}}100 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0101 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1102 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)103 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1104 ; CHECK-NEXT: G_STORE [[C]](s8), [[MV]](p0) :: (store (s8))105 ; CHECK-NEXT: SI_RETURN106 %0:_(s32) = COPY $vgpr0107 %1:_(s32) = COPY $vgpr1108 %2:_(p0) = G_MERGE_VALUES %0(s32), %1(s32)109 %3:_(s32) = G_CONSTANT i32 1110 %4:_(s8) = G_CONSTANT i8 -2111 %5:_(s8) = G_ASHR %4, %3(s32)112 G_STORE %5(s8), %2(p0) :: (store (s8))113 SI_RETURN114 115...116---117name: combine_vector_lshr118tracksRegLiveness: true119body: |120 bb.0:121 liveins: $vgpr0, $vgpr1, $vgpr31122 123 liveins: $vgpr0, $vgpr1124 125 ; CHECK-LABEL: name: combine_vector_lshr126 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1127 ; CHECK-NEXT: {{ $}}128 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0129 ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)130 ; CHECK-NEXT: $vgpr1 = COPY [[C]](s32)131 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1132 %0:_(<2 x s32>) = G_IMPLICIT_DEF133 %1:_(s32) = G_CONSTANT i32 511134 %2:_(s32) = G_CONSTANT i32 0135 %3:_(s32) = G_CONSTANT i32 1136 %4:_(s32) = G_CONSTANT i32 9137 %5:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)138 %6:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1(s32), %2(s32)139 %7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %6, %1(s32), %3(s32)140 %8:_(<2 x s32>) = G_LSHR %7, %5(<2 x s32>)141 %9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(<2 x s32>)142 $vgpr0 = COPY %9(s32)143 $vgpr1 = COPY %10(s32)144 SI_RETURN implicit $vgpr0, implicit $vgpr1145 146...147---148name: combine_vector_shl149tracksRegLiveness: true150body: |151 bb.0:152 liveins: $vgpr0, $vgpr1, $vgpr31153 154 liveins: $vgpr0, $vgpr1155 156 ; CHECK-LABEL: name: combine_vector_shl157 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0160 ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)161 ; CHECK-NEXT: $vgpr1 = COPY [[C]](s32)162 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1163 %0:_(<2 x s32>) = G_IMPLICIT_DEF164 %1:_(s32) = G_CONSTANT i32 4294901760165 %2:_(s32) = G_CONSTANT i32 0166 %3:_(s32) = G_CONSTANT i32 1167 %4:_(s32) = G_CONSTANT i32 16168 %5:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)169 %6:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1(s32), %2(s32)170 %7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %6, %1(s32), %3(s32)171 %8:_(<2 x s32>) = G_SHL %7, %5(<2 x s32>)172 %9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(<2 x s32>)173 $vgpr0 = COPY %9(s32)174 $vgpr1 = COPY %10(s32)175 SI_RETURN implicit $vgpr0, implicit $vgpr1176 177...178---179name: combine_vector_ashr180tracksRegLiveness: true181body: |182 bb.0:183 liveins: $vgpr0, $vgpr1, $vgpr31184 185 liveins: $vgpr0, $vgpr1186 187 ; CHECK-LABEL: name: combine_vector_ashr188 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1189 ; CHECK-NEXT: {{ $}}190 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1191 ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)192 ; CHECK-NEXT: $vgpr1 = COPY [[C]](s32)193 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1194 %0:_(<2 x s32>) = G_IMPLICIT_DEF195 %1:_(s32) = G_CONSTANT i32 -1196 %2:_(s32) = G_CONSTANT i32 0197 %3:_(s32) = G_CONSTANT i32 1198 %4:_(s32) = G_CONSTANT i32 1199 %5:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)200 %6:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1(s32), %2(s32)201 %7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %6, %1(s32), %3(s32)202 %8:_(<2 x s32>) = G_ASHR %7, %5(<2 x s32>)203 %9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(<2 x s32>)204 $vgpr0 = COPY %9(s32)205 $vgpr1 = COPY %10(s32)206 SI_RETURN implicit $vgpr0, implicit $vgpr1207 208...209