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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3 4 5---6name: narrow_shl_s64_32_s64amt7tracksRegLiveness: true8body: |9 bb.0:10 liveins: $vgpr0_vgpr111 12 ; CHECK-LABEL: name: narrow_shl_s64_32_s64amt13 ; CHECK: liveins: $vgpr0_vgpr114 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr116 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)17 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 018 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[TRUNC]](s32)19 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)20 %0:_(s64) = COPY $vgpr0_vgpr121 %1:_(s64) = G_CONSTANT i64 3222 %2:_(s64) = G_SHL %0, %123 $vgpr0_vgpr1 = COPY %224...25 26---27name: narrow_shl_s64_3228tracksRegLiveness: true29body: |30 bb.0:31 liveins: $vgpr0_vgpr132 33 ; CHECK-LABEL: name: narrow_shl_s64_3234 ; CHECK: liveins: $vgpr0_vgpr135 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr137 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)38 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 039 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[TRUNC]](s32)40 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)41 %0:_(s64) = COPY $vgpr0_vgpr142 %1:_(s32) = G_CONSTANT i32 3243 %2:_(s64) = G_SHL %0, %144 $vgpr0_vgpr1 = COPY %245...46 47---48name: narrow_shl_s64_3349tracksRegLiveness: true50body: |51 bb.0:52 liveins: $vgpr0_vgpr153 54 ; CHECK-LABEL: name: narrow_shl_s64_3355 ; CHECK: liveins: $vgpr0_vgpr156 ; CHECK-NEXT: {{ $}}57 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr158 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)59 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 160 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)61 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 062 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[SHL]](s32)63 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)64 %0:_(s64) = COPY $vgpr0_vgpr165 %1:_(s32) = G_CONSTANT i32 3366 %2:_(s64) = G_SHL %0, %167 $vgpr0_vgpr1 = COPY %268...69 70---71name: narrow_shl_s64_3172tracksRegLiveness: true73body: |74 bb.0:75 liveins: $vgpr0_vgpr176 77 ; CHECK-LABEL: name: narrow_shl_s64_3178 ; CHECK: liveins: $vgpr0_vgpr179 ; CHECK-NEXT: {{ $}}80 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr181 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3182 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32)83 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64)84 %0:_(s64) = COPY $vgpr0_vgpr185 %1:_(s32) = G_CONSTANT i32 3186 %2:_(s64) = G_SHL %0, %187 $vgpr0_vgpr1 = COPY %288...89 90---91name: narrow_shl_s64_6392tracksRegLiveness: true93body: |94 bb.0:95 liveins: $vgpr0_vgpr196 97 ; CHECK-LABEL: name: narrow_shl_s64_6398 ; CHECK: liveins: $vgpr0_vgpr199 ; CHECK-NEXT: {{ $}}100 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1101 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)102 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31103 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)104 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0105 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[SHL]](s32)106 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)107 %0:_(s64) = COPY $vgpr0_vgpr1108 %1:_(s32) = G_CONSTANT i32 63109 %2:_(s64) = G_SHL %0, %1110 $vgpr0_vgpr1 = COPY %2111...112 113---114name: narrow_shl_s64_64115tracksRegLiveness: true116body: |117 bb.0:118 liveins: $vgpr0_vgpr1119 120 ; CHECK-LABEL: name: narrow_shl_s64_64121 ; CHECK: liveins: $vgpr0_vgpr1122 ; CHECK-NEXT: {{ $}}123 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF124 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[DEF]](s64)125 %0:_(s64) = COPY $vgpr0_vgpr1126 %1:_(s32) = G_CONSTANT i32 64127 %2:_(s64) = G_SHL %0, %1128 $vgpr0_vgpr1 = COPY %2129...130 131---132name: narrow_shl_s64_65133tracksRegLiveness: true134body: |135 bb.0:136 liveins: $vgpr0_vgpr1137 138 ; CHECK-LABEL: name: narrow_shl_s64_65139 ; CHECK: liveins: $vgpr0_vgpr1140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF142 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[DEF]](s64)143 %0:_(s64) = COPY $vgpr0_vgpr1144 %1:_(s32) = G_CONSTANT i32 65145 %2:_(s64) = G_SHL %0, %1146 $vgpr0_vgpr1 = COPY %2147...148 149---150name: narrow_shl_s32_16151tracksRegLiveness: true152body: |153 bb.0:154 liveins: $vgpr0155 156 ; CHECK-LABEL: name: narrow_shl_s32_16157 ; CHECK: liveins: $vgpr0158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0160 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16161 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)162 ; CHECK-NEXT: $vgpr0 = COPY [[SHL]](s32)163 %0:_(s32) = COPY $vgpr0164 %1:_(s32) = G_CONSTANT i32 16165 %2:_(s32) = G_SHL %0, %1166 $vgpr0 = COPY %2167...168 169---170name: narrow_shl_s32_17171tracksRegLiveness: true172body: |173 bb.0:174 liveins: $vgpr0175 176 ; CHECK-LABEL: name: narrow_shl_s32_17177 ; CHECK: liveins: $vgpr0178 ; CHECK-NEXT: {{ $}}179 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0180 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17181 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)182 ; CHECK-NEXT: $vgpr0 = COPY [[SHL]](s32)183 %0:_(s32) = COPY $vgpr0184 %1:_(s32) = G_CONSTANT i32 17185 %2:_(s32) = G_SHL %0, %1186 $vgpr0 = COPY %2187...188 189---190name: narrow_shl_v2s32_17191tracksRegLiveness: true192body: |193 bb.0:194 liveins: $vgpr0_vgpr1195 196 ; CHECK-LABEL: name: narrow_shl_v2s32_17197 ; CHECK: liveins: $vgpr0_vgpr1198 ; CHECK-NEXT: {{ $}}199 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1200 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17201 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)202 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<2 x s32>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s32>)203 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](<2 x s32>)204 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1205 %1:_(s32) = G_CONSTANT i32 17206 %2:_(<2 x s32>) = G_BUILD_VECTOR %1, %1207 %3:_(<2 x s32>) = G_SHL %0, %2208 $vgpr0_vgpr1 = COPY %3209...210