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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s3 4---5name: urem_s32_var_const06tracksRegLiveness: true7body: |8 bb.0:9 liveins: $vgpr010 11 ; GCN-LABEL: name: urem_s32_var_const012 ; GCN: liveins: $vgpr013 ; GCN-NEXT: {{ $}}14 ; GCN-NEXT: %var:_(s32) = COPY $vgpr015 ; GCN-NEXT: %const:_(s32) = G_CONSTANT i32 016 ; GCN-NEXT: %rem:_(s32) = G_UREM %var, %const17 ; GCN-NEXT: $vgpr0 = COPY %rem(s32)18 %var:_(s32) = COPY $vgpr019 %const:_(s32) = G_CONSTANT i32 020 %rem:_(s32) = G_UREM %var, %const21 $vgpr0 = COPY %rem22...23 24---25name: urem_s32_var_const126tracksRegLiveness: true27body: |28 bb.0:29 liveins: $vgpr030 31 ; GCN-LABEL: name: urem_s32_var_const132 ; GCN: liveins: $vgpr033 ; GCN-NEXT: {{ $}}34 ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 035 ; GCN-NEXT: $vgpr0 = COPY [[C]](s32)36 %var:_(s32) = COPY $vgpr037 %const:_(s32) = G_CONSTANT i32 138 %rem:_(s32) = G_UREM %var, %const39 $vgpr0 = COPY %rem40...41 42---43name: urem_s32_var_const244tracksRegLiveness: true45body: |46 bb.0:47 liveins: $vgpr048 49 ; GCN-LABEL: name: urem_s32_var_const250 ; GCN: liveins: $vgpr051 ; GCN-NEXT: {{ $}}52 ; GCN-NEXT: %var:_(s32) = COPY $vgpr053 ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 154 ; GCN-NEXT: %rem:_(s32) = G_AND %var, [[C]]55 ; GCN-NEXT: $vgpr0 = COPY %rem(s32)56 %var:_(s32) = COPY $vgpr057 %const:_(s32) = G_CONSTANT i32 258 %rem:_(s32) = G_UREM %var, %const59 $vgpr0 = COPY %rem60...61 62---63name: urem_s32_var_shl164tracksRegLiveness: true65body: |66 bb.0:67 liveins: $vgpr0, $vgpr168 69 ; GCN-LABEL: name: urem_s32_var_shl170 ; GCN: liveins: $vgpr0, $vgpr171 ; GCN-NEXT: {{ $}}72 ; GCN-NEXT: %var:_(s32) = COPY $vgpr073 ; GCN-NEXT: %shift_amt:_(s32) = COPY $vgpr174 ; GCN-NEXT: %one:_(s32) = G_CONSTANT i32 175 ; GCN-NEXT: %one_bit:_(s32) = G_SHL %one, %shift_amt(s32)76 ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -177 ; GCN-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD %one_bit, [[C]]78 ; GCN-NEXT: %rem:_(s32) = G_AND %var, [[ADD]]79 ; GCN-NEXT: $vgpr0 = COPY %rem(s32)80 %var:_(s32) = COPY $vgpr081 %shift_amt:_(s32) = COPY $vgpr182 %one:_(s32) = G_CONSTANT i32 183 %one_bit:_(s32) = G_SHL %one, %shift_amt84 %rem:_(s32) = G_UREM %var, %one_bit85 $vgpr0 = COPY %rem86...87 88---89name: urem_s64_var_shl190tracksRegLiveness: true91body: |92 bb.0:93 liveins: $vgpr0_vgpr1, $vgpr294 95 ; GCN-LABEL: name: urem_s64_var_shl196 ; GCN: liveins: $vgpr0_vgpr1, $vgpr297 ; GCN-NEXT: {{ $}}98 ; GCN-NEXT: %var:_(s64) = COPY $vgpr0_vgpr199 ; GCN-NEXT: %shiftamt:_(s32) = COPY $vgpr2100 ; GCN-NEXT: %one:_(s64) = G_CONSTANT i64 1101 ; GCN-NEXT: %one_bit:_(s64) = G_SHL %one, %shiftamt(s32)102 ; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1103 ; GCN-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD %one_bit, [[C]]104 ; GCN-NEXT: %rem:_(s64) = G_AND %var, [[ADD]]105 ; GCN-NEXT: $vgpr0_vgpr1 = COPY %rem(s64)106 %var:_(s64) = COPY $vgpr0_vgpr1107 %shiftamt:_(s32) = COPY $vgpr2108 %one:_(s64) = G_CONSTANT i64 1109 %one_bit:_(s64) = G_SHL %one, %shiftamt110 %rem:_(s64) = G_UREM %var, %one_bit111 $vgpr0_vgpr1 = COPY %rem112...113 114---115name: urem_v2s32_var_shl1116tracksRegLiveness: true117body: |118 bb.0:119 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3120 121 ; GCN-LABEL: name: urem_v2s32_var_shl1122 ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3123 ; GCN-NEXT: {{ $}}124 ; GCN-NEXT: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1125 ; GCN-NEXT: %shift_amt:_(<2 x s32>) = COPY $vgpr2_vgpr3126 ; GCN-NEXT: %one:_(s32) = G_CONSTANT i32 1127 ; GCN-NEXT: %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one(s32), %one(s32)128 ; GCN-NEXT: %one_bit:_(<2 x s32>) = G_SHL %one_vec, %shift_amt(<2 x s32>)129 ; GCN-NEXT: %rem:_(<2 x s32>) = G_UREM %var, %one_bit130 ; GCN-NEXT: $vgpr0_vgpr1 = COPY %rem(<2 x s32>)131 %var:_(<2 x s32>) = COPY $vgpr0_vgpr1132 %shift_amt:_(<2 x s32>) = COPY $vgpr2_vgpr3133 %one:_(s32) = G_CONSTANT i32 1134 %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one, %one135 %one_bit:_(<2 x s32>) = G_SHL %one_vec, %shift_amt136 %rem:_(<2 x s32>) = G_UREM %var, %one_bit137 $vgpr0_vgpr1 = COPY %rem138...139 140---141name: urem_v2s16_var_const4_build_vector_trunc142tracksRegLiveness: true143body: |144 bb.0:145 liveins: $vgpr0, $vgpr1146 147 ; GCN-LABEL: name: urem_v2s16_var_const4_build_vector_trunc148 ; GCN: liveins: $vgpr0, $vgpr1149 ; GCN-NEXT: {{ $}}150 ; GCN-NEXT: %var:_(<2 x s16>) = COPY $vgpr0151 ; GCN-NEXT: %four:_(s32) = G_CONSTANT i32 4152 ; GCN-NEXT: %four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four(s32), %four(s32)153 ; GCN-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1154 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)155 ; GCN-NEXT: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD %four_vec, [[BUILD_VECTOR]]156 ; GCN-NEXT: %rem:_(<2 x s16>) = G_AND %var, [[ADD]]157 ; GCN-NEXT: $vgpr0 = COPY %rem(<2 x s16>)158 %var:_(<2 x s16>) = COPY $vgpr0159 %shift_amt:_(s32) = COPY $vgpr1160 %four:_(s32) = G_CONSTANT i32 4161 %four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four, %four162 %rem:_(<2 x s16>) = G_UREM %var, %four_vec163 $vgpr0 = COPY %rem164...165 166# The shl is a known power of two, but we do not know if the final167# value is a power of 2 due to the truncation.168---169name: urem_v2s16_var_nonconst_build_vector_trunc170tracksRegLiveness: true171body: |172 bb.0:173 liveins: $vgpr0, $vgpr1174 175 ; GCN-LABEL: name: urem_v2s16_var_nonconst_build_vector_trunc176 ; GCN: liveins: $vgpr0, $vgpr1177 ; GCN-NEXT: {{ $}}178 ; GCN-NEXT: %var:_(<2 x s16>) = COPY $vgpr0179 ; GCN-NEXT: %shift_amt:_(s32) = COPY $vgpr1180 ; GCN-NEXT: %two:_(s32) = G_CONSTANT i32 2181 ; GCN-NEXT: %four:_(s32) = G_CONSTANT i32 4182 ; GCN-NEXT: %shift:_(s32) = G_SHL %two, %shift_amt(s32)183 ; GCN-NEXT: %four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four(s32), %shift(s32)184 ; GCN-NEXT: %rem:_(<2 x s16>) = G_UREM %var, %four_vec185 ; GCN-NEXT: $vgpr0 = COPY %rem(<2 x s16>)186 %var:_(<2 x s16>) = COPY $vgpr0187 %shift_amt:_(s32) = COPY $vgpr1188 %two:_(s32) = G_CONSTANT i32 2189 %four:_(s32) = G_CONSTANT i32 4190 %shift:_(s32) = G_SHL %two, %shift_amt191 %four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four, %shift192 %rem:_(<2 x s16>) = G_UREM %var, %four_vec193 $vgpr0 = COPY %rem194...195 196---197name: v_urem_v2i32_pow2k_denom198tracksRegLiveness: true199body: |200 bb.0:201 liveins: $vgpr0_vgpr1202 203 ; GCN-LABEL: name: v_urem_v2i32_pow2k_denom204 ; GCN: liveins: $vgpr0_vgpr1205 ; GCN-NEXT: {{ $}}206 ; GCN-NEXT: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1207 ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4095208 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)209 ; GCN-NEXT: %rem:_(<2 x s32>) = G_AND %var, [[BUILD_VECTOR]]210 ; GCN-NEXT: $vgpr0_vgpr1 = COPY %rem(<2 x s32>)211 %var:_(<2 x s32>) = COPY $vgpr0_vgpr1212 %pow2:_(s32) = G_CONSTANT i32 4096213 %pow2_vec:_(<2 x s32>) = G_BUILD_VECTOR %pow2(s32), %pow2(s32)214 %rem:_(<2 x s32>) = G_UREM %var, %pow2_vec215 $vgpr0_vgpr1 = COPY %rem216...217 218---219name: v_urem_v2i32_pow2k_not_splat_denom220tracksRegLiveness: true221body: |222 bb.0:223 liveins: $vgpr0_vgpr1224 225 ; GCN-LABEL: name: v_urem_v2i32_pow2k_not_splat_denom226 ; GCN: liveins: $vgpr0_vgpr1227 ; GCN-NEXT: {{ $}}228 ; GCN-NEXT: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1229 ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4095230 ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2047231 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32)232 ; GCN-NEXT: %rem:_(<2 x s32>) = G_AND %var, [[BUILD_VECTOR]]233 ; GCN-NEXT: $vgpr0_vgpr1 = COPY %rem(<2 x s32>)234 %var:_(<2 x s32>) = COPY $vgpr0_vgpr1235 %pow2_1:_(s32) = G_CONSTANT i32 4096236 %pow2_2:_(s32) = G_CONSTANT i32 2048237 %pow2_vec:_(<2 x s32>) = G_BUILD_VECTOR %pow2_1(s32), %pow2_2(s32)238 %rem:_(<2 x s32>) = G_UREM %var, %pow2_vec239 $vgpr0_vgpr1 = COPY %rem240...241 242---243name: v_urem_v2i64_pow2k_denom244tracksRegLiveness: true245body: |246 bb.0:247 liveins: $vgpr0_vgpr1_vgpr2_vgpr3248 249 ; GCN-LABEL: name: v_urem_v2i64_pow2k_denom250 ; GCN: liveins: $vgpr0_vgpr1_vgpr2_vgpr3251 ; GCN-NEXT: {{ $}}252 ; GCN-NEXT: %var:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3253 ; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4095254 ; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)255 ; GCN-NEXT: %rem:_(<2 x s64>) = G_AND %var, [[BUILD_VECTOR]]256 ; GCN-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %rem(<2 x s64>)257 %var:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3258 %pow2:_(s64) = G_CONSTANT i64 4096259 %pow2_vec:_(<2 x s64>) = G_BUILD_VECTOR %pow2(s64), %pow2(s64)260 %rem:_(<2 x s64>) = G_UREM %var, %pow2_vec261 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %rem262...263