168 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 22# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: known_sign_bits_smed3_06legalized: true7tracksRegLiveness: true8body: |9 bb.0:10 liveins: $vgpr011 12 ; CHECK-LABEL: name: known_sign_bits_smed3_013 ; CHECK: liveins: $vgpr014 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: %val:_(s32) = COPY $vgpr016 ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 817 ; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -25518 ; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 25519 ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val220 ; CHECK-NEXT: $vgpr0 = COPY %smed3(s32)21 %val:_(s32) = COPY $vgpr022 %val0:_(s32) = G_SEXT_INREG %val, 823 %val1:_(s32) = G_CONSTANT i32 -25524 %val2:_(s32) = G_CONSTANT i32 25525 %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val226 %inreg:_(s32) = G_SEXT_INREG %smed3, 927 $vgpr0 = COPY %inreg28 29...30 31---32name: known_sign_bits_smed3_133legalized: true34tracksRegLiveness: true35body: |36 bb.0:37 liveins: $vgpr038 39 ; CHECK-LABEL: name: known_sign_bits_smed3_140 ; CHECK: liveins: $vgpr041 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: %val:_(s32) = COPY $vgpr043 ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 844 ; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -25545 ; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 25546 ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val0, %val247 ; CHECK-NEXT: $vgpr0 = COPY %smed3(s32)48 %val:_(s32) = COPY $vgpr049 %val0:_(s32) = G_SEXT_INREG %val, 850 %val1:_(s32) = G_CONSTANT i32 -25551 %val2:_(s32) = G_CONSTANT i32 25552 %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val0, %val253 %inreg:_(s32) = G_SEXT_INREG %smed3, 954 $vgpr0 = COPY %inreg55 56...57 58---59name: known_sign_bits_smed3_260legalized: true61tracksRegLiveness: true62body: |63 bb.0:64 liveins: $vgpr065 66 ; CHECK-LABEL: name: known_sign_bits_smed3_267 ; CHECK: liveins: $vgpr068 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: %val:_(s32) = COPY $vgpr070 ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 871 ; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -25672 ; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 12873 ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val2, %val074 ; CHECK-NEXT: $vgpr0 = COPY %smed3(s32)75 %val:_(s32) = COPY $vgpr076 %val0:_(s32) = G_SEXT_INREG %val, 877 %val1:_(s32) = G_CONSTANT i32 -25678 %val2:_(s32) = G_CONSTANT i32 12879 %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val2, %val080 %inreg:_(s32) = G_SEXT_INREG %smed3, 981 $vgpr0 = COPY %inreg82 83...84 85---86name: not_enough_sign_bits_smed3_087legalized: true88tracksRegLiveness: true89body: |90 bb.0:91 liveins: $vgpr0, $vgpr1, $vgpr292 93 ; CHECK-LABEL: name: not_enough_sign_bits_smed3_094 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr295 ; CHECK-NEXT: {{ $}}96 ; CHECK-NEXT: %val:_(s32) = COPY $vgpr097 ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 898 ; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 999 ; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9100 ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2101 ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8102 ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)103 %val:_(s32) = COPY $vgpr0104 %val0:_(s32) = G_SEXT_INREG %val, 8105 %val1:_(s32) = G_SEXT_INREG %val, 9106 %val2:_(s32) = G_SEXT_INREG %val, 9107 %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2108 %inreg:_(s32) = G_SEXT_INREG %smed3, 8109 $vgpr0 = COPY %inreg110 111...112 113---114name: not_enough_sign_bits_smed3_1115legalized: true116tracksRegLiveness: true117body: |118 bb.0:119 liveins: $vgpr0, $vgpr1, $vgpr2120 121 ; CHECK-LABEL: name: not_enough_sign_bits_smed3_1122 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2123 ; CHECK-NEXT: {{ $}}124 ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0125 ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 9126 ; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 8127 ; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9128 ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2129 ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8130 ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)131 %val:_(s32) = COPY $vgpr0132 %val0:_(s32) = G_SEXT_INREG %val, 9133 %val1:_(s32) = G_SEXT_INREG %val, 8134 %val2:_(s32) = G_SEXT_INREG %val, 9135 %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2136 %inreg:_(s32) = G_SEXT_INREG %smed3, 8137 $vgpr0 = COPY %inreg138 139...140 141---142name: not_enough_sign_bits_smed3_2143legalized: true144tracksRegLiveness: true145body: |146 bb.0:147 liveins: $vgpr0, $vgpr1, $vgpr2148 149 ; CHECK-LABEL: name: not_enough_sign_bits_smed3_2150 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2151 ; CHECK-NEXT: {{ $}}152 ; CHECK-NEXT: %val:_(s32) = COPY $vgpr0153 ; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8154 ; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 8155 ; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9156 ; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2157 ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8158 ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)159 %val:_(s32) = COPY $vgpr0160 %val0:_(s32) = G_SEXT_INREG %val, 8161 %val1:_(s32) = G_SEXT_INREG %val, 8162 %val2:_(s32) = G_SEXT_INREG %val, 9163 %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2164 %inreg:_(s32) = G_SEXT_INREG %smed3, 8165 $vgpr0 = COPY %inreg166 167...168