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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -enable-var-scope -check-prefixes=GFX10PLUS,GFX10 %s4; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -enable-var-scope -check-prefixes=GFX10PLUS,GFX11 %s5 6; Make sure we don't violate the constant bus restriction7 8define amdgpu_ps float @fmul_s_s(float inreg %src0, float inreg %src1) {9; GFX9-LABEL: fmul_s_s:10; GFX9: ; %bb.0:11; GFX9-NEXT: v_mov_b32_e32 v0, s312; GFX9-NEXT: v_mul_f32_e32 v0, s2, v013; GFX9-NEXT: ; return to shader part epilog14;15; GFX10PLUS-LABEL: fmul_s_s:16; GFX10PLUS: ; %bb.0:17; GFX10PLUS-NEXT: v_mul_f32_e64 v0, s2, s318; GFX10PLUS-NEXT: ; return to shader part epilog19 %result = fmul float %src0, %src120 ret float %result21}22 23define amdgpu_ps float @fmul_ss(float inreg %src) {24; GFX9-LABEL: fmul_ss:25; GFX9: ; %bb.0:26; GFX9-NEXT: v_mul_f32_e64 v0, s2, s227; GFX9-NEXT: ; return to shader part epilog28;29; GFX10PLUS-LABEL: fmul_ss:30; GFX10PLUS: ; %bb.0:31; GFX10PLUS-NEXT: v_mul_f32_e64 v0, s2, s232; GFX10PLUS-NEXT: ; return to shader part epilog33 %result = fmul float %src, %src34 ret float %result35}36 37; Ternary operation with 3 different SGPRs38define amdgpu_ps float @fma_s_s_s(float inreg %src0, float inreg %src1, float inreg %src2) {39; GFX9-LABEL: fma_s_s_s:40; GFX9: ; %bb.0:41; GFX9-NEXT: v_mov_b32_e32 v0, s342; GFX9-NEXT: v_mov_b32_e32 v1, s443; GFX9-NEXT: v_fma_f32 v0, s2, v0, v144; GFX9-NEXT: ; return to shader part epilog45;46; GFX10PLUS-LABEL: fma_s_s_s:47; GFX10PLUS: ; %bb.0:48; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s449; GFX10PLUS-NEXT: v_fma_f32 v0, s3, s2, v050; GFX10PLUS-NEXT: ; return to shader part epilog51 %result = call float @llvm.fma.f32(float %src0, float %src1, float %src2)52 ret float %result53}54 55; Ternary operation with 3 identical SGPRs56define amdgpu_ps float @fma_sss(float inreg %src) {57; GFX9-LABEL: fma_sss:58; GFX9: ; %bb.0:59; GFX9-NEXT: v_fma_f32 v0, s2, s2, s260; GFX9-NEXT: ; return to shader part epilog61;62; GFX10PLUS-LABEL: fma_sss:63; GFX10PLUS: ; %bb.0:64; GFX10PLUS-NEXT: v_fma_f32 v0, s2, s2, s265; GFX10PLUS-NEXT: ; return to shader part epilog66 %result = call float @llvm.fma.f32(float %src, float %src, float %src)67 ret float %result68}69 70; src0/1 are same SGPR71define amdgpu_ps float @fma_ss_s(float inreg %src01, float inreg %src2) {72; GFX9-LABEL: fma_ss_s:73; GFX9: ; %bb.0:74; GFX9-NEXT: v_mov_b32_e32 v0, s375; GFX9-NEXT: v_fma_f32 v0, s2, s2, v076; GFX9-NEXT: ; return to shader part epilog77;78; GFX10PLUS-LABEL: fma_ss_s:79; GFX10PLUS: ; %bb.0:80; GFX10PLUS-NEXT: v_fma_f32 v0, s2, s2, s381; GFX10PLUS-NEXT: ; return to shader part epilog82 %result = call float @llvm.fma.f32(float %src01, float %src01, float %src2)83 ret float %result84}85 86; src1/2 are same SGPR87define amdgpu_ps float @fma_s_ss(float inreg %src0, float inreg %src12) {88; GFX9-LABEL: fma_s_ss:89; GFX9: ; %bb.0:90; GFX9-NEXT: v_mov_b32_e32 v0, s391; GFX9-NEXT: v_fma_f32 v0, s2, v0, v092; GFX9-NEXT: ; return to shader part epilog93;94; GFX10PLUS-LABEL: fma_s_ss:95; GFX10PLUS: ; %bb.0:96; GFX10PLUS-NEXT: v_fma_f32 v0, s2, s3, s397; GFX10PLUS-NEXT: ; return to shader part epilog98 %result = call float @llvm.fma.f32(float %src0, float %src12, float %src12)99 ret float %result100}101 102; src0/2 are same SGPR103define amdgpu_ps float @fma_ss_s_same_outer(float inreg %src02, float inreg %src1) {104; GFX9-LABEL: fma_ss_s_same_outer:105; GFX9: ; %bb.0:106; GFX9-NEXT: v_mov_b32_e32 v0, s3107; GFX9-NEXT: v_fma_f32 v0, s2, v0, s2108; GFX9-NEXT: ; return to shader part epilog109;110; GFX10PLUS-LABEL: fma_ss_s_same_outer:111; GFX10PLUS: ; %bb.0:112; GFX10PLUS-NEXT: v_fma_f32 v0, s2, s3, s2113; GFX10PLUS-NEXT: ; return to shader part epilog114 %result = call float @llvm.fma.f32(float %src02, float %src1, float %src02)115 ret float %result116}117 118define amdgpu_ps float @fcmp_s_s(float inreg %src0, float inreg %src1) {119; GFX9-LABEL: fcmp_s_s:120; GFX9: ; %bb.0:121; GFX9-NEXT: v_mov_b32_e32 v0, s3122; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, s2, v0123; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc124; GFX9-NEXT: ; return to shader part epilog125;126; GFX10PLUS-LABEL: fcmp_s_s:127; GFX10PLUS: ; %bb.0:128; GFX10PLUS-NEXT: v_cmp_eq_f32_e64 s0, s2, s3129; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0130; GFX10PLUS-NEXT: ; return to shader part epilog131 %cmp = fcmp oeq float %src0, %src1132 %result = select i1 %cmp, float 1.0, float 0.0133 ret float %result134}135 136define amdgpu_ps float @select_vcc_s_s(float %cmp0, float %cmp1, float inreg %src0, float inreg %src1) {137; GFX9-LABEL: select_vcc_s_s:138; GFX9: ; %bb.0:139; GFX9-NEXT: v_mov_b32_e32 v2, s2140; GFX9-NEXT: v_mov_b32_e32 v3, s3141; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v0, v1142; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc143; GFX9-NEXT: ; return to shader part epilog144;145; GFX10PLUS-LABEL: select_vcc_s_s:146; GFX10PLUS: ; %bb.0:147; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s3148; GFX10PLUS-NEXT: v_cmp_eq_f32_e32 vcc_lo, v0, v1149; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v2, s2, vcc_lo150; GFX10PLUS-NEXT: ; return to shader part epilog151 %cmp = fcmp oeq float %cmp0, %cmp1152 %result = select i1 %cmp, float %src0, float %src1153 ret float %result154}155 156define amdgpu_ps float @select_vcc_fneg_s_s(float %cmp0, float %cmp1, float inreg %src0, float inreg %src1) {157; GFX9-LABEL: select_vcc_fneg_s_s:158; GFX9: ; %bb.0:159; GFX9-NEXT: v_mov_b32_e32 v2, s3160; GFX9-NEXT: v_mov_b32_e32 v3, s2161; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v0, v1162; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, -v3, vcc163; GFX9-NEXT: ; return to shader part epilog164;165; GFX10PLUS-LABEL: select_vcc_fneg_s_s:166; GFX10PLUS: ; %bb.0:167; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s2168; GFX10PLUS-NEXT: v_cmp_eq_f32_e32 vcc_lo, v0, v1169; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, s3, -v2, vcc_lo170; GFX10PLUS-NEXT: ; return to shader part epilog171 %cmp = fcmp oeq float %cmp0, %cmp1172 %neg.src0 = fneg float %src0173 %result = select i1 %cmp, float %neg.src0, float %src1174 ret float %result175}176 177; Constant bus used by vcc178define amdgpu_ps float @amdgcn_div_fmas_sss(float inreg %src, float %cmp.src) {179; GFX9-LABEL: amdgcn_div_fmas_sss:180; GFX9: ; %bb.0:181; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0182; GFX9-NEXT: v_mov_b32_e32 v0, s2183; GFX9-NEXT: s_nop 2184; GFX9-NEXT: v_div_fmas_f32 v0, v0, v0, v0185; GFX9-NEXT: ; return to shader part epilog186;187; GFX10PLUS-LABEL: amdgcn_div_fmas_sss:188; GFX10PLUS: ; %bb.0:189; GFX10PLUS-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0190; GFX10PLUS-NEXT: v_div_fmas_f32 v0, s2, s2, s2191; GFX10PLUS-NEXT: ; return to shader part epilog192 %vcc = fcmp oeq float %cmp.src, 0.0193 %result = call float @llvm.amdgcn.div.fmas.f32(float %src, float %src, float %src, i1 %vcc)194 ret float %result195}196 197define amdgpu_ps float @class_s_s(float inreg %src0, i32 inreg %src1) {198; GFX9-LABEL: class_s_s:199; GFX9: ; %bb.0:200; GFX9-NEXT: v_mov_b32_e32 v0, s3201; GFX9-NEXT: v_cmp_class_f32_e32 vcc, s2, v0202; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc203; GFX9-NEXT: ; return to shader part epilog204;205; GFX10PLUS-LABEL: class_s_s:206; GFX10PLUS: ; %bb.0:207; GFX10PLUS-NEXT: v_cmp_class_f32_e64 s0, s2, s3208; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0209; GFX10PLUS-NEXT: ; return to shader part epilog210 %class = call i1 @llvm.amdgcn.class.f32(float %src0, i32 %src1)211 %result = select i1 %class, float 1.0, float 0.0212 ret float %result213}214 215define amdgpu_ps float @div_scale_s_s_true(float inreg %src0, float inreg %src1) {216; GFX9-LABEL: div_scale_s_s_true:217; GFX9: ; %bb.0:218; GFX9-NEXT: v_mov_b32_e32 v0, s3219; GFX9-NEXT: v_div_scale_f32 v0, s[0:1], s2, v0, s2220; GFX9-NEXT: ; return to shader part epilog221;222; GFX10-LABEL: div_scale_s_s_true:223; GFX10: ; %bb.0:224; GFX10-NEXT: v_div_scale_f32 v0, s0, s2, s3, s2225; GFX10-NEXT: ; return to shader part epilog226;227; GFX11-LABEL: div_scale_s_s_true:228; GFX11: ; %bb.0:229; GFX11-NEXT: v_div_scale_f32 v0, null, s2, s3, s2230; GFX11-NEXT: ; return to shader part epilog231 %div.scale = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %src0, float %src1, i1 true)232 %result = extractvalue { float, i1 } %div.scale, 0233 ret float %result234}235 236define amdgpu_ps float @div_scale_s_s_false(float inreg %src0, float inreg %src1) {237; GFX9-LABEL: div_scale_s_s_false:238; GFX9: ; %bb.0:239; GFX9-NEXT: v_mov_b32_e32 v0, s3240; GFX9-NEXT: v_div_scale_f32 v0, s[0:1], v0, v0, s2241; GFX9-NEXT: ; return to shader part epilog242;243; GFX10-LABEL: div_scale_s_s_false:244; GFX10: ; %bb.0:245; GFX10-NEXT: v_div_scale_f32 v0, s0, s3, s3, s2246; GFX10-NEXT: ; return to shader part epilog247;248; GFX11-LABEL: div_scale_s_s_false:249; GFX11: ; %bb.0:250; GFX11-NEXT: v_div_scale_f32 v0, null, s3, s3, s2251; GFX11-NEXT: ; return to shader part epilog252 %div.scale = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %src0, float %src1, i1 false)253 %result = extractvalue { float, i1 } %div.scale, 0254 ret float %result255}256 257declare float @llvm.fma.f32(float, float, float) #0258declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1) #1259declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1 immarg) #1260declare i1 @llvm.amdgcn.class.f32(float, i32) #1261 262attributes #0 = { nounwind readnone speculatable willreturn }263attributes #1 = { nounwind readnone speculatable }264