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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI %s3; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s4 5declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone6declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone7 8define float @v_uitofp_i32_to_f32_mask255(i32 %arg0) nounwind {9; SI-LABEL: v_uitofp_i32_to_f32_mask255:10; SI: ; %bb.0:11; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; SI-NEXT: v_and_b32_e32 v0, 0xff, v013; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v014; SI-NEXT: s_setpc_b64 s[30:31]15;16; VI-LABEL: v_uitofp_i32_to_f32_mask255:17; VI: ; %bb.0:18; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)19; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_020; VI-NEXT: s_setpc_b64 s[30:31]21 %masked = and i32 %arg0, 25522 %cvt = uitofp i32 %masked to float23 ret float %cvt24}25 26define float @v_sitofp_i32_to_f32_mask255(i32 %arg0) nounwind {27; SI-LABEL: v_sitofp_i32_to_f32_mask255:28; SI: ; %bb.0:29; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)30; SI-NEXT: v_and_b32_e32 v0, 0xff, v031; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v032; SI-NEXT: s_setpc_b64 s[30:31]33;34; VI-LABEL: v_sitofp_i32_to_f32_mask255:35; VI: ; %bb.0:36; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)37; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_038; VI-NEXT: s_setpc_b64 s[30:31]39 %masked = and i32 %arg0, 25540 %cvt = sitofp i32 %masked to float41 ret float %cvt42}43 44define float @v_uitofp_to_f32_lshr7_mask255(i32 %arg0) nounwind {45; GCN-LABEL: v_uitofp_to_f32_lshr7_mask255:46; GCN: ; %bb.0:47; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)48; GCN-NEXT: v_bfe_u32 v0, v0, 7, 849; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, v050; GCN-NEXT: s_setpc_b64 s[30:31]51 %lshr.7 = lshr i32 %arg0, 752 %masked = and i32 %lshr.7, 25553 %cvt = uitofp i32 %masked to float54 ret float %cvt55}56 57define float @v_uitofp_to_f32_lshr8_mask255(i32 %arg0) nounwind {58; SI-LABEL: v_uitofp_to_f32_lshr8_mask255:59; SI: ; %bb.0:60; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)61; SI-NEXT: v_bfe_u32 v0, v0, 8, 862; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v063; SI-NEXT: s_setpc_b64 s[30:31]64;65; VI-LABEL: v_uitofp_to_f32_lshr8_mask255:66; VI: ; %bb.0:67; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)68; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_169; VI-NEXT: s_setpc_b64 s[30:31]70 %lshr.8 = lshr i32 %arg0, 871 %masked = and i32 %lshr.8, 25572 %cvt = uitofp i32 %masked to float73 ret float %cvt74}75 76define float @v_uitofp_to_f32_multi_use_lshr8_mask255(i32 %arg0) nounwind {77; SI-LABEL: v_uitofp_to_f32_multi_use_lshr8_mask255:78; SI: ; %bb.0:79; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)80; SI-NEXT: v_lshrrev_b32_e32 v0, 8, v081; SI-NEXT: s_mov_b32 s6, -182; SI-NEXT: s_mov_b32 s7, 0xf00083; SI-NEXT: buffer_store_dword v0, off, s[4:7], 084; SI-NEXT: s_waitcnt expcnt(0)85; SI-NEXT: v_and_b32_e32 v0, 0xff, v086; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v087; SI-NEXT: s_waitcnt vmcnt(0)88; SI-NEXT: s_setpc_b64 s[30:31]89;90; VI-LABEL: v_uitofp_to_f32_multi_use_lshr8_mask255:91; VI: ; %bb.0:92; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)93; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v094; VI-NEXT: flat_store_dword v[0:1], v095; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_096; VI-NEXT: s_waitcnt vmcnt(0)97; VI-NEXT: s_setpc_b64 s[30:31]98 %lshr.8 = lshr i32 %arg0, 899 store i32 %lshr.8, ptr addrspace(1) poison100 %masked = and i32 %lshr.8, 255101 %cvt = uitofp i32 %masked to float102 ret float %cvt103}104 105define float @v_uitofp_to_f32_lshr16_mask255(i32 %arg0) nounwind {106; SI-LABEL: v_uitofp_to_f32_lshr16_mask255:107; SI: ; %bb.0:108; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)109; SI-NEXT: v_bfe_u32 v0, v0, 16, 8110; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0111; SI-NEXT: s_setpc_b64 s[30:31]112;113; VI-LABEL: v_uitofp_to_f32_lshr16_mask255:114; VI: ; %bb.0:115; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)116; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2117; VI-NEXT: s_setpc_b64 s[30:31]118 %lshr.16 = lshr i32 %arg0, 16119 %masked = and i32 %lshr.16, 255120 %cvt = uitofp i32 %masked to float121 ret float %cvt122}123 124define float @v_uitofp_to_f32_lshr24_mask255(i32 %arg0) nounwind {125; GCN-LABEL: v_uitofp_to_f32_lshr24_mask255:126; GCN: ; %bb.0:127; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)128; GCN-NEXT: v_cvt_f32_ubyte3_e32 v0, v0129; GCN-NEXT: s_setpc_b64 s[30:31]130 %lshr.16 = lshr i32 %arg0, 24131 %masked = and i32 %lshr.16, 255132 %cvt = uitofp i32 %masked to float133 ret float %cvt134}135 136define float @v_uitofp_i8_to_f32(i8 %arg0) nounwind {137; SI-LABEL: v_uitofp_i8_to_f32:138; SI: ; %bb.0:139; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)140; SI-NEXT: v_and_b32_e32 v0, 0xff, v0141; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0142; SI-NEXT: s_setpc_b64 s[30:31]143;144; VI-LABEL: v_uitofp_i8_to_f32:145; VI: ; %bb.0:146; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)147; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0148; VI-NEXT: s_setpc_b64 s[30:31]149 %cvt = uitofp i8 %arg0 to float150 ret float %cvt151}152 153define <2 x float> @v_uitofp_v2i8_to_v2f32(i16 %arg0) nounwind {154; SI-LABEL: v_uitofp_v2i8_to_v2f32:155; SI: ; %bb.0:156; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)157; SI-NEXT: v_and_b32_e32 v1, 0xff, v0158; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v1159; SI-NEXT: v_bfe_u32 v0, v0, 8, 8160; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v0161; SI-NEXT: v_mov_b32_e32 v0, v2162; SI-NEXT: s_setpc_b64 s[30:31]163;164; VI-LABEL: v_uitofp_v2i8_to_v2f32:165; VI: ; %bb.0:166; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)167; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0168; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1169; VI-NEXT: v_mov_b32_e32 v0, v2170; VI-NEXT: s_setpc_b64 s[30:31]171 %val = bitcast i16 %arg0 to <2 x i8>172 %cvt = uitofp <2 x i8> %val to <2 x float>173 ret <2 x float> %cvt174}175 176define <3 x float> @v_uitofp_v3i8_to_v3f32(i32 %arg0) nounwind {177; SI-LABEL: v_uitofp_v3i8_to_v3f32:178; SI: ; %bb.0:179; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)180; SI-NEXT: v_and_b32_e32 v1, 0xff, v0181; SI-NEXT: v_cvt_f32_ubyte0_e32 v3, v1182; SI-NEXT: v_bfe_u32 v1, v0, 8, 8183; SI-NEXT: v_bfe_u32 v0, v0, 16, 8184; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1185; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v0186; SI-NEXT: v_mov_b32_e32 v0, v3187; SI-NEXT: s_setpc_b64 s[30:31]188;189; VI-LABEL: v_uitofp_v3i8_to_v3f32:190; VI: ; %bb.0:191; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)192; VI-NEXT: v_cvt_f32_ubyte0_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0193; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1194; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2195; VI-NEXT: v_mov_b32_e32 v0, v3196; VI-NEXT: s_setpc_b64 s[30:31]197 %trunc = trunc i32 %arg0 to i24198 %val = bitcast i24 %trunc to <3 x i8>199 %cvt = uitofp <3 x i8> %val to <3 x float>200 ret <3 x float> %cvt201}202 203define <4 x float> @v_uitofp_v4i8_to_v4f32(i32 %arg0) nounwind {204; SI-LABEL: v_uitofp_v4i8_to_v4f32:205; SI: ; %bb.0:206; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)207; SI-NEXT: v_and_b32_e32 v1, 0xff, v0208; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v1209; SI-NEXT: v_bfe_u32 v1, v0, 8, 8210; SI-NEXT: v_bfe_u32 v2, v0, 16, 8211; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1212; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2213; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0214; SI-NEXT: v_mov_b32_e32 v0, v4215; SI-NEXT: s_setpc_b64 s[30:31]216;217; VI-LABEL: v_uitofp_v4i8_to_v4f32:218; VI: ; %bb.0:219; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)220; VI-NEXT: v_cvt_f32_ubyte0_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0221; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1222; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2223; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0224; VI-NEXT: v_mov_b32_e32 v0, v4225; VI-NEXT: s_setpc_b64 s[30:31]226 %val = bitcast i32 %arg0 to <4 x i8>227 %cvt = uitofp <4 x i8> %val to <4 x float>228 ret <4 x float> %cvt229}230 231define <4 x float> @v_uitofp_unpack_i32_to_v4f32(i32 %arg0) nounwind {232; SI-LABEL: v_uitofp_unpack_i32_to_v4f32:233; SI: ; %bb.0:234; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)235; SI-NEXT: v_and_b32_e32 v1, 0xff, v0236; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v1237; SI-NEXT: v_bfe_u32 v1, v0, 8, 8238; SI-NEXT: v_bfe_u32 v2, v0, 16, 8239; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1240; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2241; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0242; SI-NEXT: v_mov_b32_e32 v0, v4243; SI-NEXT: s_setpc_b64 s[30:31]244;245; VI-LABEL: v_uitofp_unpack_i32_to_v4f32:246; VI: ; %bb.0:247; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)248; VI-NEXT: v_cvt_f32_ubyte0_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0249; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1250; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2251; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0252; VI-NEXT: v_mov_b32_e32 v0, v4253; VI-NEXT: s_setpc_b64 s[30:31]254 %mask.arg0 = and i32 %arg0, 255255 %cvt0 = uitofp i32 %mask.arg0 to float256 257 %lshr.8 = lshr i32 %arg0, 8258 %mask.lshr.8 = and i32 %lshr.8, 255259 %cvt1 = uitofp i32 %mask.lshr.8 to float260 261 %lshr.16 = lshr i32 %arg0, 16262 %mask.lshr.16 = and i32 %lshr.16, 255263 %cvt2 = uitofp i32 %mask.lshr.16 to float264 265 %lshr.24 = lshr i32 %arg0, 24266 %mask.lshr.24 = and i32 %lshr.24, 255267 %cvt3 = uitofp i32 %mask.lshr.24 to float268 269 %ins.0 = insertelement <4 x float> poison, float %cvt0, i32 0270 %ins.1 = insertelement <4 x float> %ins.0, float %cvt1, i32 1271 %ins.2 = insertelement <4 x float> %ins.1, float %cvt2, i32 2272 %ins.3 = insertelement <4 x float> %ins.2, float %cvt3, i32 3273 ret <4 x float> %ins.3274}275 276define half @v_uitofp_i32_to_f16_mask255(i32 %arg0) nounwind {277; SI-LABEL: v_uitofp_i32_to_f16_mask255:278; SI: ; %bb.0:279; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)280; SI-NEXT: v_and_b32_e32 v0, 0xff, v0281; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0282; SI-NEXT: v_cvt_f16_f32_e32 v0, v0283; SI-NEXT: s_setpc_b64 s[30:31]284;285; VI-LABEL: v_uitofp_i32_to_f16_mask255:286; VI: ; %bb.0:287; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)288; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0289; VI-NEXT: v_cvt_f16_f32_e32 v0, v0290; VI-NEXT: s_setpc_b64 s[30:31]291 %masked = and i32 %arg0, 255292 %cvt = uitofp i32 %masked to half293 ret half %cvt294}295 296define half @v_sitofp_i32_to_f16_mask255(i32 %arg0) nounwind {297; SI-LABEL: v_sitofp_i32_to_f16_mask255:298; SI: ; %bb.0:299; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)300; SI-NEXT: v_and_b32_e32 v0, 0xff, v0301; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0302; SI-NEXT: v_cvt_f16_f32_e32 v0, v0303; SI-NEXT: s_setpc_b64 s[30:31]304;305; VI-LABEL: v_sitofp_i32_to_f16_mask255:306; VI: ; %bb.0:307; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)308; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0309; VI-NEXT: v_cvt_f16_f32_e32 v0, v0310; VI-NEXT: s_setpc_b64 s[30:31]311 %masked = and i32 %arg0, 255312 %cvt = sitofp i32 %masked to half313 ret half %cvt314}315 316define half @v_uitofp_to_f16_lshr8_mask255(i32 %arg0) nounwind {317; SI-LABEL: v_uitofp_to_f16_lshr8_mask255:318; SI: ; %bb.0:319; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)320; SI-NEXT: v_bfe_u32 v0, v0, 8, 8321; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0322; SI-NEXT: v_cvt_f16_f32_e32 v0, v0323; SI-NEXT: s_setpc_b64 s[30:31]324;325; VI-LABEL: v_uitofp_to_f16_lshr8_mask255:326; VI: ; %bb.0:327; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)328; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1329; VI-NEXT: v_cvt_f16_f32_e32 v0, v0330; VI-NEXT: s_setpc_b64 s[30:31]331 %lshr.8 = lshr i32 %arg0, 8332 %masked = and i32 %lshr.8, 255333 %cvt = uitofp i32 %masked to half334 ret half %cvt335}336 337define half @v_uitofp_to_f16_lshr16_mask255(i32 %arg0) nounwind {338; SI-LABEL: v_uitofp_to_f16_lshr16_mask255:339; SI: ; %bb.0:340; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)341; SI-NEXT: v_bfe_u32 v0, v0, 16, 8342; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0343; SI-NEXT: v_cvt_f16_f32_e32 v0, v0344; SI-NEXT: s_setpc_b64 s[30:31]345;346; VI-LABEL: v_uitofp_to_f16_lshr16_mask255:347; VI: ; %bb.0:348; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)349; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2350; VI-NEXT: v_cvt_f16_f32_e32 v0, v0351; VI-NEXT: s_setpc_b64 s[30:31]352 %lshr.16 = lshr i32 %arg0, 16353 %masked = and i32 %lshr.16, 255354 %cvt = uitofp i32 %masked to half355 ret half %cvt356}357 358define half @v_uitofp_to_f16_lshr24_mask255(i32 %arg0) nounwind {359; GCN-LABEL: v_uitofp_to_f16_lshr24_mask255:360; GCN: ; %bb.0:361; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)362; GCN-NEXT: v_cvt_f32_ubyte3_e32 v0, v0363; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0364; GCN-NEXT: s_setpc_b64 s[30:31]365 %lshr.16 = lshr i32 %arg0, 24366 %masked = and i32 %lshr.16, 255367 %cvt = uitofp i32 %masked to half368 ret half %cvt369}370 371define half @v_uitofp_i8_to_f16(i8 %arg0) nounwind {372; SI-LABEL: v_uitofp_i8_to_f16:373; SI: ; %bb.0:374; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)375; SI-NEXT: v_and_b32_e32 v0, 0xff, v0376; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0377; SI-NEXT: v_cvt_f16_f32_e32 v0, v0378; SI-NEXT: s_setpc_b64 s[30:31]379;380; VI-LABEL: v_uitofp_i8_to_f16:381; VI: ; %bb.0:382; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)383; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0384; VI-NEXT: v_cvt_f16_f32_e32 v0, v0385; VI-NEXT: s_setpc_b64 s[30:31]386 %cvt = uitofp i8 %arg0 to half387 ret half %cvt388}389 390define double @v_uitofp_i32_to_f64_mask255(i32 %arg0) nounwind {391; GCN-LABEL: v_uitofp_i32_to_f64_mask255:392; GCN: ; %bb.0:393; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)394; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0395; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v0396; GCN-NEXT: s_setpc_b64 s[30:31]397 %masked = and i32 %arg0, 255398 %cvt = uitofp i32 %masked to double399 ret double %cvt400}401 402define double @v_uitofp_to_f64_lshr8_mask255(i32 %arg0) nounwind {403; GCN-LABEL: v_uitofp_to_f64_lshr8_mask255:404; GCN: ; %bb.0:405; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)406; GCN-NEXT: v_bfe_u32 v0, v0, 8, 8407; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v0408; GCN-NEXT: s_setpc_b64 s[30:31]409 %lshr.8 = lshr i32 %arg0, 8410 %masked = and i32 %lshr.8, 255411 %cvt = uitofp i32 %masked to double412 ret double %cvt413}414 415define double @v_uitofp_to_f64_lshr16_mask255(i32 %arg0) nounwind {416; GCN-LABEL: v_uitofp_to_f64_lshr16_mask255:417; GCN: ; %bb.0:418; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)419; GCN-NEXT: v_bfe_u32 v0, v0, 16, 8420; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v0421; GCN-NEXT: s_setpc_b64 s[30:31]422 %lshr.16 = lshr i32 %arg0, 16423 %masked = and i32 %lshr.16, 255424 %cvt = uitofp i32 %masked to double425 ret double %cvt426}427 428define double @v_uitofp_to_f64_lshr24_mask255(i32 %arg0) nounwind {429; GCN-LABEL: v_uitofp_to_f64_lshr24_mask255:430; GCN: ; %bb.0:431; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)432; GCN-NEXT: v_lshrrev_b32_e32 v0, 24, v0433; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v0434; GCN-NEXT: s_setpc_b64 s[30:31]435 %lshr.16 = lshr i32 %arg0, 24436 %masked = and i32 %lshr.16, 255437 %cvt = uitofp i32 %masked to double438 ret double %cvt439}440 441define double @v_uitofp_i8_to_f64(i8 %arg0) nounwind {442; GCN-LABEL: v_uitofp_i8_to_f64:443; GCN: ; %bb.0:444; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)445; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0446; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v0447; GCN-NEXT: s_setpc_b64 s[30:31]448 %cvt = uitofp i8 %arg0 to double449 ret double %cvt450}451 452define amdgpu_kernel void @load_i8_to_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {453; SI-LABEL: load_i8_to_f32:454; SI: ; %bb.0:455; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9456; SI-NEXT: s_mov_b32 s6, 0457; SI-NEXT: s_mov_b32 s7, 0xf000458; SI-NEXT: v_ashrrev_i32_e32 v1, 31, v0459; SI-NEXT: s_waitcnt lgkmcnt(0)460; SI-NEXT: s_mov_b64 s[4:5], s[2:3]461; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64462; SI-NEXT: s_mov_b32 s6, -1463; SI-NEXT: s_mov_b64 s[2:3], s[6:7]464; SI-NEXT: s_waitcnt vmcnt(0)465; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0466; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0467; SI-NEXT: s_endpgm468;469; VI-LABEL: load_i8_to_f32:470; VI: ; %bb.0:471; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24472; VI-NEXT: v_ashrrev_i32_e32 v3, 31, v0473; VI-NEXT: s_waitcnt lgkmcnt(0)474; VI-NEXT: v_mov_b32_e32 v1, s2475; VI-NEXT: v_mov_b32_e32 v2, s3476; VI-NEXT: v_add_u32_e32 v0, vcc, v1, v0477; VI-NEXT: v_addc_u32_e32 v1, vcc, v2, v3, vcc478; VI-NEXT: flat_load_ubyte v0, v[0:1]479; VI-NEXT: s_waitcnt vmcnt(0)480; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v0481; VI-NEXT: v_mov_b32_e32 v0, s0482; VI-NEXT: v_mov_b32_e32 v1, s1483; VI-NEXT: flat_store_dword v[0:1], v2484; VI-NEXT: s_endpgm485 %tid = call i32 @llvm.amdgcn.workitem.id.x()486 %gep = getelementptr i8, ptr addrspace(1) %in, i32 %tid487 %load = load i8, ptr addrspace(1) %gep, align 1488 %cvt = uitofp i8 %load to float489 store float %cvt, ptr addrspace(1) %out, align 4490 ret void491}492 493define amdgpu_kernel void @load_v2i8_to_v2f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {494; SI-LABEL: load_v2i8_to_v2f32:495; SI: ; %bb.0:496; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9497; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0498; SI-NEXT: v_mov_b32_e32 v1, 0499; SI-NEXT: s_mov_b32 s6, 0500; SI-NEXT: s_mov_b32 s7, 0xf000501; SI-NEXT: s_waitcnt lgkmcnt(0)502; SI-NEXT: s_mov_b64 s[4:5], s[2:3]503; SI-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64504; SI-NEXT: s_mov_b32 s6, -1505; SI-NEXT: s_mov_b64 s[2:3], s[6:7]506; SI-NEXT: s_waitcnt vmcnt(0)507; SI-NEXT: v_and_b32_e32 v1, 0xff, v0508; SI-NEXT: v_bfe_u32 v2, v0, 8, 8509; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v1510; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v2511; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0512; SI-NEXT: s_endpgm513;514; VI-LABEL: load_v2i8_to_v2f32:515; VI: ; %bb.0:516; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24517; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0518; VI-NEXT: s_waitcnt lgkmcnt(0)519; VI-NEXT: v_mov_b32_e32 v0, s2520; VI-NEXT: v_mov_b32_e32 v1, s3521; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2522; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc523; VI-NEXT: flat_load_ushort v1, v[0:1]524; VI-NEXT: v_mov_b32_e32 v3, s1525; VI-NEXT: v_mov_b32_e32 v2, s0526; VI-NEXT: s_waitcnt vmcnt(0)527; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0528; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1529; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]530; VI-NEXT: s_endpgm531 %tid = call i32 @llvm.amdgcn.workitem.id.x()532 %gep = getelementptr <2 x i8>, ptr addrspace(1) %in, i32 %tid533 %load = load <2 x i8>, ptr addrspace(1) %gep, align 2534 %cvt = uitofp <2 x i8> %load to <2 x float>535 store <2 x float> %cvt, ptr addrspace(1) %out, align 16536 ret void537}538 539define amdgpu_kernel void @load_v3i8_to_v3f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {540; SI-LABEL: load_v3i8_to_v3f32:541; SI: ; %bb.0:542; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9543; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0544; SI-NEXT: v_mov_b32_e32 v1, 0545; SI-NEXT: s_mov_b32 s6, 0546; SI-NEXT: s_mov_b32 s7, 0xf000547; SI-NEXT: s_waitcnt lgkmcnt(0)548; SI-NEXT: s_mov_b64 s[4:5], s[2:3]549; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64550; SI-NEXT: s_mov_b32 s6, -1551; SI-NEXT: s_mov_b64 s[2:3], s[6:7]552; SI-NEXT: s_waitcnt vmcnt(0)553; SI-NEXT: v_and_b32_e32 v1, 0xff, v0554; SI-NEXT: v_bfe_u32 v2, v0, 8, 8555; SI-NEXT: v_bfe_u32 v3, v0, 16, 8556; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v1557; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v2558; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v3559; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0560; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8561; SI-NEXT: s_endpgm562;563; VI-LABEL: load_v3i8_to_v3f32:564; VI: ; %bb.0:565; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24566; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0567; VI-NEXT: s_waitcnt lgkmcnt(0)568; VI-NEXT: v_mov_b32_e32 v0, s2569; VI-NEXT: v_mov_b32_e32 v1, s3570; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2571; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc572; VI-NEXT: flat_load_dword v2, v[0:1]573; VI-NEXT: v_mov_b32_e32 v4, s1574; VI-NEXT: v_mov_b32_e32 v3, s0575; VI-NEXT: s_waitcnt vmcnt(0)576; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0577; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1578; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2579; VI-NEXT: flat_store_dwordx3 v[3:4], v[0:2]580; VI-NEXT: s_endpgm581 %tid = call i32 @llvm.amdgcn.workitem.id.x()582 %gep = getelementptr <3 x i8>, ptr addrspace(1) %in, i32 %tid583 %load = load <3 x i8>, ptr addrspace(1) %gep, align 4584 %cvt = uitofp <3 x i8> %load to <3 x float>585 store <3 x float> %cvt, ptr addrspace(1) %out, align 16586 ret void587}588 589define amdgpu_kernel void @load_v4i8_to_v4f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {590; SI-LABEL: load_v4i8_to_v4f32:591; SI: ; %bb.0:592; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9593; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0594; SI-NEXT: v_mov_b32_e32 v1, 0595; SI-NEXT: s_mov_b32 s6, 0596; SI-NEXT: s_mov_b32 s7, 0xf000597; SI-NEXT: s_waitcnt lgkmcnt(0)598; SI-NEXT: s_mov_b64 s[4:5], s[2:3]599; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64600; SI-NEXT: s_mov_b32 s6, -1601; SI-NEXT: s_mov_b64 s[2:3], s[6:7]602; SI-NEXT: s_waitcnt vmcnt(0)603; SI-NEXT: v_and_b32_e32 v1, 0xff, v0604; SI-NEXT: v_bfe_u32 v2, v0, 8, 8605; SI-NEXT: v_bfe_u32 v4, v0, 16, 8606; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0607; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v1608; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v2609; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v4610; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0611; SI-NEXT: s_endpgm612;613; VI-LABEL: load_v4i8_to_v4f32:614; VI: ; %bb.0:615; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24616; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0617; VI-NEXT: s_waitcnt lgkmcnt(0)618; VI-NEXT: v_mov_b32_e32 v0, s2619; VI-NEXT: v_mov_b32_e32 v1, s3620; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2621; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc622; VI-NEXT: flat_load_dword v3, v[0:1]623; VI-NEXT: v_mov_b32_e32 v5, s1624; VI-NEXT: v_mov_b32_e32 v4, s0625; VI-NEXT: s_waitcnt vmcnt(0)626; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0627; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1628; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2629; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v3630; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]631; VI-NEXT: s_endpgm632 %tid = call i32 @llvm.amdgcn.workitem.id.x()633 %gep = getelementptr <4 x i8>, ptr addrspace(1) %in, i32 %tid634 %load = load <4 x i8>, ptr addrspace(1) %gep, align 4635 %cvt = uitofp <4 x i8> %load to <4 x float>636 store <4 x float> %cvt, ptr addrspace(1) %out, align 16637 ret void638}639 640; This should not be adding instructions to shift into the correct641; position in the word for the component.642 643; FIXME: Packing bytes644define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {645; SI-LABEL: load_v4i8_to_v4f32_unaligned:646; SI: ; %bb.0:647; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9648; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0649; SI-NEXT: v_mov_b32_e32 v1, 0650; SI-NEXT: s_mov_b32 s6, 0651; SI-NEXT: s_mov_b32 s7, 0xf000652; SI-NEXT: s_waitcnt lgkmcnt(0)653; SI-NEXT: s_mov_b64 s[4:5], s[2:3]654; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[4:7], 0 addr64 offset:1655; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[4:7], 0 addr64 offset:3656; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[4:7], 0 addr64 offset:2657; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64658; SI-NEXT: s_mov_b32 s6, -1659; SI-NEXT: s_mov_b64 s[2:3], s[6:7]660; SI-NEXT: s_waitcnt vmcnt(3)661; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v2662; SI-NEXT: s_waitcnt vmcnt(2)663; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v3664; SI-NEXT: s_waitcnt vmcnt(1)665; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4666; SI-NEXT: s_waitcnt vmcnt(0)667; SI-NEXT: v_or_b32_e32 v0, v1, v0668; SI-NEXT: v_or_b32_e32 v1, v2, v3669; SI-NEXT: v_or_b32_e32 v0, v1, v0670; SI-NEXT: v_and_b32_e32 v1, 0xff, v0671; SI-NEXT: v_bfe_u32 v2, v0, 8, 8672; SI-NEXT: v_bfe_u32 v4, v0, 16, 8673; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0674; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v1675; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v2676; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v4677; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0678; SI-NEXT: s_endpgm679;680; VI-LABEL: load_v4i8_to_v4f32_unaligned:681; VI: ; %bb.0:682; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24683; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0684; VI-NEXT: s_waitcnt lgkmcnt(0)685; VI-NEXT: v_mov_b32_e32 v0, s2686; VI-NEXT: v_mov_b32_e32 v1, s3687; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2688; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc689; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0690; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc691; VI-NEXT: v_add_u32_e32 v4, vcc, 2, v0692; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc693; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v0694; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc695; VI-NEXT: flat_load_ubyte v2, v[2:3]696; VI-NEXT: flat_load_ubyte v3, v[6:7]697; VI-NEXT: flat_load_ubyte v4, v[4:5]698; VI-NEXT: flat_load_ubyte v0, v[0:1]699; VI-NEXT: s_waitcnt vmcnt(3)700; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v2701; VI-NEXT: s_waitcnt vmcnt(2)702; VI-NEXT: v_lshlrev_b32_e32 v2, 24, v3703; VI-NEXT: s_waitcnt vmcnt(1)704; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v4705; VI-NEXT: s_waitcnt vmcnt(0)706; VI-NEXT: v_or_b32_e32 v0, v1, v0707; VI-NEXT: v_or_b32_e32 v1, v2, v3708; VI-NEXT: v_or_b32_e32 v3, v1, v0709; VI-NEXT: v_mov_b32_e32 v5, s1710; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0711; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1712; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2713; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v3714; VI-NEXT: v_mov_b32_e32 v4, s0715; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]716; VI-NEXT: s_endpgm717 %tid = call i32 @llvm.amdgcn.workitem.id.x()718 %gep = getelementptr <4 x i8>, ptr addrspace(1) %in, i32 %tid719 %load = load <4 x i8>, ptr addrspace(1) %gep, align 1720 %cvt = uitofp <4 x i8> %load to <4 x float>721 store <4 x float> %cvt, ptr addrspace(1) %out, align 16722 ret void723}724 725define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %out2, ptr addrspace(1) noalias %in) nounwind {726; SI-LABEL: load_v4i8_to_v4f32_2_uses:727; SI: ; %bb.0:728; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd729; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0730; SI-NEXT: v_mov_b32_e32 v1, 0731; SI-NEXT: s_mov_b32 s2, 0732; SI-NEXT: s_mov_b32 s3, 0xf000733; SI-NEXT: s_waitcnt lgkmcnt(0)734; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64735; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9736; SI-NEXT: s_mov_b32 s2, -1737; SI-NEXT: s_waitcnt lgkmcnt(0)738; SI-NEXT: s_mov_b64 s[0:1], s[4:5]739; SI-NEXT: s_waitcnt vmcnt(0)740; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v0741; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0742; SI-NEXT: v_and_b32_e32 v5, 0xff, v0743; SI-NEXT: v_lshrrev_b32_e32 v4, 24, v0744; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0745; SI-NEXT: v_add_i32_e32 v6, vcc, 9, v0746; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v5747; SI-NEXT: v_and_b32_e32 v5, 0xff, v1748; SI-NEXT: v_and_b32_e32 v7, 0xff, v2749; SI-NEXT: v_add_i32_e32 v8, vcc, 9, v1750; SI-NEXT: v_add_i32_e32 v9, vcc, 9, v2751; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v5752; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v7753; SI-NEXT: v_and_b32_e32 v5, 0xff, v8754; SI-NEXT: v_add_i32_e32 v4, vcc, 9, v4755; SI-NEXT: v_and_b32_e32 v6, 0xff, v6756; SI-NEXT: v_and_b32_e32 v7, 0xff, v9757; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0758; SI-NEXT: s_waitcnt expcnt(0)759; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v5760; SI-NEXT: v_and_b32_e32 v4, 0xff, v4761; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v7762; SI-NEXT: v_or_b32_e32 v0, v6, v0763; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v4764; SI-NEXT: v_or_b32_e32 v0, v0, v1765; SI-NEXT: v_or_b32_e32 v0, v0, v2766; SI-NEXT: s_mov_b64 s[0:1], s[6:7]767; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0768; SI-NEXT: s_endpgm769;770; VI-LABEL: load_v4i8_to_v4f32_2_uses:771; VI: ; %bb.0:772; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x34773; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0774; VI-NEXT: v_mov_b32_e32 v6, 9775; VI-NEXT: v_mov_b32_e32 v7, 8776; VI-NEXT: s_waitcnt lgkmcnt(0)777; VI-NEXT: v_mov_b32_e32 v0, s0778; VI-NEXT: v_mov_b32_e32 v1, s1779; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2780; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc781; VI-NEXT: flat_load_dword v1, v[0:1]782; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24783; VI-NEXT: v_mov_b32_e32 v2, 0xff784; VI-NEXT: s_waitcnt lgkmcnt(0)785; VI-NEXT: v_mov_b32_e32 v5, s1786; VI-NEXT: v_mov_b32_e32 v4, s0787; VI-NEXT: s_waitcnt vmcnt(0)788; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v1789; VI-NEXT: v_and_b32_sdwa v2, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD790; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0791; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v1792; VI-NEXT: v_add_u16_e32 v9, 9, v1793; VI-NEXT: v_add_u16_sdwa v10, v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD794; VI-NEXT: v_add_u16_sdwa v6, v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD795; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0796; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2797; VI-NEXT: v_add_u16_e32 v8, 9, v8798; VI-NEXT: v_and_b32_e32 v10, 0xff, v10799; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]800; VI-NEXT: v_and_b32_e32 v6, 0xff, v6801; VI-NEXT: v_lshlrev_b32_sdwa v0, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0802; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v10803; VI-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD804; VI-NEXT: v_lshlrev_b32_e32 v2, 24, v6805; VI-NEXT: v_or_b32_e32 v0, v0, v1806; VI-NEXT: v_or_b32_e32 v2, v0, v2807; VI-NEXT: v_mov_b32_e32 v0, s2808; VI-NEXT: v_mov_b32_e32 v1, s3809; VI-NEXT: flat_store_dword v[0:1], v2810; VI-NEXT: s_endpgm811 %tid.x = call i32 @llvm.amdgcn.workitem.id.x()812 %in.ptr = getelementptr <4 x i8>, ptr addrspace(1) %in, i32 %tid.x813 %load = load <4 x i8>, ptr addrspace(1) %in.ptr, align 4814 %cvt = uitofp <4 x i8> %load to <4 x float>815 store <4 x float> %cvt, ptr addrspace(1) %out, align 16816 %add = add <4 x i8> %load, <i8 9, i8 9, i8 9, i8 9> ; Second use of %load817 store <4 x i8> %add, ptr addrspace(1) %out2, align 4818 ret void819}820 821define amdgpu_kernel void @load_v7i8_to_v7f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {822; SI-LABEL: load_v7i8_to_v7f32:823; SI: ; %bb.0:824; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9825; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0826; SI-NEXT: v_mov_b32_e32 v1, 0827; SI-NEXT: s_mov_b32 s6, 0828; SI-NEXT: s_mov_b32 s7, 0xf000829; SI-NEXT: s_waitcnt lgkmcnt(0)830; SI-NEXT: s_mov_b64 s[4:5], s[2:3]831; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[4:7], 0 addr64832; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[4:7], 0 addr64 offset:1833; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[4:7], 0 addr64 offset:2834; SI-NEXT: buffer_load_ubyte v5, v[0:1], s[4:7], 0 addr64 offset:3835; SI-NEXT: buffer_load_ubyte v6, v[0:1], s[4:7], 0 addr64 offset:4836; SI-NEXT: buffer_load_ubyte v7, v[0:1], s[4:7], 0 addr64 offset:5837; SI-NEXT: buffer_load_ubyte v8, v[0:1], s[4:7], 0 addr64 offset:6838; SI-NEXT: s_mov_b32 s6, -1839; SI-NEXT: s_mov_b64 s[2:3], s[6:7]840; SI-NEXT: s_waitcnt vmcnt(6)841; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v2842; SI-NEXT: s_waitcnt vmcnt(5)843; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v3844; SI-NEXT: s_waitcnt vmcnt(4)845; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v4846; SI-NEXT: s_waitcnt vmcnt(3)847; SI-NEXT: v_cvt_f32_ubyte0_e32 v3, v5848; SI-NEXT: s_waitcnt vmcnt(2)849; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v6850; SI-NEXT: s_waitcnt vmcnt(1)851; SI-NEXT: v_cvt_f32_ubyte0_e32 v5, v7852; SI-NEXT: s_waitcnt vmcnt(0)853; SI-NEXT: v_cvt_f32_ubyte0_e32 v6, v8854; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0855; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16856; SI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:24857; SI-NEXT: s_endpgm858;859; VI-LABEL: load_v7i8_to_v7f32:860; VI: ; %bb.0:861; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24862; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0863; VI-NEXT: s_waitcnt lgkmcnt(0)864; VI-NEXT: v_mov_b32_e32 v0, s2865; VI-NEXT: v_mov_b32_e32 v1, s3866; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2867; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc868; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0869; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc870; VI-NEXT: v_add_u32_e32 v4, vcc, 2, v0871; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc872; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v0873; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc874; VI-NEXT: v_add_u32_e32 v8, vcc, 4, v0875; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc876; VI-NEXT: v_add_u32_e32 v10, vcc, 5, v0877; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v1, vcc878; VI-NEXT: v_add_u32_e32 v12, vcc, 6, v0879; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v1, vcc880; VI-NEXT: flat_load_ubyte v0, v[0:1]881; VI-NEXT: flat_load_ubyte v1, v[2:3]882; VI-NEXT: flat_load_ubyte v2, v[4:5]883; VI-NEXT: flat_load_ubyte v3, v[6:7]884; VI-NEXT: flat_load_ubyte v4, v[8:9]885; VI-NEXT: flat_load_ubyte v5, v[10:11]886; VI-NEXT: flat_load_ubyte v6, v[12:13]887; VI-NEXT: v_mov_b32_e32 v8, s1888; VI-NEXT: v_mov_b32_e32 v7, s0889; VI-NEXT: s_add_u32 s0, s0, 16890; VI-NEXT: s_addc_u32 s1, s1, 0891; VI-NEXT: v_mov_b32_e32 v10, s1892; VI-NEXT: v_mov_b32_e32 v9, s0893; VI-NEXT: s_waitcnt vmcnt(6)894; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0895; VI-NEXT: s_waitcnt vmcnt(5)896; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1897; VI-NEXT: s_waitcnt vmcnt(4)898; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2899; VI-NEXT: s_waitcnt vmcnt(3)900; VI-NEXT: v_cvt_f32_ubyte0_e32 v3, v3901; VI-NEXT: s_waitcnt vmcnt(2)902; VI-NEXT: v_cvt_f32_ubyte0_e32 v4, v4903; VI-NEXT: s_waitcnt vmcnt(1)904; VI-NEXT: v_cvt_f32_ubyte0_e32 v5, v5905; VI-NEXT: s_waitcnt vmcnt(0)906; VI-NEXT: v_cvt_f32_ubyte0_e32 v6, v6907; VI-NEXT: flat_store_dwordx4 v[7:8], v[0:3]908; VI-NEXT: flat_store_dwordx3 v[9:10], v[4:6]909; VI-NEXT: s_endpgm910 %tid = call i32 @llvm.amdgcn.workitem.id.x()911 %gep = getelementptr <7 x i8>, ptr addrspace(1) %in, i32 %tid912 %load = load <7 x i8>, ptr addrspace(1) %gep, align 1913 %cvt = uitofp <7 x i8> %load to <7 x float>914 store <7 x float> %cvt, ptr addrspace(1) %out, align 16915 ret void916}917 918define amdgpu_kernel void @load_v8i8_to_v8f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {919; SI-LABEL: load_v8i8_to_v8f32:920; SI: ; %bb.0:921; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9922; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0923; SI-NEXT: v_mov_b32_e32 v1, 0924; SI-NEXT: s_mov_b32 s6, 0925; SI-NEXT: s_mov_b32 s7, 0xf000926; SI-NEXT: s_waitcnt lgkmcnt(0)927; SI-NEXT: s_mov_b64 s[4:5], s[2:3]928; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64929; SI-NEXT: s_mov_b32 s6, -1930; SI-NEXT: s_mov_b64 s[2:3], s[6:7]931; SI-NEXT: s_waitcnt vmcnt(0)932; SI-NEXT: v_and_b32_e32 v2, 0xff, v0933; SI-NEXT: v_bfe_u32 v4, v0, 8, 8934; SI-NEXT: v_bfe_u32 v5, v0, 16, 8935; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0936; SI-NEXT: v_and_b32_e32 v6, 0xff, v1937; SI-NEXT: v_bfe_u32 v8, v1, 8, 8938; SI-NEXT: v_bfe_u32 v9, v1, 16, 8939; SI-NEXT: v_cvt_f32_ubyte3_e32 v7, v1940; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v2941; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v4942; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v5943; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v6944; SI-NEXT: v_cvt_f32_ubyte0_e32 v5, v8945; SI-NEXT: v_cvt_f32_ubyte0_e32 v6, v9946; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0947; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16948; SI-NEXT: s_endpgm949;950; VI-LABEL: load_v8i8_to_v8f32:951; VI: ; %bb.0:952; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24953; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0954; VI-NEXT: s_waitcnt lgkmcnt(0)955; VI-NEXT: v_mov_b32_e32 v0, s2956; VI-NEXT: v_mov_b32_e32 v1, s3957; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2958; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc959; VI-NEXT: flat_load_dwordx2 v[6:7], v[0:1]960; VI-NEXT: v_mov_b32_e32 v9, s1961; VI-NEXT: v_mov_b32_e32 v8, s0962; VI-NEXT: s_add_u32 s0, s0, 16963; VI-NEXT: s_addc_u32 s1, s1, 0964; VI-NEXT: v_mov_b32_e32 v11, s1965; VI-NEXT: v_mov_b32_e32 v10, s0966; VI-NEXT: s_waitcnt vmcnt(0)967; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0968; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1969; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2970; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v6971; VI-NEXT: v_cvt_f32_ubyte0_sdwa v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0972; VI-NEXT: v_cvt_f32_ubyte0_sdwa v5, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1973; VI-NEXT: v_cvt_f32_ubyte0_sdwa v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2974; VI-NEXT: v_cvt_f32_ubyte3_e32 v7, v7975; VI-NEXT: flat_store_dwordx4 v[8:9], v[0:3]976; VI-NEXT: flat_store_dwordx4 v[10:11], v[4:7]977; VI-NEXT: s_endpgm978 %tid = call i32 @llvm.amdgcn.workitem.id.x()979 %gep = getelementptr <8 x i8>, ptr addrspace(1) %in, i32 %tid980 %load = load <8 x i8>, ptr addrspace(1) %gep, align 8981 %cvt = uitofp <8 x i8> %load to <8 x float>982 store <8 x float> %cvt, ptr addrspace(1) %out, align 16983 ret void984}985 986define amdgpu_kernel void @i8_zext_inreg_i32_to_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {987; SI-LABEL: i8_zext_inreg_i32_to_f32:988; SI: ; %bb.0:989; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9990; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0991; SI-NEXT: v_mov_b32_e32 v1, 0992; SI-NEXT: s_mov_b32 s6, 0993; SI-NEXT: s_mov_b32 s7, 0xf000994; SI-NEXT: s_waitcnt lgkmcnt(0)995; SI-NEXT: s_mov_b64 s[4:5], s[2:3]996; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64997; SI-NEXT: s_mov_b32 s6, -1998; SI-NEXT: s_mov_b64 s[2:3], s[6:7]999; SI-NEXT: s_waitcnt vmcnt(0)1000; SI-NEXT: v_add_i32_e32 v0, vcc, 2, v01001; SI-NEXT: v_and_b32_e32 v0, 0xff, v01002; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v01003; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01004; SI-NEXT: s_endpgm1005;1006; VI-LABEL: i8_zext_inreg_i32_to_f32:1007; VI: ; %bb.0:1008; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241009; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01010; VI-NEXT: s_waitcnt lgkmcnt(0)1011; VI-NEXT: v_mov_b32_e32 v0, s21012; VI-NEXT: v_mov_b32_e32 v1, s31013; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v21014; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1015; VI-NEXT: flat_load_dword v0, v[0:1]1016; VI-NEXT: s_waitcnt vmcnt(0)1017; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v01018; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_01019; VI-NEXT: v_mov_b32_e32 v0, s01020; VI-NEXT: v_mov_b32_e32 v1, s11021; VI-NEXT: flat_store_dword v[0:1], v21022; VI-NEXT: s_endpgm1023 %tid = call i32 @llvm.amdgcn.workitem.id.x()1024 %gep = getelementptr i32, ptr addrspace(1) %in, i32 %tid1025 %load = load i32, ptr addrspace(1) %gep, align 41026 %add = add i32 %load, 21027 %inreg = and i32 %add, 2551028 %cvt = uitofp i32 %inreg to float1029 store float %cvt, ptr addrspace(1) %out, align 41030 ret void1031}1032 1033define amdgpu_kernel void @i8_zext_inreg_hi1_to_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {1034; SI-LABEL: i8_zext_inreg_hi1_to_f32:1035; SI: ; %bb.0:1036; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91037; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01038; SI-NEXT: v_mov_b32_e32 v1, 01039; SI-NEXT: s_mov_b32 s6, 01040; SI-NEXT: s_mov_b32 s7, 0xf0001041; SI-NEXT: s_waitcnt lgkmcnt(0)1042; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1043; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr641044; SI-NEXT: s_mov_b32 s6, -11045; SI-NEXT: s_mov_b64 s[2:3], s[6:7]1046; SI-NEXT: s_waitcnt vmcnt(0)1047; SI-NEXT: v_bfe_u32 v0, v0, 8, 81048; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v01049; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01050; SI-NEXT: s_endpgm1051;1052; VI-LABEL: i8_zext_inreg_hi1_to_f32:1053; VI: ; %bb.0:1054; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241055; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01056; VI-NEXT: s_waitcnt lgkmcnt(0)1057; VI-NEXT: v_mov_b32_e32 v0, s21058; VI-NEXT: v_mov_b32_e32 v1, s31059; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v21060; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1061; VI-NEXT: flat_load_dword v0, v[0:1]1062; VI-NEXT: s_waitcnt vmcnt(0)1063; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_11064; VI-NEXT: v_mov_b32_e32 v0, s01065; VI-NEXT: v_mov_b32_e32 v1, s11066; VI-NEXT: flat_store_dword v[0:1], v21067; VI-NEXT: s_endpgm1068 %tid = call i32 @llvm.amdgcn.workitem.id.x()1069 %gep = getelementptr i32, ptr addrspace(1) %in, i32 %tid1070 %load = load i32, ptr addrspace(1) %gep, align 41071 %inreg = and i32 %load, 652801072 %shr = lshr i32 %inreg, 81073 %cvt = uitofp i32 %shr to float1074 store float %cvt, ptr addrspace(1) %out, align 41075 ret void1076}1077 1078; We don't get these ones because of the zext, but instcombine removes1079; them so it shouldn't really matter.1080define amdgpu_kernel void @i8_zext_i32_to_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {1081; SI-LABEL: i8_zext_i32_to_f32:1082; SI: ; %bb.0:1083; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91084; SI-NEXT: s_mov_b32 s6, 01085; SI-NEXT: s_mov_b32 s7, 0xf0001086; SI-NEXT: v_ashrrev_i32_e32 v1, 31, v01087; SI-NEXT: s_waitcnt lgkmcnt(0)1088; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1089; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr641090; SI-NEXT: s_mov_b32 s6, -11091; SI-NEXT: s_mov_b64 s[2:3], s[6:7]1092; SI-NEXT: s_waitcnt vmcnt(0)1093; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v01094; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01095; SI-NEXT: s_endpgm1096;1097; VI-LABEL: i8_zext_i32_to_f32:1098; VI: ; %bb.0:1099; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241100; VI-NEXT: v_ashrrev_i32_e32 v3, 31, v01101; VI-NEXT: s_waitcnt lgkmcnt(0)1102; VI-NEXT: v_mov_b32_e32 v1, s21103; VI-NEXT: v_mov_b32_e32 v2, s31104; VI-NEXT: v_add_u32_e32 v0, vcc, v1, v01105; VI-NEXT: v_addc_u32_e32 v1, vcc, v2, v3, vcc1106; VI-NEXT: flat_load_ubyte v0, v[0:1]1107; VI-NEXT: s_waitcnt vmcnt(0)1108; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v01109; VI-NEXT: v_mov_b32_e32 v0, s01110; VI-NEXT: v_mov_b32_e32 v1, s11111; VI-NEXT: flat_store_dword v[0:1], v21112; VI-NEXT: s_endpgm1113 %tid = call i32 @llvm.amdgcn.workitem.id.x()1114 %gep = getelementptr i8, ptr addrspace(1) %in, i32 %tid1115 %load = load i8, ptr addrspace(1) %gep, align 11116 %ext = zext i8 %load to i321117 %cvt = uitofp i32 %ext to float1118 store float %cvt, ptr addrspace(1) %out, align 41119 ret void1120}1121 1122define amdgpu_kernel void @v4i8_zext_v4i32_to_v4f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {1123; SI-LABEL: v4i8_zext_v4i32_to_v4f32:1124; SI: ; %bb.0:1125; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91126; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01127; SI-NEXT: v_mov_b32_e32 v1, 01128; SI-NEXT: s_mov_b32 s6, 01129; SI-NEXT: s_mov_b32 s7, 0xf0001130; SI-NEXT: s_waitcnt lgkmcnt(0)1131; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1132; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[4:7], 0 addr64 offset:11133; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[4:7], 0 addr64 offset:31134; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[4:7], 0 addr64 offset:21135; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr641136; SI-NEXT: s_mov_b32 s6, -11137; SI-NEXT: s_mov_b64 s[2:3], s[6:7]1138; SI-NEXT: s_waitcnt vmcnt(3)1139; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v21140; SI-NEXT: s_waitcnt vmcnt(2)1141; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v31142; SI-NEXT: s_waitcnt vmcnt(1)1143; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v41144; SI-NEXT: s_waitcnt vmcnt(0)1145; SI-NEXT: v_or_b32_e32 v0, v1, v01146; SI-NEXT: v_or_b32_e32 v1, v2, v31147; SI-NEXT: v_or_b32_e32 v0, v1, v01148; SI-NEXT: v_and_b32_e32 v1, 0xff, v01149; SI-NEXT: v_bfe_u32 v2, v0, 8, 81150; SI-NEXT: v_bfe_u32 v4, v0, 16, 81151; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v01152; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v11153; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v21154; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v41155; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 01156; SI-NEXT: s_endpgm1157;1158; VI-LABEL: v4i8_zext_v4i32_to_v4f32:1159; VI: ; %bb.0:1160; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241161; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01162; VI-NEXT: s_waitcnt lgkmcnt(0)1163; VI-NEXT: v_mov_b32_e32 v0, s21164; VI-NEXT: v_mov_b32_e32 v1, s31165; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v21166; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1167; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v01168; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc1169; VI-NEXT: v_add_u32_e32 v4, vcc, 2, v01170; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc1171; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v01172; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc1173; VI-NEXT: flat_load_ubyte v2, v[2:3]1174; VI-NEXT: flat_load_ubyte v3, v[6:7]1175; VI-NEXT: flat_load_ubyte v4, v[4:5]1176; VI-NEXT: flat_load_ubyte v0, v[0:1]1177; VI-NEXT: s_waitcnt vmcnt(3)1178; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v21179; VI-NEXT: s_waitcnt vmcnt(2)1180; VI-NEXT: v_lshlrev_b32_e32 v2, 24, v31181; VI-NEXT: s_waitcnt vmcnt(1)1182; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v41183; VI-NEXT: s_waitcnt vmcnt(0)1184; VI-NEXT: v_or_b32_e32 v0, v1, v01185; VI-NEXT: v_or_b32_e32 v1, v2, v31186; VI-NEXT: v_or_b32_e32 v3, v1, v01187; VI-NEXT: v_mov_b32_e32 v5, s11188; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_01189; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_11190; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_21191; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v31192; VI-NEXT: v_mov_b32_e32 v4, s01193; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]1194; VI-NEXT: s_endpgm1195 %tid = call i32 @llvm.amdgcn.workitem.id.x()1196 %gep = getelementptr <4 x i8>, ptr addrspace(1) %in, i32 %tid1197 %load = load <4 x i8>, ptr addrspace(1) %gep, align 11198 %ext = zext <4 x i8> %load to <4 x i32>1199 %cvt = uitofp <4 x i32> %ext to <4 x float>1200 store <4 x float> %cvt, ptr addrspace(1) %out, align 161201 ret void1202}1203 1204define amdgpu_kernel void @extract_byte0_to_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {1205; SI-LABEL: extract_byte0_to_f32:1206; SI: ; %bb.0:1207; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91208; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01209; SI-NEXT: v_mov_b32_e32 v1, 01210; SI-NEXT: s_mov_b32 s6, 01211; SI-NEXT: s_mov_b32 s7, 0xf0001212; SI-NEXT: s_waitcnt lgkmcnt(0)1213; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1214; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr641215; SI-NEXT: s_mov_b32 s6, -11216; SI-NEXT: s_mov_b64 s[2:3], s[6:7]1217; SI-NEXT: s_waitcnt vmcnt(0)1218; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v01219; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01220; SI-NEXT: s_endpgm1221;1222; VI-LABEL: extract_byte0_to_f32:1223; VI: ; %bb.0:1224; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241225; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01226; VI-NEXT: s_waitcnt lgkmcnt(0)1227; VI-NEXT: v_mov_b32_e32 v0, s21228; VI-NEXT: v_mov_b32_e32 v1, s31229; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v21230; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1231; VI-NEXT: flat_load_ubyte v0, v[0:1]1232; VI-NEXT: s_waitcnt vmcnt(0)1233; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v01234; VI-NEXT: v_mov_b32_e32 v0, s01235; VI-NEXT: v_mov_b32_e32 v1, s11236; VI-NEXT: flat_store_dword v[0:1], v21237; VI-NEXT: s_endpgm1238 %tid = call i32 @llvm.amdgcn.workitem.id.x()1239 %gep = getelementptr i32, ptr addrspace(1) %in, i32 %tid1240 %val = load i32, ptr addrspace(1) %gep1241 %and = and i32 %val, 2551242 %cvt = uitofp i32 %and to float1243 store float %cvt, ptr addrspace(1) %out1244 ret void1245}1246 1247define amdgpu_kernel void @extract_byte1_to_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {1248; SI-LABEL: extract_byte1_to_f32:1249; SI: ; %bb.0:1250; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91251; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01252; SI-NEXT: v_mov_b32_e32 v1, 01253; SI-NEXT: s_mov_b32 s6, 01254; SI-NEXT: s_mov_b32 s7, 0xf0001255; SI-NEXT: s_waitcnt lgkmcnt(0)1256; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1257; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr641258; SI-NEXT: s_mov_b32 s6, -11259; SI-NEXT: s_mov_b64 s[2:3], s[6:7]1260; SI-NEXT: s_waitcnt vmcnt(0)1261; SI-NEXT: v_bfe_u32 v0, v0, 8, 81262; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v01263; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01264; SI-NEXT: s_endpgm1265;1266; VI-LABEL: extract_byte1_to_f32:1267; VI: ; %bb.0:1268; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241269; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01270; VI-NEXT: s_waitcnt lgkmcnt(0)1271; VI-NEXT: v_mov_b32_e32 v0, s21272; VI-NEXT: v_mov_b32_e32 v1, s31273; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v21274; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1275; VI-NEXT: flat_load_dword v0, v[0:1]1276; VI-NEXT: s_waitcnt vmcnt(0)1277; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_11278; VI-NEXT: v_mov_b32_e32 v0, s01279; VI-NEXT: v_mov_b32_e32 v1, s11280; VI-NEXT: flat_store_dword v[0:1], v21281; VI-NEXT: s_endpgm1282 %tid = call i32 @llvm.amdgcn.workitem.id.x()1283 %gep = getelementptr i32, ptr addrspace(1) %in, i32 %tid1284 %val = load i32, ptr addrspace(1) %gep1285 %srl = lshr i32 %val, 81286 %and = and i32 %srl, 2551287 %cvt = uitofp i32 %and to float1288 store float %cvt, ptr addrspace(1) %out1289 ret void1290}1291 1292define amdgpu_kernel void @extract_byte2_to_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {1293; SI-LABEL: extract_byte2_to_f32:1294; SI: ; %bb.0:1295; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91296; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01297; SI-NEXT: v_mov_b32_e32 v1, 01298; SI-NEXT: s_mov_b32 s6, 01299; SI-NEXT: s_mov_b32 s7, 0xf0001300; SI-NEXT: s_waitcnt lgkmcnt(0)1301; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1302; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr641303; SI-NEXT: s_mov_b32 s6, -11304; SI-NEXT: s_mov_b64 s[2:3], s[6:7]1305; SI-NEXT: s_waitcnt vmcnt(0)1306; SI-NEXT: v_bfe_u32 v0, v0, 16, 81307; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v01308; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01309; SI-NEXT: s_endpgm1310;1311; VI-LABEL: extract_byte2_to_f32:1312; VI: ; %bb.0:1313; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241314; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01315; VI-NEXT: s_waitcnt lgkmcnt(0)1316; VI-NEXT: v_mov_b32_e32 v0, s21317; VI-NEXT: v_mov_b32_e32 v1, s31318; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v21319; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1320; VI-NEXT: flat_load_dword v0, v[0:1]1321; VI-NEXT: s_waitcnt vmcnt(0)1322; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_21323; VI-NEXT: v_mov_b32_e32 v0, s01324; VI-NEXT: v_mov_b32_e32 v1, s11325; VI-NEXT: flat_store_dword v[0:1], v21326; VI-NEXT: s_endpgm1327 %tid = call i32 @llvm.amdgcn.workitem.id.x()1328 %gep = getelementptr i32, ptr addrspace(1) %in, i32 %tid1329 %val = load i32, ptr addrspace(1) %gep1330 %srl = lshr i32 %val, 161331 %and = and i32 %srl, 2551332 %cvt = uitofp i32 %and to float1333 store float %cvt, ptr addrspace(1) %out1334 ret void1335}1336 1337define amdgpu_kernel void @extract_byte3_to_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {1338; SI-LABEL: extract_byte3_to_f32:1339; SI: ; %bb.0:1340; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91341; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01342; SI-NEXT: v_mov_b32_e32 v1, 01343; SI-NEXT: s_mov_b32 s6, 01344; SI-NEXT: s_mov_b32 s7, 0xf0001345; SI-NEXT: s_waitcnt lgkmcnt(0)1346; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1347; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr641348; SI-NEXT: s_mov_b32 s6, -11349; SI-NEXT: s_mov_b64 s[2:3], s[6:7]1350; SI-NEXT: s_waitcnt vmcnt(0)1351; SI-NEXT: v_cvt_f32_ubyte3_e32 v0, v01352; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01353; SI-NEXT: s_endpgm1354;1355; VI-LABEL: extract_byte3_to_f32:1356; VI: ; %bb.0:1357; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241358; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01359; VI-NEXT: s_waitcnt lgkmcnt(0)1360; VI-NEXT: v_mov_b32_e32 v0, s21361; VI-NEXT: v_mov_b32_e32 v1, s31362; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v21363; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1364; VI-NEXT: flat_load_dword v0, v[0:1]1365; VI-NEXT: s_waitcnt vmcnt(0)1366; VI-NEXT: v_cvt_f32_ubyte3_e32 v2, v01367; VI-NEXT: v_mov_b32_e32 v0, s01368; VI-NEXT: v_mov_b32_e32 v1, s11369; VI-NEXT: flat_store_dword v[0:1], v21370; VI-NEXT: s_endpgm1371 %tid = call i32 @llvm.amdgcn.workitem.id.x()1372 %gep = getelementptr i32, ptr addrspace(1) %in, i32 %tid1373 %val = load i32, ptr addrspace(1) %gep1374 %srl = lshr i32 %val, 241375 %and = and i32 %srl, 2551376 %cvt = uitofp i32 %and to float1377 store float %cvt, ptr addrspace(1) %out1378 ret void1379}1380 1381define amdgpu_kernel void @cvt_ubyte0_or_multiuse(ptr addrspace(1) %in, ptr addrspace(1) %out) {1382; SI-LABEL: cvt_ubyte0_or_multiuse:1383; SI: ; %bb.0: ; %bb1384; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91385; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v01386; SI-NEXT: v_mov_b32_e32 v1, 01387; SI-NEXT: s_mov_b32 s6, 01388; SI-NEXT: s_mov_b32 s7, 0xf0001389; SI-NEXT: s_waitcnt lgkmcnt(0)1390; SI-NEXT: s_mov_b64 s[4:5], s[0:1]1391; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr641392; SI-NEXT: s_mov_b32 s6, -11393; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1394; SI-NEXT: s_waitcnt vmcnt(0)1395; SI-NEXT: v_or_b32_e32 v0, 0x80000001, v01396; SI-NEXT: v_and_b32_e32 v1, 0xff, v01397; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v11398; SI-NEXT: v_add_f32_e32 v0, v0, v11399; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01400; SI-NEXT: s_endpgm1401;1402; VI-LABEL: cvt_ubyte0_or_multiuse:1403; VI: ; %bb.0: ; %bb1404; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241405; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v01406; VI-NEXT: s_waitcnt lgkmcnt(0)1407; VI-NEXT: v_mov_b32_e32 v0, s01408; VI-NEXT: v_mov_b32_e32 v1, s11409; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v21410; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1411; VI-NEXT: flat_load_dword v0, v[0:1]1412; VI-NEXT: s_waitcnt vmcnt(0)1413; VI-NEXT: v_or_b32_e32 v0, 0x80000001, v01414; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_01415; VI-NEXT: v_add_f32_e32 v2, v0, v11416; VI-NEXT: v_mov_b32_e32 v0, s21417; VI-NEXT: v_mov_b32_e32 v1, s31418; VI-NEXT: flat_store_dword v[0:1], v21419; VI-NEXT: s_endpgm1420bb:1421 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()1422 %gep = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %lid1423 %load = load i32, ptr addrspace(1) %gep1424 %or = or i32 %load, -21474836471425 %and = and i32 %or, 2551426 %uitofp = uitofp i32 %and to float1427 %cast = bitcast i32 %or to float1428 %add = fadd float %cast, %uitofp1429 store float %add, ptr addrspace(1) %out1430 ret void1431}1432 1433define float @v_test_sitofp_i64_byte_to_f32(i64 %arg0) {1434; SI-LABEL: v_test_sitofp_i64_byte_to_f32:1435; SI: ; %bb.0:1436; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1437; SI-NEXT: v_ffbh_i32_e32 v2, 01438; SI-NEXT: v_add_i32_e32 v2, vcc, -1, v21439; SI-NEXT: v_and_b32_e32 v0, 0xff, v01440; SI-NEXT: v_mov_b32_e32 v1, 01441; SI-NEXT: v_min_u32_e32 v2, 32, v21442; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v21443; SI-NEXT: v_min_u32_e32 v0, 1, v01444; SI-NEXT: v_or_b32_e32 v0, v1, v01445; SI-NEXT: v_cvt_f32_i32_e32 v0, v01446; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v21447; SI-NEXT: v_ldexp_f32_e32 v0, v0, v11448; SI-NEXT: s_setpc_b64 s[30:31]1449;1450; VI-LABEL: v_test_sitofp_i64_byte_to_f32:1451; VI: ; %bb.0:1452; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1453; VI-NEXT: v_ffbh_i32_e32 v2, 01454; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v21455; VI-NEXT: v_and_b32_e32 v0, 0xff, v01456; VI-NEXT: v_mov_b32_e32 v1, 01457; VI-NEXT: v_min_u32_e32 v2, 32, v21458; VI-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]1459; VI-NEXT: v_min_u32_e32 v0, 1, v01460; VI-NEXT: v_or_b32_e32 v0, v1, v01461; VI-NEXT: v_cvt_f32_i32_e32 v0, v01462; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v21463; VI-NEXT: v_ldexp_f32 v0, v0, v11464; VI-NEXT: s_setpc_b64 s[30:31]1465 %masked = and i64 %arg0, 2551466 %itofp = sitofp i64 %masked to float1467 ret float %itofp1468}1469 1470define float @v_test_uitofp_i64_byte_to_f32(i64 %arg0) {1471; SI-LABEL: v_test_uitofp_i64_byte_to_f32:1472; SI: ; %bb.0:1473; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1474; SI-NEXT: v_ffbh_u32_e32 v2, 01475; SI-NEXT: v_and_b32_e32 v0, 0xff, v01476; SI-NEXT: v_mov_b32_e32 v1, 01477; SI-NEXT: v_min_u32_e32 v2, 32, v21478; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v21479; SI-NEXT: v_min_u32_e32 v0, 1, v01480; SI-NEXT: v_or_b32_e32 v0, v1, v01481; SI-NEXT: v_cvt_f32_u32_e32 v0, v01482; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v21483; SI-NEXT: v_ldexp_f32_e32 v0, v0, v11484; SI-NEXT: s_setpc_b64 s[30:31]1485;1486; VI-LABEL: v_test_uitofp_i64_byte_to_f32:1487; VI: ; %bb.0:1488; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1489; VI-NEXT: v_ffbh_u32_e32 v2, 01490; VI-NEXT: v_and_b32_e32 v0, 0xff, v01491; VI-NEXT: v_mov_b32_e32 v1, 01492; VI-NEXT: v_min_u32_e32 v2, 32, v21493; VI-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]1494; VI-NEXT: v_min_u32_e32 v0, 1, v01495; VI-NEXT: v_or_b32_e32 v0, v1, v01496; VI-NEXT: v_cvt_f32_u32_e32 v0, v01497; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v21498; VI-NEXT: v_ldexp_f32 v0, v0, v11499; VI-NEXT: s_setpc_b64 s[30:31]1500 %masked = and i64 %arg0, 2551501 %itofp = uitofp i64 %masked to float1502 ret float %itofp1503}1504 1505define float @v_test_sitofp_i16_byte_to_f32(i16 %arg0) {1506; SI-LABEL: v_test_sitofp_i16_byte_to_f32:1507; SI: ; %bb.0:1508; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1509; SI-NEXT: v_and_b32_e32 v0, 0xff, v01510; SI-NEXT: v_bfe_i32 v0, v0, 0, 161511; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v01512; SI-NEXT: s_setpc_b64 s[30:31]1513;1514; VI-LABEL: v_test_sitofp_i16_byte_to_f32:1515; VI: ; %bb.0:1516; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1517; VI-NEXT: v_and_b32_e32 v0, 0xff, v01518; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_01519; VI-NEXT: s_setpc_b64 s[30:31]1520 %masked = and i16 %arg0, 2551521 %itofp = sitofp i16 %masked to float1522 ret float %itofp1523}1524 1525define float @v_test_uitofp_i16_byte_to_f32(i16 %arg0) {1526; SI-LABEL: v_test_uitofp_i16_byte_to_f32:1527; SI: ; %bb.0:1528; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1529; SI-NEXT: v_and_b32_e32 v0, 0xff, v01530; SI-NEXT: v_and_b32_e32 v0, 0xffff, v01531; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v01532; SI-NEXT: s_setpc_b64 s[30:31]1533;1534; VI-LABEL: v_test_uitofp_i16_byte_to_f32:1535; VI: ; %bb.0:1536; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1537; VI-NEXT: v_mov_b32_e32 v1, 0xffff1538; VI-NEXT: v_and_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_01539; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v01540; VI-NEXT: s_setpc_b64 s[30:31]1541 %masked = and i16 %arg0, 2551542 %itofp = uitofp i16 %masked to float1543 ret float %itofp1544}1545