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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji -stop-after=irtranslator -o - %s | FileCheck %s3 4declare align(8) dereferenceable(8) ptr @declared_with_ret_deref() #05declare align(8) ptr @unknown_decl() #06declare align(8) dereferenceable(4) ptr @declared_with_ret_deref4() #07declare align(8) dereferenceable_or_null(8) ptr @declared_with_ret_deref_or_null() #08declare align(8) nonnull ptr @nonnull_decl() #09declare align(8) dereferenceable_or_null(4) ptr @declared_with_ret_deref_or_null4() #010 11; Should have dereferenceable on mem operand12define i64 @load_deref_declaration_only() {13 ; CHECK-LABEL: name: load_deref_declaration_only14 ; CHECK: bb.1 (%ir-block.0):15 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc16 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @declared_with_ret_deref17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr318 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)19 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @declared_with_ret_deref, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr120 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr021 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr122 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)23 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc24 ; CHECK-NEXT: [[ASSERT_ALIGN:%[0-9]+]]:_(p0) = G_ASSERT_ALIGN [[MV]], 825 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[ASSERT_ALIGN]](p0) :: (dereferenceable load (s64) from %ir.call)26 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)27 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)28 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)29 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr130 %call = call ptr @declared_with_ret_deref()31 %load = load i64, ptr %call, align 832 ret i64 %load33}34 35; No dereferenceable on mem operand36define i64 @load_deref_unknown_decl() {37 ; CHECK-LABEL: name: load_deref_unknown_decl38 ; CHECK: bb.1 (%ir-block.0):39 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc40 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @unknown_decl41 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr342 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)43 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @unknown_decl, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr144 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr045 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr146 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)47 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc48 ; CHECK-NEXT: [[ASSERT_ALIGN:%[0-9]+]]:_(p0) = G_ASSERT_ALIGN [[MV]], 849 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[ASSERT_ALIGN]](p0) :: (load (s64) from %ir.call)50 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)51 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)52 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)53 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr154 %call = call ptr @unknown_decl()55 %load = load i64, ptr %call, align 856 ret i64 %load57}58 59; Should have dereferenceable on mem operand60define i64 @load_deref_callsite_only() {61 ; CHECK-LABEL: name: load_deref_callsite_only62 ; CHECK: bb.1 (%ir-block.0):63 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc64 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @unknown_decl65 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr366 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)67 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @unknown_decl, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr168 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr069 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr170 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)71 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc72 ; CHECK-NEXT: [[ASSERT_ALIGN:%[0-9]+]]:_(p0) = G_ASSERT_ALIGN [[MV]], 873 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[ASSERT_ALIGN]](p0) :: (dereferenceable load (s64) from %ir.call)74 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)75 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)76 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)77 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr178 %call = call dereferenceable(8) ptr @unknown_decl()79 %load = load i64, ptr %call, align 880 ret i64 %load81}82 83; Both loads should have effective dereferenceable(8) since the84; maximum should be used.85define i64 @load_deref_maxmimum_callsite_declaration_only() {86 ; CHECK-LABEL: name: load_deref_maxmimum_callsite_declaration_only87 ; CHECK: bb.1 (%ir-block.0):88 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc89 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @declared_with_ret_deref90 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr391 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)92 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @declared_with_ret_deref, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr193 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr094 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr195 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)96 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc97 ; CHECK-NEXT: [[ASSERT_ALIGN:%[0-9]+]]:_(p0) = G_ASSERT_ALIGN [[MV]], 898 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[ASSERT_ALIGN]](p0) :: (dereferenceable load (s64) from %ir.call0)99 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc100 ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @declared_with_ret_deref4101 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3102 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY3]](<4 x s32>)103 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV1]](p0), @declared_with_ret_deref4, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1104 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr0105 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr1106 ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)107 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc108 ; CHECK-NEXT: [[ASSERT_ALIGN1:%[0-9]+]]:_(p0) = G_ASSERT_ALIGN [[MV1]], 8109 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[ASSERT_ALIGN1]](p0) :: (dereferenceable load (s64) from %ir.call1)110 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LOAD]], [[LOAD1]]111 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ADD]](s64)112 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)113 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)114 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1115 %call0 = call dereferenceable(4) ptr @declared_with_ret_deref()116 %load0 = load i64, ptr %call0, align 8117 %call1 = call dereferenceable(8) ptr @declared_with_ret_deref4()118 %load1 = load i64, ptr %call1, align 8119 %add = add i64 %load0, %load1120 ret i64 %add121}122 123; Should have deref_or_nullerenceable on mem operand124define i64 @load_deref_or_null_declaration_only() {125 ; CHECK-LABEL: name: load_deref_or_null_declaration_only126 ; CHECK: bb.1 (%ir-block.0):127 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc128 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @declared_with_ret_deref_or_null129 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3130 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)131 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @declared_with_ret_deref_or_null, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1132 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0133 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1134 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)135 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc136 ; CHECK-NEXT: [[ASSERT_ALIGN:%[0-9]+]]:_(p0) = G_ASSERT_ALIGN [[MV]], 8137 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[ASSERT_ALIGN]](p0) :: (dereferenceable load (s64) from %ir.call)138 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)139 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)140 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)141 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1142 %call = call nonnull ptr @declared_with_ret_deref_or_null()143 %load = load i64, ptr %call, align 8144 ret i64 %load145}146 147; No deref_or_nullerenceable on mem operand148define i64 @load_deref_or_null_nonnull_decl() {149 ; CHECK-LABEL: name: load_deref_or_null_nonnull_decl150 ; CHECK: bb.1 (%ir-block.0):151 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc152 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @nonnull_decl153 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3154 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)155 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @nonnull_decl, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1156 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0157 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1158 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)159 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc160 ; CHECK-NEXT: [[ASSERT_ALIGN:%[0-9]+]]:_(p0) = G_ASSERT_ALIGN [[MV]], 8161 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[ASSERT_ALIGN]](p0) :: (load (s64) from %ir.call)162 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)163 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)164 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)165 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1166 %call = call ptr @nonnull_decl()167 %load = load i64, ptr %call, align 8168 ret i64 %load169}170 171; Should have deref_or_nullerenceable on mem operand172define i64 @load_deref_or_null_callsite_only() {173 ; CHECK-LABEL: name: load_deref_or_null_callsite_only174 ; CHECK: bb.1 (%ir-block.0):175 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc176 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @nonnull_decl177 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3178 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)179 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @nonnull_decl, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1180 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0181 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1182 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)183 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc184 ; CHECK-NEXT: [[ASSERT_ALIGN:%[0-9]+]]:_(p0) = G_ASSERT_ALIGN [[MV]], 8185 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[ASSERT_ALIGN]](p0) :: (dereferenceable load (s64) from %ir.call)186 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)187 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)188 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)189 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1190 %call = call dereferenceable_or_null(8) ptr @nonnull_decl()191 %load = load i64, ptr %call, align 8192 ret i64 %load193}194 195; Both loads should have effective deref_or_nullerenceable(8) since the196; maximum should be used.197define i64 @load_deref_or_null_maxmimum_callsite_declaration_only() {198 ; CHECK-LABEL: name: load_deref_or_null_maxmimum_callsite_declaration_only199 ; CHECK: bb.1 (%ir-block.0):200 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc201 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @declared_with_ret_deref_or_null202 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3203 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)204 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @declared_with_ret_deref_or_null, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1205 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0206 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr1207 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)208 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc209 ; CHECK-NEXT: [[ASSERT_ALIGN:%[0-9]+]]:_(p0) = G_ASSERT_ALIGN [[MV]], 8210 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[ASSERT_ALIGN]](p0) :: (dereferenceable load (s64) from %ir.call0)211 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc212 ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @declared_with_ret_deref_or_null4213 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3214 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY3]](<4 x s32>)215 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV1]](p0), @declared_with_ret_deref_or_null4, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $vgpr0, implicit-def $vgpr1216 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr0217 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr1218 ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)219 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc220 ; CHECK-NEXT: [[ASSERT_ALIGN1:%[0-9]+]]:_(p0) = G_ASSERT_ALIGN [[MV1]], 8221 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[ASSERT_ALIGN1]](p0) :: (dereferenceable load (s64) from %ir.call1)222 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LOAD]], [[LOAD1]]223 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ADD]](s64)224 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)225 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)226 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1227 %call0 = call dereferenceable_or_null(4) nonnull ptr @declared_with_ret_deref_or_null()228 %load0 = load i64, ptr %call0, align 8229 %call1 = call dereferenceable_or_null(8) nonnull ptr @declared_with_ret_deref_or_null4()230 %load1 = load i64, ptr %call1, align 8231 %add = add i64 %load0, %load1232 ret i64 %add233}234 235attributes #0 = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }236