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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s3 4--- |5 define void @divergent_i1_phi_uniform_branch() {ret void}6 define void @divergent_i1_phi_uniform_branch_simple() {ret void}7 define void @divergent_i1_phi_used_inside_loop() {ret void}8 define void @divergent_i1_phi_used_inside_loop_bigger_loop_body() {ret void}9 define void @single_lane_execution_attribute() #0 {ret void}10 11 attributes #0 = {"amdgpu-flat-work-group-size"="1,1"}12...13 14---15name: divergent_i1_phi_uniform_branch16legalized: true17tracksRegLiveness: true18body: |19 ; GFX10-LABEL: name: divergent_i1_phi_uniform_branch20 ; GFX10: bb.0:21 ; GFX10-NEXT: successors: %bb.1(0x30000000), %bb.2(0x50000000)22 ; GFX10-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr423 ; GFX10-NEXT: {{ $}}24 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr025 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr126 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)27 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr228 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr029 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr330 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr431 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)32 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 633 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C]]34 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 035 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY3]](s32), [[C1]]36 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)37 ; GFX10-NEXT: G_BRCOND [[ICMP1]](s1), %bb.238 ; GFX10-NEXT: G_BR %bb.139 ; GFX10-NEXT: {{ $}}40 ; GFX10-NEXT: bb.1:41 ; GFX10-NEXT: successors: %bb.3(0x80000000)42 ; GFX10-NEXT: {{ $}}43 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12344 ; GFX10-NEXT: G_STORE [[C2]](s32), [[MV1]](p1) :: (store (s32), addrspace 1)45 ; GFX10-NEXT: G_BR %bb.346 ; GFX10-NEXT: {{ $}}47 ; GFX10-NEXT: bb.2:48 ; GFX10-NEXT: successors: %bb.4(0x80000000)49 ; GFX10-NEXT: {{ $}}50 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY6]](s1), %bb.0, %20(s1), %bb.351 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)52 ; GFX10-NEXT: G_BR %bb.453 ; GFX10-NEXT: {{ $}}54 ; GFX10-NEXT: bb.3:55 ; GFX10-NEXT: successors: %bb.2(0x80000000)56 ; GFX10-NEXT: {{ $}}57 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 158 ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C3]]59 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)60 ; GFX10-NEXT: G_BR %bb.261 ; GFX10-NEXT: {{ $}}62 ; GFX10-NEXT: bb.4:63 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY7]](s1)64 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 265 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT]], [[C4]]66 ; GFX10-NEXT: G_STORE [[ADD]](s32), [[MV]](p1) :: (store (s32), addrspace 1)67 ; GFX10-NEXT: S_ENDPGM 068 bb.0:69 successors: %bb.1(0x30000000), %bb.2(0x50000000)70 liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr471 72 %0:_(s32) = COPY $vgpr073 %1:_(s32) = COPY $vgpr174 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)75 %3:_(s32) = COPY $vgpr276 %4:_(s32) = COPY $sgpr077 %5:_(s32) = COPY $vgpr378 %6:_(s32) = COPY $vgpr479 %7:_(p1) = G_MERGE_VALUES %5(s32), %6(s32)80 %8:_(s32) = G_CONSTANT i32 681 %9:_(s1) = G_ICMP intpred(uge), %3(s32), %882 %10:_(s32) = G_CONSTANT i32 083 %11:_(s1) = G_ICMP intpred(ne), %4(s32), %1084 G_BRCOND %11(s1), %bb.285 G_BR %bb.186 87 bb.1:88 successors: %bb.3(0x80000000)89 90 %12:_(s32) = G_CONSTANT i32 12391 G_STORE %12(s32), %7(p1) :: (store (s32), addrspace 1)92 G_BR %bb.393 94 bb.2:95 successors: %bb.4(0x80000000)96 97 %13:_(s1) = G_PHI %14(s1), %bb.3, %9(s1), %bb.098 G_BR %bb.499 100 bb.3:101 successors: %bb.2(0x80000000)102 103 %15:_(s32) = G_CONSTANT i32 1104 %14:_(s1) = G_ICMP intpred(ult), %3(s32), %15105 G_BR %bb.2106 107 bb.4:108 %16:_(s32) = G_SEXT %13(s1)109 %17:_(s32) = G_CONSTANT i32 2110 %18:_(s32) = G_ADD %16, %17111 G_STORE %18(s32), %2(p1) :: (store (s32), addrspace 1)112 S_ENDPGM 0113...114 115---116name: divergent_i1_phi_uniform_branch_simple117legalized: true118tracksRegLiveness: true119body: |120 ; GFX10-LABEL: name: divergent_i1_phi_uniform_branch_simple121 ; GFX10: bb.0:122 ; GFX10-NEXT: successors: %bb.1(0x30000000), %bb.2(0x50000000)123 ; GFX10-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2124 ; GFX10-NEXT: {{ $}}125 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0126 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1127 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)128 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2129 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr0130 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6131 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C]]132 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0133 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY3]](s32), [[C1]]134 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)135 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[COPY4]](s1)136 ; GFX10-NEXT: G_BRCOND [[ICMP1]](s1), %bb.2137 ; GFX10-NEXT: G_BR %bb.1138 ; GFX10-NEXT: {{ $}}139 ; GFX10-NEXT: bb.1:140 ; GFX10-NEXT: successors: %bb.2(0x80000000)141 ; GFX10-NEXT: {{ $}}142 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1143 ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C2]]144 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)145 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY5]](s1), $exec_lo, implicit-def $scc146 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY6]](s1), implicit-def $scc147 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc148 ; GFX10-NEXT: {{ $}}149 ; GFX10-NEXT: bb.2:150 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY4]](s1), %bb.0, [[S_OR_B32_]](s1), %bb.1151 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)152 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY7]](s1)153 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2154 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT]], [[C3]]155 ; GFX10-NEXT: G_STORE [[ADD]](s32), [[MV]](p1) :: (store (s32), addrspace 1)156 ; GFX10-NEXT: S_ENDPGM 0157 bb.0:158 successors: %bb.1(0x30000000), %bb.2(0x50000000)159 liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2160 161 %0:_(s32) = COPY $vgpr0162 %1:_(s32) = COPY $vgpr1163 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)164 %3:_(s32) = COPY $vgpr2165 %4:_(s32) = COPY $sgpr0166 %5:_(s32) = G_CONSTANT i32 6167 %6:_(s1) = G_ICMP intpred(uge), %3(s32), %5168 %7:_(s32) = G_CONSTANT i32 0169 %8:_(s1) = G_ICMP intpred(ne), %4(s32), %7170 G_BRCOND %8(s1), %bb.2171 G_BR %bb.1172 173 bb.1:174 successors: %bb.2(0x80000000)175 176 %9:_(s32) = G_CONSTANT i32 1177 %10:_(s1) = G_ICMP intpred(ult), %3(s32), %9178 179 bb.2:180 %11:_(s1) = G_PHI %6(s1), %bb.0, %10(s1), %bb.1181 %12:_(s32) = G_SEXT %11(s1)182 %13:_(s32) = G_CONSTANT i32 2183 %14:_(s32) = G_ADD %12, %13184 G_STORE %14(s32), %2(p1) :: (store (s32), addrspace 1)185 S_ENDPGM 0186...187 188---189name: divergent_i1_phi_used_inside_loop190legalized: true191tracksRegLiveness: true192body: |193 ; GFX10-LABEL: name: divergent_i1_phi_used_inside_loop194 ; GFX10: bb.0:195 ; GFX10-NEXT: successors: %bb.1(0x80000000)196 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2197 ; GFX10-NEXT: {{ $}}198 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0199 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1200 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2201 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)202 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0203 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true204 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF205 ; GFX10-NEXT: {{ $}}206 ; GFX10-NEXT: bb.1:207 ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)208 ; GFX10-NEXT: {{ $}}209 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %19(s1), %bb.1210 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C]](s32), %bb.0211 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %9(s32), %bb.1212 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C1]](s1), %bb.0, %11(s1), %bb.1213 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)214 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true215 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI3]], [[C2]]216 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)217 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI2]](s32)218 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]219 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1220 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C3]]221 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI1]](s32)222 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY3]](s1), $exec_lo, implicit-def $scc223 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY4]](s1), implicit-def $scc224 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc225 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec226 ; GFX10-NEXT: G_BR %bb.2227 ; GFX10-NEXT: {{ $}}228 ; GFX10-NEXT: bb.2:229 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)230 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00231 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00232 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[S_OR_B32_]](s1), [[C5]], [[C4]]233 ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32))234 ; GFX10-NEXT: SI_RETURN235 bb.0:236 successors: %bb.1(0x80000000)237 liveins: $vgpr0, $vgpr1, $vgpr2238 239 %0:_(s32) = COPY $vgpr0240 %1:_(s32) = COPY $vgpr1241 %2:_(s32) = COPY $vgpr2242 %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32)243 %4:_(s32) = G_CONSTANT i32 0244 %5:_(s1) = G_CONSTANT i1 true245 246 bb.1:247 successors: %bb.2(0x04000000), %bb.1(0x7c000000)248 249 %6:_(s32) = G_PHI %7(s32), %bb.1, %4(s32), %bb.0250 %8:_(s32) = G_PHI %4(s32), %bb.0, %9(s32), %bb.1251 %10:_(s1) = G_PHI %5(s1), %bb.0, %11(s1), %bb.1252 %12:_(s1) = G_CONSTANT i1 true253 %11:_(s1) = G_XOR %10, %12254 %13:_(s32) = G_UITOFP %8(s32)255 %14:_(s1) = G_FCMP floatpred(ogt), %13(s32), %0256 %15:_(s32) = G_CONSTANT i32 1257 %9:_(s32) = G_ADD %8, %15258 %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %14(s1), %6(s32)259 SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec260 G_BR %bb.2261 262 bb.2:263 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %7(s32)264 %16:_(s32) = G_FCONSTANT float 0.000000e+00265 %17:_(s32) = G_FCONSTANT float 1.000000e+00266 %18:_(s32) = G_SELECT %11(s1), %17, %16267 G_STORE %18(s32), %3(p0) :: (store (s32))268 SI_RETURN269...270 271---272name: divergent_i1_phi_used_inside_loop_bigger_loop_body273legalized: true274tracksRegLiveness: true275body: |276 ; GFX10-LABEL: name: divergent_i1_phi_used_inside_loop_bigger_loop_body277 ; GFX10: bb.0:278 ; GFX10-NEXT: successors: %bb.1(0x80000000)279 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7280 ; GFX10-NEXT: {{ $}}281 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0282 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1283 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2284 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3285 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)286 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4287 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5288 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)289 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6290 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7291 ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)292 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00293 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY1]](s32), [[C]]294 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0295 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF296 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[FCMP]](s1)297 ; GFX10-NEXT: {{ $}}298 ; GFX10-NEXT: bb.1:299 ; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)300 ; GFX10-NEXT: {{ $}}301 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY8]](s1), %bb.0, %44(s1), %bb.5302 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %36(s1), %bb.5303 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %15(s32), %bb.5, [[C1]](s32), %bb.0304 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %17(s32), %bb.5305 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)306 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)307 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000308 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[PHI3]](s32), [[C2]]309 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true310 ; GFX10-NEXT: G_BRCOND [[ICMP]](s1), %bb.4311 ; GFX10-NEXT: G_BR %bb.2312 ; GFX10-NEXT: {{ $}}313 ; GFX10-NEXT: bb.2:314 ; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)315 ; GFX10-NEXT: {{ $}}316 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s1) = G_PHI %24(s1), %bb.4, [[C3]](s1), %bb.1317 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true318 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI4]], [[C4]]319 ; GFX10-NEXT: G_BRCOND [[XOR]](s1), %bb.5320 ; GFX10-NEXT: G_BR %bb.3321 ; GFX10-NEXT: {{ $}}322 ; GFX10-NEXT: bb.3:323 ; GFX10-NEXT: successors: %bb.5(0x80000000)324 ; GFX10-NEXT: {{ $}}325 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000326 ; GFX10-NEXT: G_STORE [[C5]](s32), [[MV1]](p0) :: (store (s32))327 ; GFX10-NEXT: G_BR %bb.5328 ; GFX10-NEXT: {{ $}}329 ; GFX10-NEXT: bb.4:330 ; GFX10-NEXT: successors: %bb.2(0x80000000)331 ; GFX10-NEXT: {{ $}}332 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000333 ; GFX10-NEXT: G_STORE [[C6]](s32), [[MV2]](p0) :: (store (s32))334 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s1) = G_CONSTANT i1 false335 ; GFX10-NEXT: G_BR %bb.2336 ; GFX10-NEXT: {{ $}}337 ; GFX10-NEXT: bb.5:338 ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000)339 ; GFX10-NEXT: {{ $}}340 ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s1) = G_CONSTANT i1 true341 ; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[COPY9]], [[C8]]342 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[XOR1]](s1)343 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI3]](s32)344 ; GFX10-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]345 ; GFX10-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 1346 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI3]], [[C9]]347 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP1]](s1), [[PHI2]](s32)348 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc349 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc350 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc351 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[XOR1]](s1)352 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec353 ; GFX10-NEXT: G_BR %bb.6354 ; GFX10-NEXT: {{ $}}355 ; GFX10-NEXT: bb.6:356 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)357 ; GFX10-NEXT: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00358 ; GFX10-NEXT: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00359 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[S_OR_B32_]](s1), [[C11]], [[C10]]360 ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32))361 ; GFX10-NEXT: SI_RETURN362 bb.0:363 successors: %bb.1(0x80000000)364 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7365 366 %0:_(s32) = COPY $vgpr0367 %1:_(s32) = COPY $vgpr1368 %2:_(s32) = COPY $vgpr2369 %3:_(s32) = COPY $vgpr3370 %4:_(p0) = G_MERGE_VALUES %2(s32), %3(s32)371 %5:_(s32) = COPY $vgpr4372 %6:_(s32) = COPY $vgpr5373 %7:_(p0) = G_MERGE_VALUES %5(s32), %6(s32)374 %8:_(s32) = COPY $vgpr6375 %9:_(s32) = COPY $vgpr7376 %10:_(p0) = G_MERGE_VALUES %8(s32), %9(s32)377 %11:_(s32) = G_FCONSTANT float 1.000000e+00378 %12:_(s1) = G_FCMP floatpred(ogt), %1(s32), %11379 %13:_(s32) = G_CONSTANT i32 0380 381 bb.1:382 successors: %bb.4(0x40000000), %bb.2(0x40000000)383 384 %14:_(s32) = G_PHI %15(s32), %bb.5, %13(s32), %bb.0385 %16:_(s32) = G_PHI %13(s32), %bb.0, %17(s32), %bb.5386 %18:_(s1) = G_PHI %12(s1), %bb.0, %19(s1), %bb.5387 %20:_(s32) = G_CONSTANT i32 1000388 %21:_(s1) = G_ICMP intpred(sle), %16(s32), %20389 %22:_(s1) = G_CONSTANT i1 true390 G_BRCOND %21(s1), %bb.4391 G_BR %bb.2392 393 bb.2:394 successors: %bb.3(0x40000000), %bb.5(0x40000000)395 396 %23:_(s1) = G_PHI %24(s1), %bb.4, %22(s1), %bb.1397 %25:_(s1) = G_CONSTANT i1 true398 %26:_(s1) = G_XOR %23, %25399 G_BRCOND %26(s1), %bb.5400 G_BR %bb.3401 402 bb.3:403 successors: %bb.5(0x80000000)404 405 %27:_(s32) = G_CONSTANT i32 1000406 G_STORE %27(s32), %7(p0) :: (store (s32))407 G_BR %bb.5408 409 bb.4:410 successors: %bb.2(0x80000000)411 412 %28:_(s32) = G_CONSTANT i32 1000413 G_STORE %28(s32), %10(p0) :: (store (s32))414 %24:_(s1) = G_CONSTANT i1 false415 G_BR %bb.2416 417 bb.5:418 successors: %bb.6(0x04000000), %bb.1(0x7c000000)419 420 %29:_(s1) = G_CONSTANT i1 true421 %19:_(s1) = G_XOR %18, %29422 %30:_(s32) = G_UITOFP %16(s32)423 %31:_(s1) = G_FCMP floatpred(ogt), %30(s32), %0424 %32:_(s32) = G_CONSTANT i32 1425 %17:_(s32) = G_ADD %16, %32426 %15:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %31(s1), %14(s32)427 SI_LOOP %15(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec428 G_BR %bb.6429 430 bb.6:431 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)432 %33:_(s32) = G_FCONSTANT float 0.000000e+00433 %34:_(s32) = G_FCONSTANT float 1.000000e+00434 %35:_(s32) = G_SELECT %19(s1), %34, %33435 G_STORE %35(s32), %4(p0) :: (store (s32))436 SI_RETURN437...438 439---440name: single_lane_execution_attribute441legalized: true442tracksRegLiveness: true443body: |444 ; GFX10-LABEL: name: single_lane_execution_attribute445 ; GFX10: bb.0:446 ; GFX10-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)447 ; GFX10-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2448 ; GFX10-NEXT: {{ $}}449 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0450 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1451 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr0452 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF453 ; GFX10-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.getpc)454 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296455 ; GFX10-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[INT]], [[C]]456 ; GFX10-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)457 ; GFX10-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[ZEXT]]458 ; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[OR]](s64)459 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[INTTOPTR]](p4) :: (invariant load (<8 x s32>), align 16, addrspace 4)460 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0461 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1462 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2463 ; GFX10-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[LOAD]](<8 x s32>)464 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1465 ; GFX10-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), [[C4]](s32), [[C1]](s32)466 ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.hi), [[C4]](s32), [[INT1]](s32)467 ; GFX10-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[INT2]]468 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FREEZE]], [[C3]](s32)469 ; GFX10-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_BUFFER_LOAD [[UV]](<4 x s32>), [[C1]](s32), [[SHL]], [[C1]], 0, 0, 0 :: (dereferenceable load (s32), align 1, addrspace 8)470 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AMDGPU_BUFFER_LOAD]](s32), [[C1]]471 ; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[FREEZE]], [[C2]]472 ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[AND1]](s32)473 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 true474 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[TRUNC]], [[C5]]475 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32(s1) = COPY [[C5]](s1)476 ; GFX10-NEXT: G_BRCOND [[XOR]](s1), %bb.2477 ; GFX10-NEXT: G_BR %bb.1478 ; GFX10-NEXT: {{ $}}479 ; GFX10-NEXT: bb.1:480 ; GFX10-NEXT: successors: %bb.3(0x80000000)481 ; GFX10-NEXT: {{ $}}482 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0483 ; GFX10-NEXT: G_BR %bb.3484 ; GFX10-NEXT: {{ $}}485 ; GFX10-NEXT: bb.2:486 ; GFX10-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)487 ; GFX10-NEXT: {{ $}}488 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY3]](s1), %bb.0, %57(s1), %bb.4489 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %29(s32), %bb.4, [[DEF]](s32), %bb.0490 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)491 ; GFX10-NEXT: G_BRCOND [[COPY4]](s1), %bb.5492 ; GFX10-NEXT: G_BR %bb.6493 ; GFX10-NEXT: {{ $}}494 ; GFX10-NEXT: bb.3:495 ; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000)496 ; GFX10-NEXT: {{ $}}497 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %33(s32), %bb.3, [[C6]](s32), %bb.1498 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI %35(s32), %bb.3, [[FREEZE]](s32), %bb.1499 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI %37(s32), %bb.3, [[C6]](s32), %bb.1500 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0501 ; GFX10-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:_(s32) = G_AMDGPU_BUFFER_LOAD [[UV]](<4 x s32>), [[C7]](s32), [[PHI2]], [[C7]], 0, 0, 0 :: (dereferenceable load (s32), align 1, addrspace 8)502 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AMDGPU_BUFFER_LOAD1]], [[PHI4]]503 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32), implicit $exec_lo504 ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1505 ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI3]], [[C8]]506 ; GFX10-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 4507 ; GFX10-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C9]]508 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD1]](s32), [[C7]]509 ; GFX10-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3510 ; GFX10-NEXT: G_BR %bb.4511 ; GFX10-NEXT: {{ $}}512 ; GFX10-NEXT: bb.4:513 ; GFX10-NEXT: successors: %bb.2(0x80000000)514 ; GFX10-NEXT: {{ $}}515 ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY5]](s32), [[AMDGPU_BUFFER_LOAD]]516 ; GFX10-NEXT: [[OR1:%[0-9]+]]:_(s1) = G_OR [[ICMP]], [[ICMP2]]517 ; GFX10-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s1)518 ; GFX10-NEXT: [[C10:%[0-9]+]]:_(s1) = G_CONSTANT i1 false519 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[C10]](s1)520 ; GFX10-NEXT: G_BR %bb.2521 ; GFX10-NEXT: {{ $}}522 ; GFX10-NEXT: bb.5:523 ; GFX10-NEXT: successors: %bb.6(0x80000000)524 ; GFX10-NEXT: {{ $}}525 ; GFX10-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)526 ; GFX10-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 2527 ; GFX10-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[C11]]528 ; GFX10-NEXT: {{ $}}529 ; GFX10-NEXT: bb.6:530 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s32) = G_PHI [[PHI1]](s32), %bb.2, [[OR2]](s32), %bb.5531 ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[LOAD]](<8 x s32>)532 ; GFX10-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY1]]533 ; GFX10-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 2534 ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ADD3]], [[C12]](s32)535 ; GFX10-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0536 ; GFX10-NEXT: G_AMDGPU_BUFFER_STORE [[PHI5]](s32), [[UV3]](<4 x s32>), [[C13]](s32), [[SHL1]], [[C13]], 0, 0, 0 :: (dereferenceable store (s32), align 1, addrspace 8)537 ; GFX10-NEXT: S_ENDPGM 0538 bb.0:539 successors: %bb.1(0x40000000), %bb.2(0x40000000)540 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2541 542 %0:_(s32) = COPY $sgpr0543 %1:_(s32) = COPY $sgpr1544 %2:_(s32) = COPY $vgpr0545 %3:_(s32) = G_IMPLICIT_DEF546 %4:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.getpc)547 %5:_(s64) = G_CONSTANT i64 -4294967296548 %6:_(s64) = G_AND %4, %5549 %7:_(s64) = G_ZEXT %0(s32)550 %8:_(s64) = G_OR %6, %7551 %9:_(p4) = G_INTTOPTR %8(s64)552 %10:_(<8 x s32>) = G_LOAD %9(p4) :: (invariant load (<8 x s32>), align 16, addrspace 4)553 %11:_(s32) = G_CONSTANT i32 0554 %12:_(s32) = G_CONSTANT i32 1555 %13:_(s32) = G_CONSTANT i32 2556 %14:_(<4 x s32>), %15:_(<4 x s32>) = G_UNMERGE_VALUES %10(<8 x s32>)557 %16:_(s32) = G_CONSTANT i32 -1558 %17:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %16(s32), %11(s32)559 %18:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.hi), %16(s32), %17(s32)560 %19:_(s32) = G_FREEZE %18561 %20:_(s32) = G_SHL %19, %13(s32)562 %21:_(s32) = G_AMDGPU_BUFFER_LOAD %14(<4 x s32>), %11(s32), %20, %11, 0, 0, 0 :: (dereferenceable load (s32), align 1, addrspace 8)563 %22:_(s1) = G_ICMP intpred(eq), %21(s32), %11564 %23:_(s32) = G_AND %19, %12565 %24:_(s1) = G_TRUNC %23(s32)566 %25:_(s1) = G_CONSTANT i1 true567 %26:_(s1) = G_XOR %24, %25568 G_BRCOND %26(s1), %bb.2569 G_BR %bb.1570 571 bb.1:572 successors: %bb.3(0x80000000)573 574 %27:_(s32) = G_CONSTANT i32 0575 G_BR %bb.3576 577 bb.2:578 successors: %bb.5(0x40000000), %bb.6(0x40000000)579 580 %28:_(s32) = G_PHI %29(s32), %bb.4, %3(s32), %bb.0581 %30:_(s1) = G_PHI %31(s1), %bb.4, %25(s1), %bb.0582 G_BRCOND %30(s1), %bb.5583 G_BR %bb.6584 585 bb.3:586 successors: %bb.4(0x04000000), %bb.3(0x7c000000)587 588 %32:_(s32) = G_PHI %33(s32), %bb.3, %27(s32), %bb.1589 %34:_(s32) = G_PHI %35(s32), %bb.3, %19(s32), %bb.1590 %36:_(s32) = G_PHI %37(s32), %bb.3, %27(s32), %bb.1591 %38:_(s32) = G_CONSTANT i32 0592 %39:_(s32) = G_AMDGPU_BUFFER_LOAD %14(<4 x s32>), %38(s32), %32, %38, 0, 0, 0 :: (dereferenceable load (s32), align 1, addrspace 8)593 %37:_(s32) = G_ADD %39, %36594 %40:_(s32) = G_CONSTANT i32 -1595 %35:_(s32) = G_ADD %34, %40596 %41:_(s32) = G_CONSTANT i32 4597 %33:_(s32) = G_ADD %32, %41598 %42:_(s1) = G_ICMP intpred(ne), %35(s32), %38599 G_BRCOND %42(s1), %bb.3600 G_BR %bb.4601 602 bb.4:603 successors: %bb.2(0x80000000)604 605 %43:_(s1) = G_ICMP intpred(eq), %37(s32), %21606 %44:_(s1) = G_OR %22, %43607 %29:_(s32) = G_ZEXT %44(s1)608 %31:_(s1) = G_CONSTANT i1 false609 G_BR %bb.2610 611 bb.5:612 successors: %bb.6(0x80000000)613 614 %45:_(s32) = G_ZEXT %22(s1)615 %46:_(s32) = G_CONSTANT i32 2616 %47:_(s32) = G_OR %45, %46617 618 bb.6:619 %48:_(s32) = G_PHI %28(s32), %bb.2, %47(s32), %bb.5620 %49:_(<4 x s32>), %50:_(<4 x s32>) = G_UNMERGE_VALUES %10(<8 x s32>)621 %51:_(s32) = G_ADD %2, %1622 %52:_(s32) = G_CONSTANT i32 2623 %53:_(s32) = G_SHL %51, %52(s32)624 %54:_(s32) = G_CONSTANT i32 0625 G_AMDGPU_BUFFER_STORE %48(s32), %50(<4 x s32>), %54(s32), %53, %54, 0, 0, 0 :: (dereferenceable store (s32), align 1, addrspace 8)626 S_ENDPGM 0627...628