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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s3 4---5name: divergent_i1_phi_used_outside_loop6legalized: true7tracksRegLiveness: true8body: |9 ; GFX10-LABEL: name: divergent_i1_phi_used_outside_loop10 ; GFX10: bb.0:11 ; GFX10-NEXT: successors: %bb.1(0x80000000)12 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr313 ; GFX10-NEXT: {{ $}}14 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr015 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr116 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr217 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr318 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)19 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+0020 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY1]](s32), [[C]]21 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 022 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF23 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[FCMP]](s1)24 ; GFX10-NEXT: {{ $}}25 ; GFX10-NEXT: bb.1:26 ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)27 ; GFX10-NEXT: {{ $}}28 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY4]](s1), %bb.0, %29(s1), %bb.129 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %21(s1), %bb.130 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %9(s32), %bb.1, [[C1]](s32), %bb.031 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %11(s32), %bb.132 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)33 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[COPY5]](s1)34 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)35 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true36 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[COPY5]], [[C2]]37 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI3]](s32)38 ; GFX10-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]39 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 140 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI3]], [[C3]]41 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP1]](s1), [[PHI2]](s32)42 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY7]](s1), $exec_lo, implicit-def $scc43 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY6]](s1), implicit-def $scc44 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc45 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)46 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec47 ; GFX10-NEXT: G_BR %bb.248 ; GFX10-NEXT: {{ $}}49 ; GFX10-NEXT: bb.2:50 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)51 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+0052 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+0053 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[S_OR_B32_]](s1), [[C5]], [[C4]]54 ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32))55 ; GFX10-NEXT: SI_RETURN56 bb.0:57 successors: %bb.1(0x80000000)58 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr359 60 %0:_(s32) = COPY $vgpr061 %1:_(s32) = COPY $vgpr162 %2:_(s32) = COPY $vgpr263 %3:_(s32) = COPY $vgpr364 %4:_(p0) = G_MERGE_VALUES %2(s32), %3(s32)65 %5:_(s32) = G_FCONSTANT float 1.000000e+0066 %6:_(s1) = G_FCMP floatpred(ogt), %1(s32), %567 %7:_(s32) = G_CONSTANT i32 068 69 bb.1:70 successors: %bb.2(0x04000000), %bb.1(0x7c000000)71 72 %8:_(s32) = G_PHI %9(s32), %bb.1, %7(s32), %bb.073 %10:_(s32) = G_PHI %7(s32), %bb.0, %11(s32), %bb.174 %12:_(s1) = G_PHI %6(s1), %bb.0, %13(s1), %bb.175 %14:_(s1) = G_CONSTANT i1 true76 %13:_(s1) = G_XOR %12, %1477 %15:_(s32) = G_UITOFP %10(s32)78 %16:_(s1) = G_FCMP floatpred(ogt), %15(s32), %079 %17:_(s32) = G_CONSTANT i32 180 %11:_(s32) = G_ADD %10, %1781 %9:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %16(s1), %8(s32)82 SI_LOOP %9(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec83 G_BR %bb.284 85 bb.2:86 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %9(s32)87 %18:_(s32) = G_FCONSTANT float 0.000000e+0088 %19:_(s32) = G_FCONSTANT float 1.000000e+0089 %20:_(s32) = G_SELECT %12(s1), %19, %1890 G_STORE %20(s32), %4(p0) :: (store (s32))91 SI_RETURN92...93 94---95name: divergent_i1_phi_used_outside_loop_larger_loop_body96legalized: true97tracksRegLiveness: true98body: |99 ; GFX10-LABEL: name: divergent_i1_phi_used_outside_loop_larger_loop_body100 ; GFX10: bb.0:101 ; GFX10-NEXT: successors: %bb.1(0x80000000)102 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4103 ; GFX10-NEXT: {{ $}}104 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr1105 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2106 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)107 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr3108 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr4109 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)110 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true111 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[C]](s1)112 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1113 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF114 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[DEF]](s1)115 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY5]](s1), $exec_lo, implicit-def $scc116 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY4]](s1), implicit-def $scc117 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc118 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF119 ; GFX10-NEXT: {{ $}}120 ; GFX10-NEXT: bb.1:121 ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)122 ; GFX10-NEXT: {{ $}}123 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %40(s1), %bb.3124 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[S_OR_B32_]](s1), %bb.0, %26(s1), %bb.3125 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %9(s32), %bb.3126 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(p1) = G_PHI [[MV]](p1), %bb.0, %11(p1), %bb.3127 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)128 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI1]](s1)129 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[COPY7]](s1)130 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI1]](s1)131 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc132 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY8]](s1), implicit-def $scc133 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc134 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_1]](s1)135 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY7]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec136 ; GFX10-NEXT: G_BR %bb.2137 ; GFX10-NEXT: {{ $}}138 ; GFX10-NEXT: bb.2:139 ; GFX10-NEXT: successors: %bb.3(0x80000000)140 ; GFX10-NEXT: {{ $}}141 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PHI3]](p1) :: (load (s32), addrspace 1)142 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0143 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C2]]144 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)145 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc146 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc147 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc148 ; GFX10-NEXT: {{ $}}149 ; GFX10-NEXT: bb.3:150 ; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000)151 ; GFX10-NEXT: {{ $}}152 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_1]](s1), %bb.1, [[S_OR_B32_2]](s1), %bb.2153 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[PHI4]](s1)154 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[COPY12]](s1)155 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)156 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4157 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[PHI3]], [[C3]](s64)158 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1159 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[PHI2]], [[C4]]160 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 10161 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[ADD]](s32), [[C5]]162 ; GFX10-NEXT: [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY9]](s1), $exec_lo, implicit-def $scc163 ; GFX10-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY13]](s1), implicit-def $scc164 ; GFX10-NEXT: [[S_OR_B32_3:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc165 ; GFX10-NEXT: G_BRCOND [[ICMP1]](s1), %bb.1166 ; GFX10-NEXT: G_BR %bb.4167 ; GFX10-NEXT: {{ $}}168 ; GFX10-NEXT: bb.4:169 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00170 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00171 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[COPY7]](s1), [[C7]], [[C6]]172 ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV1]](p0) :: (store (s32))173 ; GFX10-NEXT: SI_RETURN174 bb.0:175 successors: %bb.1(0x80000000)176 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4177 178 %0:_(s32) = COPY $vgpr1179 %1:_(s32) = COPY $vgpr2180 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)181 %3:_(s32) = COPY $vgpr3182 %4:_(s32) = COPY $vgpr4183 %5:_(p0) = G_MERGE_VALUES %3(s32), %4(s32)184 %6:_(s1) = G_CONSTANT i1 true185 %7:_(s32) = G_CONSTANT i32 -1186 187 bb.1:188 successors: %bb.2(0x40000000), %bb.3(0x40000000)189 190 %8:_(s32) = G_PHI %7(s32), %bb.0, %9(s32), %bb.3191 %10:_(p1) = G_PHI %2(p1), %bb.0, %11(p1), %bb.3192 %12:sreg_32_xm0_xexec(s1) = G_PHI %6(s1), %bb.0, %13(s1), %bb.3193 %14:sreg_32_xm0_xexec(s32) = SI_IF %12(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec194 G_BR %bb.2195 196 bb.2:197 successors: %bb.3(0x80000000)198 199 %15:_(s32) = G_LOAD %10(p1) :: (load (s32), addrspace 1)200 %16:_(s32) = G_CONSTANT i32 0201 %17:_(s1) = G_ICMP intpred(eq), %15(s32), %16202 203 bb.3:204 successors: %bb.4(0x04000000), %bb.1(0x7c000000)205 206 %13:_(s1) = G_PHI %17(s1), %bb.2, %12(s1), %bb.1207 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %14(s32)208 %18:_(s64) = G_CONSTANT i64 4209 %11:_(p1) = G_PTR_ADD %10, %18(s64)210 %19:_(s32) = G_CONSTANT i32 1211 %9:_(s32) = nsw G_ADD %8, %19212 %20:_(s32) = G_CONSTANT i32 10213 %21:_(s1) = G_ICMP intpred(sge), %9(s32), %20214 G_BRCOND %21(s1), %bb.1215 G_BR %bb.4216 217 bb.4:218 %22:_(s32) = G_FCONSTANT float 0.000000e+00219 %23:_(s32) = G_FCONSTANT float 1.000000e+00220 %24:_(s32) = G_SELECT %12(s1), %23, %22221 G_STORE %24(s32), %5(p0) :: (store (s32))222 SI_RETURN223...224 225---226name: divergent_i1_xor_used_outside_loop227legalized: true228tracksRegLiveness: true229body: |230 ; GFX10-LABEL: name: divergent_i1_xor_used_outside_loop231 ; GFX10: bb.0:232 ; GFX10-NEXT: successors: %bb.1(0x80000000)233 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3234 ; GFX10-NEXT: {{ $}}235 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0236 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1237 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2238 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3239 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)240 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00241 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY1]](s32), [[C]]242 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0243 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF244 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[FCMP]](s1)245 ; GFX10-NEXT: {{ $}}246 ; GFX10-NEXT: bb.1:247 ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)248 ; GFX10-NEXT: {{ $}}249 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY4]](s1), %bb.0, %29(s1), %bb.1250 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %21(s1), %bb.1251 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %9(s32), %bb.1, [[C1]](s32), %bb.0252 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %11(s32), %bb.1253 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)254 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)255 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true256 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[COPY5]], [[C2]]257 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)258 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI3]](s32)259 ; GFX10-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]260 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1261 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI3]], [[C3]]262 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP1]](s1), [[PHI2]](s32)263 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc264 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY7]](s1), implicit-def $scc265 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc266 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)267 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec268 ; GFX10-NEXT: G_BR %bb.2269 ; GFX10-NEXT: {{ $}}270 ; GFX10-NEXT: bb.2:271 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)272 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00273 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00274 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[S_OR_B32_]](s1), [[C5]], [[C4]]275 ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32))276 ; GFX10-NEXT: SI_RETURN277 bb.0:278 successors: %bb.1(0x80000000)279 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3280 281 %0:_(s32) = COPY $vgpr0282 %1:_(s32) = COPY $vgpr1283 %2:_(s32) = COPY $vgpr2284 %3:_(s32) = COPY $vgpr3285 %4:_(p0) = G_MERGE_VALUES %2(s32), %3(s32)286 %5:_(s32) = G_FCONSTANT float 1.000000e+00287 %6:_(s1) = G_FCMP floatpred(ogt), %1(s32), %5288 %7:_(s32) = G_CONSTANT i32 0289 290 bb.1:291 successors: %bb.2(0x04000000), %bb.1(0x7c000000)292 293 %8:_(s32) = G_PHI %9(s32), %bb.1, %7(s32), %bb.0294 %10:_(s32) = G_PHI %7(s32), %bb.0, %11(s32), %bb.1295 %12:_(s1) = G_PHI %6(s1), %bb.0, %13(s1), %bb.1296 %14:_(s1) = G_CONSTANT i1 true297 %13:_(s1) = G_XOR %12, %14298 %15:_(s32) = G_UITOFP %10(s32)299 %16:_(s1) = G_FCMP floatpred(ogt), %15(s32), %0300 %17:_(s32) = G_CONSTANT i32 1301 %11:_(s32) = G_ADD %10, %17302 %9:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %16(s1), %8(s32)303 SI_LOOP %9(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec304 G_BR %bb.2305 306 bb.2:307 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %9(s32)308 %18:_(s32) = G_FCONSTANT float 0.000000e+00309 %19:_(s32) = G_FCONSTANT float 1.000000e+00310 %20:_(s32) = G_SELECT %13(s1), %19, %18311 G_STORE %20(s32), %4(p0) :: (store (s32))312 SI_RETURN313...314 315 316---317name: divergent_i1_xor_used_outside_loop_twice318legalized: true319tracksRegLiveness: true320body: |321 ; GFX10-LABEL: name: divergent_i1_xor_used_outside_loop_twice322 ; GFX10: bb.0:323 ; GFX10-NEXT: successors: %bb.1(0x80000000)324 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5325 ; GFX10-NEXT: {{ $}}326 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0327 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1328 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2329 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3330 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)331 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4332 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5333 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)334 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00335 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY1]](s32), [[C]]336 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0337 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF338 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[FCMP]](s1)339 ; GFX10-NEXT: {{ $}}340 ; GFX10-NEXT: bb.1:341 ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)342 ; GFX10-NEXT: {{ $}}343 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY6]](s1), %bb.0, %35(s1), %bb.1344 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %27(s1), %bb.1345 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.1, [[C1]](s32), %bb.0346 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %14(s32), %bb.1347 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)348 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)349 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true350 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[COPY7]], [[C2]]351 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)352 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI3]](s32)353 ; GFX10-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]354 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1355 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI3]], [[C3]]356 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP1]](s1), [[PHI2]](s32)357 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc358 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc359 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc360 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)361 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec362 ; GFX10-NEXT: G_BR %bb.2363 ; GFX10-NEXT: {{ $}}364 ; GFX10-NEXT: bb.2:365 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)366 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00367 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00368 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[S_OR_B32_]](s1), [[C5]], [[C4]]369 ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32))370 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00371 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00372 ; GFX10-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[S_OR_B32_]](s1), [[C7]], [[C6]]373 ; GFX10-NEXT: G_STORE [[SELECT1]](s32), [[MV1]](p0) :: (store (s32))374 ; GFX10-NEXT: SI_RETURN375 bb.0:376 successors: %bb.1(0x80000000)377 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5378 379 %0:_(s32) = COPY $vgpr0380 %1:_(s32) = COPY $vgpr1381 %2:_(s32) = COPY $vgpr2382 %3:_(s32) = COPY $vgpr3383 %4:_(p0) = G_MERGE_VALUES %2(s32), %3(s32)384 %5:_(s32) = COPY $vgpr4385 %6:_(s32) = COPY $vgpr5386 %7:_(p0) = G_MERGE_VALUES %5(s32), %6(s32)387 %8:_(s32) = G_FCONSTANT float 1.000000e+00388 %9:_(s1) = G_FCMP floatpred(ogt), %1(s32), %8389 %10:_(s32) = G_CONSTANT i32 0390 391 bb.1:392 successors: %bb.2(0x04000000), %bb.1(0x7c000000)393 394 %11:_(s32) = G_PHI %12(s32), %bb.1, %10(s32), %bb.0395 %13:_(s32) = G_PHI %10(s32), %bb.0, %14(s32), %bb.1396 %15:_(s1) = G_PHI %9(s1), %bb.0, %16(s1), %bb.1397 %17:_(s1) = G_CONSTANT i1 true398 %16:_(s1) = G_XOR %15, %17399 %18:_(s32) = G_UITOFP %13(s32)400 %19:_(s1) = G_FCMP floatpred(ogt), %18(s32), %0401 %20:_(s32) = G_CONSTANT i32 1402 %14:_(s32) = G_ADD %13, %20403 %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %19(s1), %11(s32)404 SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec405 G_BR %bb.2406 407 bb.2:408 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %12(s32)409 %21:_(s32) = G_FCONSTANT float 0.000000e+00410 %22:_(s32) = G_FCONSTANT float 1.000000e+00411 %23:_(s32) = G_SELECT %16(s1), %22, %21412 G_STORE %23(s32), %4(p0) :: (store (s32))413 %24:_(s32) = G_FCONSTANT float -1.000000e+00414 %25:_(s32) = G_FCONSTANT float 2.000000e+00415 %26:_(s32) = G_SELECT %16(s1), %25, %24416 G_STORE %26(s32), %7(p0) :: (store (s32))417 SI_RETURN418...419 420---421name: divergent_i1_xor_used_outside_loop_larger_loop_body422legalized: true423tracksRegLiveness: true424body: |425 ; GFX10-LABEL: name: divergent_i1_xor_used_outside_loop_larger_loop_body426 ; GFX10: bb.0:427 ; GFX10-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)428 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4429 ; GFX10-NEXT: {{ $}}430 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0431 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1432 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2433 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)434 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3435 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4436 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)437 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF438 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0439 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]440 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true441 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[C1]](s1)442 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[COPY5]](s1)443 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec444 ; GFX10-NEXT: G_BR %bb.1445 ; GFX10-NEXT: {{ $}}446 ; GFX10-NEXT: bb.1:447 ; GFX10-NEXT: successors: %bb.3(0x80000000)448 ; GFX10-NEXT: {{ $}}449 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0450 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF451 ; GFX10-NEXT: [[DEF2:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF452 ; GFX10-NEXT: [[DEF3:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF453 ; GFX10-NEXT: G_BR %bb.3454 ; GFX10-NEXT: {{ $}}455 ; GFX10-NEXT: bb.2:456 ; GFX10-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)457 ; GFX10-NEXT: {{ $}}458 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[COPY5]](s1), %bb.0, %45(s1), %bb.8459 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI]](s1)460 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)461 ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY7]](s1), %bb.6, implicit-def $exec, implicit-def $scc, implicit $exec462 ; GFX10-NEXT: G_BR %bb.5463 ; GFX10-NEXT: {{ $}}464 ; GFX10-NEXT: bb.3:465 ; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.7(0x40000000)466 ; GFX10-NEXT: {{ $}}467 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[DEF3]](s1), %bb.1, %67(s1), %bb.7468 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:sreg_32(s1) = PHI [[DEF2]](s1), %bb.1, %54(s1), %bb.7469 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.1, %37(s1), %bb.7470 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[C2]](s32), %bb.1, %17(s32), %bb.7471 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s32) = G_PHI %19(s32), %bb.7, [[C2]](s32), %bb.1472 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)473 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[PHI2]](s1)474 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)475 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI5]](s32)476 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2477 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C3]](s32)478 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL]](s64)479 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)480 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0481 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C4]]482 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 true483 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[C5]](s1)484 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[C5]](s1)485 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY9]](s1), $exec_lo, implicit-def $scc486 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY12]](s1), implicit-def $scc487 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc488 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)489 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc490 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc491 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc492 ; GFX10-NEXT: [[COPY14:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_1]](s1)493 ; GFX10-NEXT: [[SI_IF2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec494 ; GFX10-NEXT: G_BR %bb.4495 ; GFX10-NEXT: {{ $}}496 ; GFX10-NEXT: bb.4:497 ; GFX10-NEXT: successors: %bb.7(0x80000000)498 ; GFX10-NEXT: {{ $}}499 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1500 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI5]], [[C6]]501 ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[PHI5]](s32), [[COPY]]502 ; GFX10-NEXT: [[COPY15:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)503 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s1) = G_CONSTANT i1 false504 ; GFX10-NEXT: [[COPY16:%[0-9]+]]:sreg_32(s1) = COPY [[C7]](s1)505 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY13]](s1), $exec_lo, implicit-def $scc506 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY16]](s1), implicit-def $scc507 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc508 ; GFX10-NEXT: [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY14]](s1), $exec_lo, implicit-def $scc509 ; GFX10-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY15]](s1), implicit-def $scc510 ; GFX10-NEXT: [[S_OR_B32_3:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc511 ; GFX10-NEXT: G_BR %bb.7512 ; GFX10-NEXT: {{ $}}513 ; GFX10-NEXT: bb.5:514 ; GFX10-NEXT: successors: %bb.6(0x80000000)515 ; GFX10-NEXT: {{ $}}516 ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 5517 ; GFX10-NEXT: G_STORE [[C8]](s32), [[MV1]](p0) :: (store (s32))518 ; GFX10-NEXT: {{ $}}519 ; GFX10-NEXT: bb.6:520 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32)521 ; GFX10-NEXT: SI_RETURN522 ; GFX10-NEXT: {{ $}}523 ; GFX10-NEXT: bb.7:524 ; GFX10-NEXT: successors: %bb.8(0x04000000), %bb.3(0x7c000000)525 ; GFX10-NEXT: {{ $}}526 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_1]](s1), %bb.3, [[S_OR_B32_3]](s1), %bb.4527 ; GFX10-NEXT: [[PHI7:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.3, [[S_OR_B32_2]](s1), %bb.4528 ; GFX10-NEXT: [[PHI8:%[0-9]+]]:_(s32) = G_PHI [[ADD]](s32), %bb.4, [[DEF]](s32), %bb.3529 ; GFX10-NEXT: [[COPY17:%[0-9]+]]:sreg_32(s1) = COPY [[PHI6]](s1)530 ; GFX10-NEXT: [[COPY18:%[0-9]+]]:sreg_32(s1) = COPY [[PHI7]](s1)531 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF2]](s32)532 ; GFX10-NEXT: [[C9:%[0-9]+]]:_(s1) = G_CONSTANT i1 true533 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[COPY18]], [[C9]]534 ; GFX10-NEXT: [[COPY19:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)535 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY17]](s1), [[PHI4]](s32)536 ; GFX10-NEXT: [[S_ANDN2_B32_4:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc537 ; GFX10-NEXT: [[S_AND_B32_4:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY19]](s1), implicit-def $scc538 ; GFX10-NEXT: [[S_OR_B32_4:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_4]](s1), [[S_AND_B32_4]](s1), implicit-def $scc539 ; GFX10-NEXT: [[COPY20:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[S_OR_B32_4]](s1)540 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec541 ; GFX10-NEXT: G_BR %bb.8542 ; GFX10-NEXT: {{ $}}543 ; GFX10-NEXT: bb.8:544 ; GFX10-NEXT: successors: %bb.2(0x80000000)545 ; GFX10-NEXT: {{ $}}546 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)547 ; GFX10-NEXT: [[S_ANDN2_B32_5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc548 ; GFX10-NEXT: [[S_AND_B32_5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY20]](s1), implicit-def $scc549 ; GFX10-NEXT: [[S_OR_B32_5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_5]](s1), [[S_AND_B32_5]](s1), implicit-def $scc550 ; GFX10-NEXT: G_BR %bb.2551 bb.0:552 successors: %bb.1(0x40000000), %bb.2(0x40000000)553 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4554 555 %0:_(s32) = COPY $vgpr0556 %1:_(s32) = COPY $vgpr1557 %2:_(s32) = COPY $vgpr2558 %3:_(p1) = G_MERGE_VALUES %1(s32), %2(s32)559 %4:_(s32) = COPY $vgpr3560 %5:_(s32) = COPY $vgpr4561 %6:_(p0) = G_MERGE_VALUES %4(s32), %5(s32)562 %7:_(s32) = G_IMPLICIT_DEF563 %8:_(s32) = G_CONSTANT i32 0564 %9:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), %0(s32), %8565 %10:_(s1) = G_CONSTANT i1 true566 %11:sreg_32_xm0_xexec(s32) = SI_IF %9(s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec567 G_BR %bb.1568 569 bb.1:570 successors: %bb.3(0x80000000)571 572 %12:_(s32) = G_CONSTANT i32 0573 G_BR %bb.3574 575 bb.2:576 successors: %bb.5(0x40000000), %bb.6(0x40000000)577 578 %13:sreg_32_xm0_xexec(s1) = G_PHI %14(s1), %bb.8, %10(s1), %bb.0579 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %11(s32)580 %15:sreg_32_xm0_xexec(s32) = SI_IF %13(s1), %bb.6, implicit-def $exec, implicit-def $scc, implicit $exec581 G_BR %bb.5582 583 bb.3:584 successors: %bb.4(0x40000000), %bb.7(0x40000000)585 586 %16:_(s32) = G_PHI %12(s32), %bb.1, %17(s32), %bb.7587 %18:_(s32) = G_PHI %19(s32), %bb.7, %12(s32), %bb.1588 %20:_(s64) = G_SEXT %18(s32)589 %21:_(s32) = G_CONSTANT i32 2590 %22:_(s64) = G_SHL %20, %21(s32)591 %23:_(p1) = G_PTR_ADD %3, %22(s64)592 %24:_(s32) = G_LOAD %23(p1) :: (load (s32), addrspace 1)593 %25:_(s32) = G_CONSTANT i32 0594 %26:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %24(s32), %25595 %27:_(s1) = G_CONSTANT i1 true596 %28:sreg_32_xm0_xexec(s32) = SI_IF %26(s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec597 G_BR %bb.4598 599 bb.4:600 successors: %bb.7(0x80000000)601 602 %29:_(s32) = G_CONSTANT i32 1603 %30:_(s32) = G_ADD %18, %29604 %31:_(s1) = G_ICMP intpred(slt), %18(s32), %0605 %32:_(s1) = G_CONSTANT i1 false606 G_BR %bb.7607 608 bb.5:609 successors: %bb.6(0x80000000)610 611 %33:_(s32) = G_CONSTANT i32 5612 G_STORE %33(s32), %6(p0) :: (store (s32))613 614 bb.6:615 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)616 SI_RETURN617 618 bb.7:619 successors: %bb.8(0x04000000), %bb.3(0x7c000000)620 621 %19:_(s32) = G_PHI %30(s32), %bb.4, %7(s32), %bb.3622 %34:_(s1) = G_PHI %32(s1), %bb.4, %27(s1), %bb.3623 %35:_(s1) = G_PHI %31(s1), %bb.4, %27(s1), %bb.3624 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %28(s32)625 %36:_(s1) = G_CONSTANT i1 true626 %14:_(s1) = G_XOR %34, %36627 %17:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %35(s1), %16(s32)628 SI_LOOP %17(s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec629 G_BR %bb.8630 631 bb.8:632 successors: %bb.2(0x80000000)633 634 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %17(s32)635 G_BR %bb.2636...637 638---639name: divergent_i1_icmp_used_outside_loop640legalized: true641tracksRegLiveness: true642body: |643 ; GFX10-LABEL: name: divergent_i1_icmp_used_outside_loop644 ; GFX10: bb.0:645 ; GFX10-NEXT: successors: %bb.1(0x80000000)646 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9647 ; GFX10-NEXT: {{ $}}648 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0649 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1650 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2651 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3652 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)653 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr6654 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr7655 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)656 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF657 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0658 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF659 ; GFX10-NEXT: {{ $}}660 ; GFX10-NEXT: bb.1:661 ; GFX10-NEXT: successors: %bb.2(0x80000000)662 ; GFX10-NEXT: {{ $}}663 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %29(s1), %bb.6664 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %11(s32), %bb.6, [[C]](s32), %bb.0665 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %13(s32), %bb.6666 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)667 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[PHI2]](s32), implicit $exec_lo668 ; GFX10-NEXT: {{ $}}669 ; GFX10-NEXT: bb.2:670 ; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)671 ; GFX10-NEXT: {{ $}}672 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[PHI2]]673 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)674 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc675 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY8]](s1), implicit-def $scc676 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc677 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec678 ; GFX10-NEXT: G_BR %bb.3679 ; GFX10-NEXT: {{ $}}680 ; GFX10-NEXT: bb.3:681 ; GFX10-NEXT: successors: %bb.4(0x80000000)682 ; GFX10-NEXT: {{ $}}683 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI2]](s32)684 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2685 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C1]](s32)686 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL]](s64)687 ; GFX10-NEXT: G_STORE [[PHI2]](s32), [[PTR_ADD]](p1) :: (store (s32), addrspace 1)688 ; GFX10-NEXT: {{ $}}689 ; GFX10-NEXT: bb.4:690 ; GFX10-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)691 ; GFX10-NEXT: {{ $}}692 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)693 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[PHI2]]694 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true695 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[C2]](s1)696 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[COPY9]](s1)697 ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.6, implicit-def $exec, implicit-def $scc, implicit $exec698 ; GFX10-NEXT: G_BR %bb.5699 ; GFX10-NEXT: {{ $}}700 ; GFX10-NEXT: bb.5:701 ; GFX10-NEXT: successors: %bb.6(0x80000000)702 ; GFX10-NEXT: {{ $}}703 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1704 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C3]]705 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 false706 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[C4]](s1)707 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc708 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc709 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc710 ; GFX10-NEXT: {{ $}}711 ; GFX10-NEXT: bb.6:712 ; GFX10-NEXT: successors: %bb.7(0x04000000), %bb.1(0x7c000000)713 ; GFX10-NEXT: {{ $}}714 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[COPY9]](s1), %bb.4, [[S_OR_B32_1]](s1), %bb.5715 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[ADD]](s32), %bb.5, [[DEF]](s32), %bb.4716 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)717 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32)718 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY12]](s1), [[PHI1]](s32)719 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec720 ; GFX10-NEXT: G_BR %bb.7721 ; GFX10-NEXT: {{ $}}722 ; GFX10-NEXT: bb.7:723 ; GFX10-NEXT: successors: %bb.8(0x40000000), %bb.9(0x40000000)724 ; GFX10-NEXT: {{ $}}725 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)726 ; GFX10-NEXT: [[SI_IF2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[S_OR_B32_]](s1), %bb.9, implicit-def $exec, implicit-def $scc, implicit $exec727 ; GFX10-NEXT: G_BR %bb.8728 ; GFX10-NEXT: {{ $}}729 ; GFX10-NEXT: bb.8:730 ; GFX10-NEXT: successors: %bb.9(0x80000000)731 ; GFX10-NEXT: {{ $}}732 ; GFX10-NEXT: G_STORE [[COPY7]](s32), [[MV1]](p1) :: (store (s32), addrspace 1)733 ; GFX10-NEXT: {{ $}}734 ; GFX10-NEXT: bb.9:735 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF2]](s32)736 ; GFX10-NEXT: SI_RETURN737 bb.0:738 successors: %bb.1(0x80000000)739 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9740 741 %0:_(s32) = COPY $vgpr0742 %1:_(s32) = COPY $vgpr1743 %2:_(s32) = COPY $vgpr2744 %3:_(s32) = COPY $vgpr3745 %4:_(p1) = G_MERGE_VALUES %2(s32), %3(s32)746 %5:_(s32) = COPY $vgpr6747 %6:_(s32) = COPY $vgpr7748 %7:_(p1) = G_MERGE_VALUES %5(s32), %6(s32)749 %8:_(s32) = G_IMPLICIT_DEF750 %9:_(s32) = G_CONSTANT i32 0751 752 bb.1:753 successors: %bb.2(0x80000000)754 755 %10:_(s32) = G_PHI %11(s32), %bb.6, %9(s32), %bb.0756 %12:_(s32) = G_PHI %9(s32), %bb.0, %13(s32), %bb.6757 758 bb.2:759 successors: %bb.3(0x40000000), %bb.4(0x40000000)760 761 %14:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), %0(s32), %12762 %15:sreg_32_xm0_xexec(s32) = SI_IF %14(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec763 G_BR %bb.3764 765 bb.3:766 successors: %bb.4(0x80000000)767 768 %16:_(s64) = G_SEXT %12(s32)769 %17:_(s32) = G_CONSTANT i32 2770 %18:_(s64) = G_SHL %16, %17(s32)771 %19:_(p1) = G_PTR_ADD %4, %18(s64)772 G_STORE %12(s32), %19(p1) :: (store (s32), addrspace 1)773 774 bb.4:775 successors: %bb.5(0x40000000), %bb.6(0x40000000)776 777 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)778 %20:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %1(s32), %12779 %21:_(s1) = G_CONSTANT i1 true780 %22:sreg_32_xm0_xexec(s32) = SI_IF %20(s1), %bb.6, implicit-def $exec, implicit-def $scc, implicit $exec781 G_BR %bb.5782 783 bb.5:784 successors: %bb.6(0x80000000)785 786 %23:_(s32) = G_CONSTANT i32 1787 %24:_(s32) = G_ADD %12, %23788 %25:_(s1) = G_CONSTANT i1 false789 790 bb.6:791 successors: %bb.7(0x04000000), %bb.1(0x7c000000)792 793 %13:_(s32) = G_PHI %24(s32), %bb.5, %8(s32), %bb.4794 %26:_(s1) = G_PHI %25(s1), %bb.5, %21(s1), %bb.4795 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %22(s32)796 %11:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %26(s1), %10(s32)797 SI_LOOP %11(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec798 G_BR %bb.7799 800 bb.7:801 successors: %bb.8(0x40000000), %bb.9(0x40000000)802 803 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %11(s32)804 %27:sreg_32_xm0_xexec(s32) = SI_IF %14(s1), %bb.9, implicit-def $exec, implicit-def $scc, implicit $exec805 G_BR %bb.8806 807 bb.8:808 successors: %bb.9(0x80000000)809 810 G_STORE %12(s32), %7(p1) :: (store (s32), addrspace 1)811 812 bb.9:813 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %27(s32)814 SI_RETURN815...816 817---818name: divergent_i1_freeze_used_outside_loop819legalized: true820tracksRegLiveness: true821body: |822 ; GFX10-LABEL: name: divergent_i1_freeze_used_outside_loop823 ; GFX10: bb.0:824 ; GFX10-NEXT: successors: %bb.1(0x80000000)825 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4826 ; GFX10-NEXT: {{ $}}827 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0828 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1829 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2830 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)831 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3832 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4833 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)834 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true835 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0836 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF837 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[C]](s1)838 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF839 ; GFX10-NEXT: {{ $}}840 ; GFX10-NEXT: bb.1:841 ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)842 ; GFX10-NEXT: {{ $}}843 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %48(s1), %bb.3844 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[COPY5]](s1), %bb.0, %38(s1), %bb.3845 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %29(s1), %bb.3846 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI %10(s32), %bb.3, [[C1]](s32), %bb.0847 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %12(s32), %bb.3848 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)849 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI1]](s1)850 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[COPY7]](s1)851 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[PHI2]](s1)852 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc853 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY8]](s1), implicit-def $scc854 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc855 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)856 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY7]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec857 ; GFX10-NEXT: G_BR %bb.2858 ; GFX10-NEXT: {{ $}}859 ; GFX10-NEXT: bb.2:860 ; GFX10-NEXT: successors: %bb.3(0x80000000)861 ; GFX10-NEXT: {{ $}}862 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI4]](s32)863 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2864 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)865 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL]](s64)866 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)867 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0868 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C3]]869 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)870 ; GFX10-NEXT: [[DEF2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF871 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc872 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc873 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc874 ; GFX10-NEXT: {{ $}}875 ; GFX10-NEXT: bb.3:876 ; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000)877 ; GFX10-NEXT: {{ $}}878 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, [[S_OR_B32_1]](s1), %bb.2879 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[PHI1]](s1), %bb.1, [[DEF2]](s1), %bb.2880 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[PHI5]](s1)881 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI6]](s1)882 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)883 ; GFX10-NEXT: [[FREEZE:%[0-9]+]]:_(s1) = G_FREEZE [[COPY12]]884 ; GFX10-NEXT: [[COPY14:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[FREEZE]](s1)885 ; GFX10-NEXT: [[COPY15:%[0-9]+]]:sreg_32(s1) = COPY [[FREEZE]](s1)886 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1887 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI4]], [[C4]]888 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[PHI4]](s32), [[COPY]]889 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ICMP1]](s1), [[PHI3]](s32)890 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY9]](s1), $exec_lo, implicit-def $scc891 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY15]](s1), implicit-def $scc892 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc893 ; GFX10-NEXT: [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY13]](s1), $exec_lo, implicit-def $scc894 ; GFX10-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY14]](s1), implicit-def $scc895 ; GFX10-NEXT: [[S_OR_B32_3:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc896 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec897 ; GFX10-NEXT: G_BR %bb.4898 ; GFX10-NEXT: {{ $}}899 ; GFX10-NEXT: bb.4:900 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)901 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00902 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00903 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[S_OR_B32_2]](s1), [[C6]], [[C5]]904 ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV1]](p0) :: (store (s32))905 ; GFX10-NEXT: S_ENDPGM 0906 bb.0:907 successors: %bb.1(0x80000000)908 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4909 910 %0:_(s32) = COPY $vgpr0911 %1:_(s32) = COPY $vgpr1912 %2:_(s32) = COPY $vgpr2913 %3:_(p1) = G_MERGE_VALUES %1(s32), %2(s32)914 %4:_(s32) = COPY $vgpr3915 %5:_(s32) = COPY $vgpr4916 %6:_(p0) = G_MERGE_VALUES %4(s32), %5(s32)917 %7:_(s1) = G_CONSTANT i1 true918 %8:_(s32) = G_CONSTANT i32 0919 920 bb.1:921 successors: %bb.2(0x40000000), %bb.3(0x40000000)922 923 %9:_(s32) = G_PHI %10(s32), %bb.3, %8(s32), %bb.0924 %11:_(s32) = G_PHI %8(s32), %bb.0, %12(s32), %bb.3925 %13:sreg_32_xm0_xexec(s1) = G_PHI %7(s1), %bb.0, %14(s1), %bb.3926 %15:sreg_32_xm0_xexec(s32) = SI_IF %13(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec927 G_BR %bb.2928 929 bb.2:930 successors: %bb.3(0x80000000)931 932 %16:_(s64) = G_SEXT %11(s32)933 %17:_(s32) = G_CONSTANT i32 2934 %18:_(s64) = G_SHL %16, %17(s32)935 %19:_(p1) = G_PTR_ADD %3, %18(s64)936 %20:_(s32) = G_LOAD %19(p1) :: (load (s32), addrspace 1)937 %21:_(s32) = G_CONSTANT i32 0938 %22:_(s1) = G_ICMP intpred(eq), %20(s32), %21939 940 bb.3:941 successors: %bb.4(0x04000000), %bb.1(0x7c000000)942 943 %23:_(s1) = G_PHI %22(s1), %bb.2, %13(s1), %bb.1944 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)945 %14:_(s1) = G_FREEZE %23946 %24:_(s32) = G_CONSTANT i32 1947 %12:_(s32) = G_ADD %11, %24948 %25:_(s1) = G_ICMP intpred(slt), %11(s32), %0949 %10:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %25(s1), %9(s32)950 SI_LOOP %10(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec951 G_BR %bb.4952 953 bb.4:954 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %10(s32)955 %26:_(s32) = G_FCONSTANT float 0.000000e+00956 %27:_(s32) = G_FCONSTANT float 1.000000e+00957 %28:_(s32) = G_SELECT %14(s1), %27, %26958 G_STORE %28(s32), %6(p0) :: (store (s32))959 S_ENDPGM 0960...961 962---963name: loop_with_1break964legalized: true965tracksRegLiveness: true966body: |967 ; GFX10-LABEL: name: loop_with_1break968 ; GFX10: bb.0:969 ; GFX10-NEXT: successors: %bb.1(0x80000000)970 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5971 ; GFX10-NEXT: {{ $}}972 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0973 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1974 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)975 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2976 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3977 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)978 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4979 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5980 ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)981 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF982 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0983 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF984 ; GFX10-NEXT: [[DEF2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF985 ; GFX10-NEXT: [[DEF3:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF986 ; GFX10-NEXT: {{ $}}987 ; GFX10-NEXT: bb.1:988 ; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)989 ; GFX10-NEXT: {{ $}}990 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF3]](s1), %bb.0, %61(s1), %bb.5991 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[DEF2]](s1), %bb.0, %48(s1), %bb.5992 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %38(s1), %bb.5993 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.5, [[C]](s32), %bb.0994 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %14(s32), %bb.5995 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)996 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI1]](s1)997 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI2]](s1)998 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI4]](s32)999 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 21000 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C1]](s32)1001 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)1002 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)1003 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 01004 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C2]]1005 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true1006 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[C3]](s1)1007 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[C3]](s1)1008 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY7]](s1), $exec_lo, implicit-def $scc1009 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY10]](s1), implicit-def $scc1010 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc1011 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[S_OR_B32_]](s1)1012 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc1013 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc1014 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc1015 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_1]](s1)1016 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec1017 ; GFX10-NEXT: G_BR %bb.31018 ; GFX10-NEXT: {{ $}}1019 ; GFX10-NEXT: bb.2:1020 ; GFX10-NEXT: successors: %bb.4(0x80000000)1021 ; GFX10-NEXT: {{ $}}1022 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 101023 ; GFX10-NEXT: G_STORE [[C4]](s32), [[MV2]](p1) :: (store (s32), addrspace 1)1024 ; GFX10-NEXT: G_BR %bb.41025 ; GFX10-NEXT: {{ $}}1026 ; GFX10-NEXT: bb.3:1027 ; GFX10-NEXT: successors: %bb.5(0x80000000)1028 ; GFX10-NEXT: {{ $}}1029 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 21030 ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C5]](s32)1031 ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64)1032 ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)1033 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 11034 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C6]]1035 ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1)1036 ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI4]], [[C6]]1037 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1001038 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI4]](s32), [[C7]]1039 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP1]](s1)1040 ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s1) = G_CONSTANT i1 false1041 ; GFX10-NEXT: [[COPY14:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[C8]](s1)1042 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY11]](s1), $exec_lo, implicit-def $scc1043 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY14]](s1), implicit-def $scc1044 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc1045 ; GFX10-NEXT: [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY12]](s1), $exec_lo, implicit-def $scc1046 ; GFX10-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY13]](s1), implicit-def $scc1047 ; GFX10-NEXT: [[S_OR_B32_3:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc1048 ; GFX10-NEXT: G_BR %bb.51049 ; GFX10-NEXT: {{ $}}1050 ; GFX10-NEXT: bb.4:1051 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32)1052 ; GFX10-NEXT: S_ENDPGM 01053 ; GFX10-NEXT: {{ $}}1054 ; GFX10-NEXT: bb.5:1055 ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000)1056 ; GFX10-NEXT: {{ $}}1057 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_1]](s1), %bb.1, [[S_OR_B32_3]](s1), %bb.31058 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[S_OR_B32_]](s1), %bb.1, [[S_OR_B32_2]](s1), %bb.31059 ; GFX10-NEXT: [[PHI7:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.3, [[DEF]](s32), %bb.11060 ; GFX10-NEXT: [[COPY15:%[0-9]+]]:sreg_32(s1) = COPY [[PHI5]](s1)1061 ; GFX10-NEXT: [[COPY16:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI6]](s1)1062 ; GFX10-NEXT: [[COPY17:%[0-9]+]]:sreg_32(s1) = COPY [[COPY16]](s1)1063 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)1064 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY15]](s1), [[PHI3]](s32)1065 ; GFX10-NEXT: [[S_ANDN2_B32_4:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc1066 ; GFX10-NEXT: [[S_AND_B32_4:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY17]](s1), implicit-def $scc1067 ; GFX10-NEXT: [[S_OR_B32_4:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_4]](s1), [[S_AND_B32_4]](s1), implicit-def $scc1068 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec1069 ; GFX10-NEXT: G_BR %bb.61070 ; GFX10-NEXT: {{ $}}1071 ; GFX10-NEXT: bb.6:1072 ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)1073 ; GFX10-NEXT: {{ $}}1074 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)1075 ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[S_OR_B32_4]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec1076 ; GFX10-NEXT: G_BR %bb.21077 bb.0:1078 successors: %bb.1(0x80000000)1079 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr51080 1081 %0:_(s32) = COPY $vgpr01082 %1:_(s32) = COPY $vgpr11083 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)1084 %3:_(s32) = COPY $vgpr21085 %4:_(s32) = COPY $vgpr31086 %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)1087 %6:_(s32) = COPY $vgpr41088 %7:_(s32) = COPY $vgpr51089 %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)1090 %9:_(s32) = G_IMPLICIT_DEF1091 %10:_(s32) = G_CONSTANT i32 01092 1093 bb.1:1094 successors: %bb.3(0x40000000), %bb.5(0x40000000)1095 1096 %11:_(s32) = G_PHI %12(s32), %bb.5, %10(s32), %bb.01097 %13:_(s32) = G_PHI %10(s32), %bb.0, %14(s32), %bb.51098 %15:_(s64) = G_SEXT %13(s32)1099 %16:_(s32) = G_CONSTANT i32 21100 %17:_(s64) = G_SHL %15, %16(s32)1101 %18:_(p1) = G_PTR_ADD %5, %17(s64)1102 %19:_(s32) = G_LOAD %18(p1) :: (load (s32), addrspace 1)1103 %20:_(s32) = G_CONSTANT i32 01104 %21:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %19(s32), %201105 %22:_(s1) = G_CONSTANT i1 true1106 %23:sreg_32_xm0_xexec(s32) = SI_IF %21(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec1107 G_BR %bb.31108 1109 bb.2:1110 successors: %bb.4(0x80000000)1111 1112 %24:_(s32) = G_CONSTANT i32 101113 G_STORE %24(s32), %8(p1) :: (store (s32), addrspace 1)1114 G_BR %bb.41115 1116 bb.3:1117 successors: %bb.5(0x80000000)1118 1119 %25:_(s32) = G_CONSTANT i32 21120 %26:_(s64) = G_SHL %15, %25(s32)1121 %27:_(p1) = G_PTR_ADD %2, %26(s64)1122 %28:_(s32) = G_LOAD %27(p1) :: (load (s32), addrspace 1)1123 %29:_(s32) = G_CONSTANT i32 11124 %30:_(s32) = G_ADD %28, %291125 G_STORE %30(s32), %27(p1) :: (store (s32), addrspace 1)1126 %31:_(s32) = G_ADD %13, %291127 %32:_(s32) = G_CONSTANT i32 1001128 %33:_(s1) = G_ICMP intpred(ult), %13(s32), %321129 %34:_(s1) = G_CONSTANT i1 false1130 G_BR %bb.51131 1132 bb.4:1133 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32)1134 S_ENDPGM 01135 1136 bb.5:1137 successors: %bb.6(0x04000000), %bb.1(0x7c000000)1138 1139 %14:_(s32) = G_PHI %31(s32), %bb.3, %9(s32), %bb.11140 %36:sreg_32_xm0_xexec(s1) = G_PHI %34(s1), %bb.3, %22(s1), %bb.11141 %37:_(s1) = G_PHI %33(s1), %bb.3, %22(s1), %bb.11142 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %23(s32)1143 %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %37(s1), %11(s32)1144 SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec1145 G_BR %bb.61146 1147 bb.6:1148 successors: %bb.2(0x40000000), %bb.4(0x40000000)1149 1150 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %12(s32)1151 %35:sreg_32_xm0_xexec(s32) = SI_IF %36(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec1152 G_BR %bb.21153...1154