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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s3 4---5name: divergent_i1_phi_if_then6legalized: true7tracksRegLiveness: true8body: |9 ; GFX10-LABEL: name: divergent_i1_phi_if_then10 ; GFX10: bb.0:11 ; GFX10-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)12 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr313 ; GFX10-NEXT: {{ $}}14 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr015 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr116 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)17 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr218 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr319 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 620 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C]]21 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 022 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C1]]23 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)24 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[COPY4]](s1)25 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec26 ; GFX10-NEXT: G_BR %bb.127 ; GFX10-NEXT: {{ $}}28 ; GFX10-NEXT: bb.1:29 ; GFX10-NEXT: successors: %bb.2(0x80000000)30 ; GFX10-NEXT: {{ $}}31 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 132 ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C2]]33 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)34 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY5]](s1), $exec_lo, implicit-def $scc35 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY6]](s1), implicit-def $scc36 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc37 ; GFX10-NEXT: {{ $}}38 ; GFX10-NEXT: bb.2:39 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY4]](s1), %bb.0, [[S_OR_B32_]](s1), %bb.140 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)41 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)42 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY7]](s1)43 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 244 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT]], [[C3]]45 ; GFX10-NEXT: G_STORE [[ADD]](s32), [[MV]](p1) :: (store (s32), addrspace 1)46 ; GFX10-NEXT: S_ENDPGM 047 bb.0:48 successors: %bb.1(0x40000000), %bb.2(0x40000000)49 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr350 51 %0:_(s32) = COPY $vgpr052 %1:_(s32) = COPY $vgpr153 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)54 %3:_(s32) = COPY $vgpr255 %4:_(s32) = COPY $vgpr356 %5:_(s32) = G_CONSTANT i32 657 %6:_(s1) = G_ICMP intpred(uge), %3(s32), %558 %7:_(s32) = G_CONSTANT i32 059 %8:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), %4(s32), %760 %9:sreg_32_xm0_xexec(s32) = SI_IF %8(s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec61 G_BR %bb.162 63 bb.1:64 successors: %bb.2(0x80000000)65 66 %10:_(s32) = G_CONSTANT i32 167 %11:_(s1) = G_ICMP intpred(ult), %3(s32), %1068 69 bb.2:70 %12:_(s1) = G_PHI %6(s1), %bb.0, %11(s1), %bb.171 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %9(s32)72 %13:_(s32) = G_SEXT %12(s1)73 %14:_(s32) = G_CONSTANT i32 274 %15:_(s32) = G_ADD %13, %1475 G_STORE %15(s32), %2(p1) :: (store (s32), addrspace 1)76 S_ENDPGM 077...78 79---80name: divergent_i1_phi_if_else81legalized: true82tracksRegLiveness: true83body: |84 ; GFX10-LABEL: name: divergent_i1_phi_if_else85 ; GFX10: bb.0:86 ; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)87 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr388 ; GFX10-NEXT: {{ $}}89 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr090 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr191 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)92 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr293 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr394 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF95 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 096 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY3]](s32), [[C]]97 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[DEF]](s1)98 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[COPY4]](s1)99 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec100 ; GFX10-NEXT: G_BR %bb.3101 ; GFX10-NEXT: {{ $}}102 ; GFX10-NEXT: bb.1:103 ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)104 ; GFX10-NEXT: {{ $}}105 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY4]](s1), %bb.0, %20(s1), %bb.3106 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)107 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[COPY6]](s1)108 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[COPY7]](s1)109 ; GFX10-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_ELSE [[SI_IF]](s32), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec110 ; GFX10-NEXT: G_BR %bb.2111 ; GFX10-NEXT: {{ $}}112 ; GFX10-NEXT: bb.2:113 ; GFX10-NEXT: successors: %bb.4(0x80000000)114 ; GFX10-NEXT: {{ $}}115 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1116 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C1]]117 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP1]](s1)118 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc119 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc120 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc121 ; GFX10-NEXT: G_BR %bb.4122 ; GFX10-NEXT: {{ $}}123 ; GFX10-NEXT: bb.3:124 ; GFX10-NEXT: successors: %bb.1(0x80000000)125 ; GFX10-NEXT: {{ $}}126 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2127 ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C2]]128 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)129 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY5]](s1), $exec_lo, implicit-def $scc130 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY10]](s1), implicit-def $scc131 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc132 ; GFX10-NEXT: G_BR %bb.1133 ; GFX10-NEXT: {{ $}}134 ; GFX10-NEXT: bb.4:135 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[COPY7]](s1), %bb.1, [[S_OR_B32_]](s1), %bb.2136 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)137 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_ELSE]](s32)138 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY11]](s1)139 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2140 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT]], [[C3]]141 ; GFX10-NEXT: G_STORE [[ADD]](s32), [[MV]](p1) :: (store (s32), addrspace 1)142 ; GFX10-NEXT: S_ENDPGM 0143 bb.0:144 successors: %bb.3(0x40000000), %bb.1(0x40000000)145 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3146 147 %0:_(s32) = COPY $vgpr0148 %1:_(s32) = COPY $vgpr1149 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)150 %3:_(s32) = COPY $vgpr2151 %4:_(s32) = COPY $vgpr3152 %5:_(s1) = G_IMPLICIT_DEF153 %6:_(s32) = G_CONSTANT i32 0154 %7:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %4(s32), %6155 %8:sreg_32_xm0_xexec(s32) = SI_IF %7(s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec156 G_BR %bb.3157 158 bb.1:159 successors: %bb.2(0x40000000), %bb.4(0x40000000)160 161 %9:_(s1) = G_PHI %10(s1), %bb.3, %5(s1), %bb.0162 %11:sreg_32_xm0_xexec(s32) = SI_ELSE %8(s32), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec163 G_BR %bb.2164 165 bb.2:166 successors: %bb.4(0x80000000)167 168 %12:_(s32) = G_CONSTANT i32 1169 %13:_(s1) = G_ICMP intpred(uge), %3(s32), %12170 G_BR %bb.4171 172 bb.3:173 successors: %bb.1(0x80000000)174 175 %14:_(s32) = G_CONSTANT i32 2176 %10:_(s1) = G_ICMP intpred(ult), %3(s32), %14177 G_BR %bb.1178 179 bb.4:180 %15:_(s1) = G_PHI %9(s1), %bb.1, %13(s1), %bb.2181 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %11(s32)182 %16:_(s32) = G_SEXT %15(s1)183 %17:_(s32) = G_CONSTANT i32 2184 %18:_(s32) = G_ADD %16, %17185 G_STORE %18(s32), %2(p1) :: (store (s32), addrspace 1)186 S_ENDPGM 0187...188 189---190name: loop_with_1break191legalized: true192tracksRegLiveness: true193body: |194 ; GFX10-LABEL: name: loop_with_1break195 ; GFX10: bb.0:196 ; GFX10-NEXT: successors: %bb.1(0x80000000)197 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3198 ; GFX10-NEXT: {{ $}}199 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0200 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1201 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)202 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2203 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3204 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)205 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF206 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0207 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF208 ; GFX10-NEXT: {{ $}}209 ; GFX10-NEXT: bb.1:210 ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)211 ; GFX10-NEXT: {{ $}}212 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %34(s1), %bb.3213 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %9(s32), %bb.3, [[C]](s32), %bb.0214 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %11(s32), %bb.3215 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)216 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI2]](s32)217 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2218 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C1]](s32)219 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)220 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)221 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0222 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C2]]223 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true224 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[C3]](s1)225 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY4]](s1), $exec_lo, implicit-def $scc226 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY5]](s1), implicit-def $scc227 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc228 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)229 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec230 ; GFX10-NEXT: G_BR %bb.2231 ; GFX10-NEXT: {{ $}}232 ; GFX10-NEXT: bb.2:233 ; GFX10-NEXT: successors: %bb.3(0x80000000)234 ; GFX10-NEXT: {{ $}}235 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2236 ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C4]](s32)237 ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64)238 ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)239 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1240 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C5]]241 ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1)242 ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C5]]243 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 100244 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI2]](s32), [[C6]]245 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP1]](s1)246 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc247 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY7]](s1), implicit-def $scc248 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc249 ; GFX10-NEXT: {{ $}}250 ; GFX10-NEXT: bb.3:251 ; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000)252 ; GFX10-NEXT: {{ $}}253 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, [[S_OR_B32_1]](s1), %bb.2254 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.2, [[DEF]](s32), %bb.1255 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)256 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)257 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY8]](s1), [[PHI1]](s32)258 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec259 ; GFX10-NEXT: G_BR %bb.4260 ; GFX10-NEXT: {{ $}}261 ; GFX10-NEXT: bb.4:262 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)263 ; GFX10-NEXT: S_ENDPGM 0264 bb.0:265 successors: %bb.1(0x80000000)266 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3267 268 %0:_(s32) = COPY $vgpr0269 %1:_(s32) = COPY $vgpr1270 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)271 %3:_(s32) = COPY $vgpr2272 %4:_(s32) = COPY $vgpr3273 %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)274 %6:_(s32) = G_IMPLICIT_DEF275 %7:_(s32) = G_CONSTANT i32 0276 277 bb.1:278 successors: %bb.2(0x40000000), %bb.3(0x40000000)279 280 %8:_(s32) = G_PHI %9(s32), %bb.3, %7(s32), %bb.0281 %10:_(s32) = G_PHI %7(s32), %bb.0, %11(s32), %bb.3282 %12:_(s64) = G_SEXT %10(s32)283 %13:_(s32) = G_CONSTANT i32 2284 %14:_(s64) = G_SHL %12, %13(s32)285 %15:_(p1) = G_PTR_ADD %5, %14(s64)286 %16:_(s32) = G_LOAD %15(p1) :: (load (s32), addrspace 1)287 %17:_(s32) = G_CONSTANT i32 0288 %18:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %16(s32), %17289 %19:_(s1) = G_CONSTANT i1 true290 %20:sreg_32_xm0_xexec(s32) = SI_IF %18(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec291 G_BR %bb.2292 293 bb.2:294 successors: %bb.3(0x80000000)295 296 %21:_(s32) = G_CONSTANT i32 2297 %22:_(s64) = G_SHL %12, %21(s32)298 %23:_(p1) = G_PTR_ADD %2, %22(s64)299 %24:_(s32) = G_LOAD %23(p1) :: (load (s32), addrspace 1)300 %25:_(s32) = G_CONSTANT i32 1301 %26:_(s32) = G_ADD %24, %25302 G_STORE %26(s32), %23(p1) :: (store (s32), addrspace 1)303 %27:_(s32) = G_ADD %10, %25304 %28:_(s32) = G_CONSTANT i32 100305 %29:_(s1) = G_ICMP intpred(ult), %10(s32), %28306 307 bb.3:308 successors: %bb.4(0x04000000), %bb.1(0x7c000000)309 310 %11:_(s32) = G_PHI %27(s32), %bb.2, %6(s32), %bb.1311 %30:_(s1) = G_PHI %29(s1), %bb.2, %19(s1), %bb.1312 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %20(s32)313 %9:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %30(s1), %8(s32)314 SI_LOOP %9(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec315 G_BR %bb.4316 317 bb.4:318 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %9(s32)319 S_ENDPGM 0320...321 322---323name: loop_with_2breaks324legalized: true325tracksRegLiveness: true326body: |327 ; GFX10-LABEL: name: loop_with_2breaks328 ; GFX10: bb.0:329 ; GFX10-NEXT: successors: %bb.1(0x80000000)330 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5331 ; GFX10-NEXT: {{ $}}332 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0333 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1334 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)335 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2336 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3337 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)338 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4339 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5340 ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)341 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF342 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0343 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF344 ; GFX10-NEXT: {{ $}}345 ; GFX10-NEXT: bb.1:346 ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)347 ; GFX10-NEXT: {{ $}}348 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %47(s1), %bb.3349 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.3, [[C]](s32), %bb.0350 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %14(s32), %bb.3351 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)352 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI2]](s32)353 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2354 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C1]](s32)355 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)356 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)357 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0358 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C2]]359 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true360 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[C3]](s1)361 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc362 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY7]](s1), implicit-def $scc363 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc364 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)365 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec366 ; GFX10-NEXT: G_BR %bb.2367 ; GFX10-NEXT: {{ $}}368 ; GFX10-NEXT: bb.2:369 ; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)370 ; GFX10-NEXT: {{ $}}371 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2372 ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C4]](s32)373 ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV2]], [[SHL1]](s64)374 ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)375 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0376 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD1]](s32), [[C5]]377 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s1) = G_CONSTANT i1 true378 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[C6]](s1)379 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[COPY9]](s1)380 ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec381 ; GFX10-NEXT: G_BR %bb.4382 ; GFX10-NEXT: {{ $}}383 ; GFX10-NEXT: bb.3:384 ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000)385 ; GFX10-NEXT: {{ $}}386 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, %46(s1), %bb.5387 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI %32(s32), %bb.5, [[DEF]](s32), %bb.1388 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)389 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)390 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY11]](s1), [[PHI1]](s32)391 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec392 ; GFX10-NEXT: G_BR %bb.6393 ; GFX10-NEXT: {{ $}}394 ; GFX10-NEXT: bb.4:395 ; GFX10-NEXT: successors: %bb.5(0x80000000)396 ; GFX10-NEXT: {{ $}}397 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 2398 ; GFX10-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C7]](s32)399 ; GFX10-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL2]](s64)400 ; GFX10-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s32), addrspace 1)401 ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1402 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[C8]]403 ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD2]](p1) :: (store (s32), addrspace 1)404 ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C8]]405 ; GFX10-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 100406 ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI2]](s32), [[C9]]407 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)408 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc409 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY12]](s1), implicit-def $scc410 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc411 ; GFX10-NEXT: {{ $}}412 ; GFX10-NEXT: bb.5:413 ; GFX10-NEXT: successors: %bb.3(0x80000000)414 ; GFX10-NEXT: {{ $}}415 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32(s1) = PHI [[COPY9]](s1), %bb.2, [[S_OR_B32_1]](s1), %bb.4416 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.4, [[DEF]](s32), %bb.2417 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[PHI5]](s1)418 ; GFX10-NEXT: [[COPY14:%[0-9]+]]:sreg_32(s1) = COPY [[COPY13]](s1)419 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32)420 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc421 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY14]](s1), implicit-def $scc422 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc423 ; GFX10-NEXT: G_BR %bb.3424 ; GFX10-NEXT: {{ $}}425 ; GFX10-NEXT: bb.6:426 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)427 ; GFX10-NEXT: S_ENDPGM 0428 bb.0:429 successors: %bb.1(0x80000000)430 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5431 432 %0:_(s32) = COPY $vgpr0433 %1:_(s32) = COPY $vgpr1434 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)435 %3:_(s32) = COPY $vgpr2436 %4:_(s32) = COPY $vgpr3437 %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)438 %6:_(s32) = COPY $vgpr4439 %7:_(s32) = COPY $vgpr5440 %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)441 %9:_(s32) = G_IMPLICIT_DEF442 %10:_(s32) = G_CONSTANT i32 0443 444 bb.1:445 successors: %bb.2(0x40000000), %bb.3(0x40000000)446 447 %11:_(s32) = G_PHI %12(s32), %bb.3, %10(s32), %bb.0448 %13:_(s32) = G_PHI %10(s32), %bb.0, %14(s32), %bb.3449 %15:_(s64) = G_SEXT %13(s32)450 %16:_(s32) = G_CONSTANT i32 2451 %17:_(s64) = G_SHL %15, %16(s32)452 %18:_(p1) = G_PTR_ADD %5, %17(s64)453 %19:_(s32) = G_LOAD %18(p1) :: (load (s32), addrspace 1)454 %20:_(s32) = G_CONSTANT i32 0455 %21:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %19(s32), %20456 %22:_(s1) = G_CONSTANT i1 true457 %23:sreg_32_xm0_xexec(s32) = SI_IF %21(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec458 G_BR %bb.2459 460 bb.2:461 successors: %bb.4(0x40000000), %bb.5(0x40000000)462 463 %24:_(s32) = G_CONSTANT i32 2464 %25:_(s64) = G_SHL %15, %24(s32)465 %26:_(p1) = G_PTR_ADD %8, %25(s64)466 %27:_(s32) = G_LOAD %26(p1) :: (load (s32), addrspace 1)467 %28:_(s32) = G_CONSTANT i32 0468 %29:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %27(s32), %28469 %30:_(s1) = G_CONSTANT i1 true470 %31:sreg_32_xm0_xexec(s32) = SI_IF %29(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec471 G_BR %bb.4472 473 bb.3:474 successors: %bb.6(0x04000000), %bb.1(0x7c000000)475 476 %14:_(s32) = G_PHI %32(s32), %bb.5, %9(s32), %bb.1477 %33:_(s1) = G_PHI %34(s1), %bb.5, %22(s1), %bb.1478 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %23(s32)479 %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %33(s1), %11(s32)480 SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec481 G_BR %bb.6482 483 bb.4:484 successors: %bb.5(0x80000000)485 486 %35:_(s32) = G_CONSTANT i32 2487 %36:_(s64) = G_SHL %15, %35(s32)488 %37:_(p1) = G_PTR_ADD %2, %36(s64)489 %38:_(s32) = G_LOAD %37(p1) :: (load (s32), addrspace 1)490 %39:_(s32) = G_CONSTANT i32 1491 %40:_(s32) = G_ADD %38, %39492 G_STORE %40(s32), %37(p1) :: (store (s32), addrspace 1)493 %41:_(s32) = G_ADD %13, %39494 %42:_(s32) = G_CONSTANT i32 100495 %43:_(s1) = G_ICMP intpred(ult), %13(s32), %42496 497 bb.5:498 successors: %bb.3(0x80000000)499 500 %32:_(s32) = G_PHI %41(s32), %bb.4, %9(s32), %bb.2501 %34:_(s1) = G_PHI %43(s1), %bb.4, %30(s1), %bb.2502 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %31(s32)503 G_BR %bb.3504 505 bb.6:506 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %12(s32)507 S_ENDPGM 0508...509 510---511name: loop_with_3breaks512legalized: true513tracksRegLiveness: true514body: |515 ; GFX10-LABEL: name: loop_with_3breaks516 ; GFX10: bb.0:517 ; GFX10-NEXT: successors: %bb.1(0x80000000)518 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7519 ; GFX10-NEXT: {{ $}}520 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0521 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1522 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)523 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2524 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3525 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)526 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4527 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5528 ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)529 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6530 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7531 ; GFX10-NEXT: [[MV3:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)532 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF533 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0534 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF535 ; GFX10-NEXT: {{ $}}536 ; GFX10-NEXT: bb.1:537 ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)538 ; GFX10-NEXT: {{ $}}539 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %60(s1), %bb.3540 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %15(s32), %bb.3, [[C]](s32), %bb.0541 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %17(s32), %bb.3542 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)543 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI2]](s32)544 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2545 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C1]](s32)546 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)547 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)548 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0549 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C2]]550 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true551 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[C3]](s1)552 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc553 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc554 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc555 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)556 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec557 ; GFX10-NEXT: G_BR %bb.2558 ; GFX10-NEXT: {{ $}}559 ; GFX10-NEXT: bb.2:560 ; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)561 ; GFX10-NEXT: {{ $}}562 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2563 ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C4]](s32)564 ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV2]], [[SHL1]](s64)565 ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)566 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0567 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD1]](s32), [[C5]]568 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s1) = G_CONSTANT i1 true569 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[C6]](s1)570 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[COPY11]](s1)571 ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec572 ; GFX10-NEXT: G_BR %bb.4573 ; GFX10-NEXT: {{ $}}574 ; GFX10-NEXT: bb.3:575 ; GFX10-NEXT: successors: %bb.8(0x04000000), %bb.1(0x7c000000)576 ; GFX10-NEXT: {{ $}}577 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, %59(s1), %bb.5578 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI %35(s32), %bb.5, [[DEF]](s32), %bb.1579 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)580 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)581 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY13]](s1), [[PHI1]](s32)582 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec583 ; GFX10-NEXT: G_BR %bb.8584 ; GFX10-NEXT: {{ $}}585 ; GFX10-NEXT: bb.4:586 ; GFX10-NEXT: successors: %bb.6(0x40000000), %bb.7(0x40000000)587 ; GFX10-NEXT: {{ $}}588 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 2589 ; GFX10-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C7]](s32)590 ; GFX10-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV3]], [[SHL2]](s64)591 ; GFX10-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s32), addrspace 1)592 ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0593 ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD2]](s32), [[C8]]594 ; GFX10-NEXT: [[C9:%[0-9]+]]:_(s1) = G_CONSTANT i1 true595 ; GFX10-NEXT: [[COPY14:%[0-9]+]]:sreg_32(s1) = COPY [[C9]](s1)596 ; GFX10-NEXT: [[COPY15:%[0-9]+]]:sreg_32(s1) = COPY [[COPY14]](s1)597 ; GFX10-NEXT: [[SI_IF2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP2]](s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec598 ; GFX10-NEXT: G_BR %bb.6599 ; GFX10-NEXT: {{ $}}600 ; GFX10-NEXT: bb.5:601 ; GFX10-NEXT: successors: %bb.3(0x80000000)602 ; GFX10-NEXT: {{ $}}603 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32(s1) = PHI [[COPY11]](s1), %bb.2, %71(s1), %bb.7604 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s32) = G_PHI %46(s32), %bb.7, [[DEF]](s32), %bb.2605 ; GFX10-NEXT: [[COPY16:%[0-9]+]]:sreg_32(s1) = COPY [[PHI5]](s1)606 ; GFX10-NEXT: [[COPY17:%[0-9]+]]:sreg_32(s1) = COPY [[COPY16]](s1)607 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32)608 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc609 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY17]](s1), implicit-def $scc610 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc611 ; GFX10-NEXT: G_BR %bb.3612 ; GFX10-NEXT: {{ $}}613 ; GFX10-NEXT: bb.6:614 ; GFX10-NEXT: successors: %bb.7(0x80000000)615 ; GFX10-NEXT: {{ $}}616 ; GFX10-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 2617 ; GFX10-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C10]](s32)618 ; GFX10-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL3]](s64)619 ; GFX10-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s32), addrspace 1)620 ; GFX10-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 1621 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[C11]]622 ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD3]](p1) :: (store (s32), addrspace 1)623 ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C11]]624 ; GFX10-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 100625 ; GFX10-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI2]](s32), [[C12]]626 ; GFX10-NEXT: [[COPY18:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP3]](s1)627 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY15]](s1), $exec_lo, implicit-def $scc628 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY18]](s1), implicit-def $scc629 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc630 ; GFX10-NEXT: {{ $}}631 ; GFX10-NEXT: bb.7:632 ; GFX10-NEXT: successors: %bb.5(0x80000000)633 ; GFX10-NEXT: {{ $}}634 ; GFX10-NEXT: [[PHI7:%[0-9]+]]:sreg_32(s1) = PHI [[COPY14]](s1), %bb.4, [[S_OR_B32_2]](s1), %bb.6635 ; GFX10-NEXT: [[PHI8:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.6, [[DEF]](s32), %bb.4636 ; GFX10-NEXT: [[COPY19:%[0-9]+]]:sreg_32(s1) = COPY [[PHI7]](s1)637 ; GFX10-NEXT: [[COPY20:%[0-9]+]]:sreg_32(s1) = COPY [[COPY19]](s1)638 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF2]](s32)639 ; GFX10-NEXT: [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY12]](s1), $exec_lo, implicit-def $scc640 ; GFX10-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY20]](s1), implicit-def $scc641 ; GFX10-NEXT: [[S_OR_B32_3:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc642 ; GFX10-NEXT: G_BR %bb.5643 ; GFX10-NEXT: {{ $}}644 ; GFX10-NEXT: bb.8:645 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)646 ; GFX10-NEXT: S_ENDPGM 0647 bb.0:648 successors: %bb.1(0x80000000)649 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7650 651 %0:_(s32) = COPY $vgpr0652 %1:_(s32) = COPY $vgpr1653 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)654 %3:_(s32) = COPY $vgpr2655 %4:_(s32) = COPY $vgpr3656 %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)657 %6:_(s32) = COPY $vgpr4658 %7:_(s32) = COPY $vgpr5659 %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)660 %9:_(s32) = COPY $vgpr6661 %10:_(s32) = COPY $vgpr7662 %11:_(p1) = G_MERGE_VALUES %9(s32), %10(s32)663 %12:_(s32) = G_IMPLICIT_DEF664 %13:_(s32) = G_CONSTANT i32 0665 666 bb.1:667 successors: %bb.2(0x40000000), %bb.3(0x40000000)668 669 %14:_(s32) = G_PHI %15(s32), %bb.3, %13(s32), %bb.0670 %16:_(s32) = G_PHI %13(s32), %bb.0, %17(s32), %bb.3671 %18:_(s64) = G_SEXT %16(s32)672 %19:_(s32) = G_CONSTANT i32 2673 %20:_(s64) = G_SHL %18, %19(s32)674 %21:_(p1) = G_PTR_ADD %5, %20(s64)675 %22:_(s32) = G_LOAD %21(p1) :: (load (s32), addrspace 1)676 %23:_(s32) = G_CONSTANT i32 0677 %24:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %22(s32), %23678 %25:_(s1) = G_CONSTANT i1 true679 %26:sreg_32_xm0_xexec(s32) = SI_IF %24(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec680 G_BR %bb.2681 682 bb.2:683 successors: %bb.4(0x40000000), %bb.5(0x40000000)684 685 %27:_(s32) = G_CONSTANT i32 2686 %28:_(s64) = G_SHL %18, %27(s32)687 %29:_(p1) = G_PTR_ADD %8, %28(s64)688 %30:_(s32) = G_LOAD %29(p1) :: (load (s32), addrspace 1)689 %31:_(s32) = G_CONSTANT i32 0690 %32:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %30(s32), %31691 %33:_(s1) = G_CONSTANT i1 true692 %34:sreg_32_xm0_xexec(s32) = SI_IF %32(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec693 G_BR %bb.4694 695 bb.3:696 successors: %bb.8(0x04000000), %bb.1(0x7c000000)697 698 %17:_(s32) = G_PHI %35(s32), %bb.5, %12(s32), %bb.1699 %36:_(s1) = G_PHI %37(s1), %bb.5, %25(s1), %bb.1700 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %26(s32)701 %15:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %36(s1), %14(s32)702 SI_LOOP %15(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec703 G_BR %bb.8704 705 bb.4:706 successors: %bb.6(0x40000000), %bb.7(0x40000000)707 708 %38:_(s32) = G_CONSTANT i32 2709 %39:_(s64) = G_SHL %18, %38(s32)710 %40:_(p1) = G_PTR_ADD %11, %39(s64)711 %41:_(s32) = G_LOAD %40(p1) :: (load (s32), addrspace 1)712 %42:_(s32) = G_CONSTANT i32 0713 %43:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %41(s32), %42714 %44:_(s1) = G_CONSTANT i1 true715 %45:sreg_32_xm0_xexec(s32) = SI_IF %43(s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec716 G_BR %bb.6717 718 bb.5:719 successors: %bb.3(0x80000000)720 721 %35:_(s32) = G_PHI %46(s32), %bb.7, %12(s32), %bb.2722 %37:_(s1) = G_PHI %47(s1), %bb.7, %33(s1), %bb.2723 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %34(s32)724 G_BR %bb.3725 726 bb.6:727 successors: %bb.7(0x80000000)728 729 %48:_(s32) = G_CONSTANT i32 2730 %49:_(s64) = G_SHL %18, %48(s32)731 %50:_(p1) = G_PTR_ADD %2, %49(s64)732 %51:_(s32) = G_LOAD %50(p1) :: (load (s32), addrspace 1)733 %52:_(s32) = G_CONSTANT i32 1734 %53:_(s32) = G_ADD %51, %52735 G_STORE %53(s32), %50(p1) :: (store (s32), addrspace 1)736 %54:_(s32) = G_ADD %16, %52737 %55:_(s32) = G_CONSTANT i32 100738 %56:_(s1) = G_ICMP intpred(ult), %16(s32), %55739 740 bb.7:741 successors: %bb.5(0x80000000)742 743 %46:_(s32) = G_PHI %54(s32), %bb.6, %12(s32), %bb.4744 %47:_(s1) = G_PHI %56(s1), %bb.6, %44(s1), %bb.4745 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %45(s32)746 G_BR %bb.5747 748 bb.8:749 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)750 S_ENDPGM 0751...752 753---754name: loop_with_div_break_with_body755legalized: true756tracksRegLiveness: true757body: |758 ; GFX10-LABEL: name: loop_with_div_break_with_body759 ; GFX10: bb.0:760 ; GFX10-NEXT: successors: %bb.1(0x80000000)761 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5762 ; GFX10-NEXT: {{ $}}763 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0764 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1765 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)766 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2767 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3768 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)769 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4770 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5771 ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)772 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF773 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0774 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF775 ; GFX10-NEXT: [[DEF2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF776 ; GFX10-NEXT: [[DEF3:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF777 ; GFX10-NEXT: {{ $}}778 ; GFX10-NEXT: bb.1:779 ; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)780 ; GFX10-NEXT: {{ $}}781 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF3]](s1), %bb.0, %61(s1), %bb.5782 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[DEF2]](s1), %bb.0, %48(s1), %bb.5783 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %38(s1), %bb.5784 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.5, [[C]](s32), %bb.0785 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %14(s32), %bb.5786 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)787 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI1]](s1)788 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI2]](s1)789 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI4]](s32)790 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2791 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C1]](s32)792 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)793 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)794 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0795 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C2]]796 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true797 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[C3]](s1)798 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[C3]](s1)799 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY7]](s1), $exec_lo, implicit-def $scc800 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY10]](s1), implicit-def $scc801 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc802 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[S_OR_B32_]](s1)803 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc804 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc805 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc806 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_1]](s1)807 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec808 ; GFX10-NEXT: G_BR %bb.3809 ; GFX10-NEXT: {{ $}}810 ; GFX10-NEXT: bb.2:811 ; GFX10-NEXT: successors: %bb.4(0x80000000)812 ; GFX10-NEXT: {{ $}}813 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10814 ; GFX10-NEXT: G_STORE [[C4]](s32), [[MV2]](p1) :: (store (s32), addrspace 1)815 ; GFX10-NEXT: G_BR %bb.4816 ; GFX10-NEXT: {{ $}}817 ; GFX10-NEXT: bb.3:818 ; GFX10-NEXT: successors: %bb.5(0x80000000)819 ; GFX10-NEXT: {{ $}}820 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2821 ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C5]](s32)822 ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64)823 ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)824 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1825 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C6]]826 ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1)827 ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI4]], [[C6]]828 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 100829 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI4]](s32), [[C7]]830 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP1]](s1)831 ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s1) = G_CONSTANT i1 false832 ; GFX10-NEXT: [[COPY14:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[C8]](s1)833 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY11]](s1), $exec_lo, implicit-def $scc834 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY14]](s1), implicit-def $scc835 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc836 ; GFX10-NEXT: [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY12]](s1), $exec_lo, implicit-def $scc837 ; GFX10-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY13]](s1), implicit-def $scc838 ; GFX10-NEXT: [[S_OR_B32_3:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc839 ; GFX10-NEXT: G_BR %bb.5840 ; GFX10-NEXT: {{ $}}841 ; GFX10-NEXT: bb.4:842 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32)843 ; GFX10-NEXT: S_ENDPGM 0844 ; GFX10-NEXT: {{ $}}845 ; GFX10-NEXT: bb.5:846 ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000)847 ; GFX10-NEXT: {{ $}}848 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_1]](s1), %bb.1, [[S_OR_B32_3]](s1), %bb.3849 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[S_OR_B32_]](s1), %bb.1, [[S_OR_B32_2]](s1), %bb.3850 ; GFX10-NEXT: [[PHI7:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.3, [[DEF]](s32), %bb.1851 ; GFX10-NEXT: [[COPY15:%[0-9]+]]:sreg_32(s1) = COPY [[PHI5]](s1)852 ; GFX10-NEXT: [[COPY16:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI6]](s1)853 ; GFX10-NEXT: [[COPY17:%[0-9]+]]:sreg_32(s1) = COPY [[COPY16]](s1)854 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)855 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY15]](s1), [[PHI3]](s32)856 ; GFX10-NEXT: [[S_ANDN2_B32_4:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc857 ; GFX10-NEXT: [[S_AND_B32_4:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY17]](s1), implicit-def $scc858 ; GFX10-NEXT: [[S_OR_B32_4:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_4]](s1), [[S_AND_B32_4]](s1), implicit-def $scc859 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec860 ; GFX10-NEXT: G_BR %bb.6861 ; GFX10-NEXT: {{ $}}862 ; GFX10-NEXT: bb.6:863 ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)864 ; GFX10-NEXT: {{ $}}865 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)866 ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[S_OR_B32_4]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec867 ; GFX10-NEXT: G_BR %bb.2868 bb.0:869 successors: %bb.1(0x80000000)870 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5871 872 %0:_(s32) = COPY $vgpr0873 %1:_(s32) = COPY $vgpr1874 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)875 %3:_(s32) = COPY $vgpr2876 %4:_(s32) = COPY $vgpr3877 %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)878 %6:_(s32) = COPY $vgpr4879 %7:_(s32) = COPY $vgpr5880 %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)881 %9:_(s32) = G_IMPLICIT_DEF882 %10:_(s32) = G_CONSTANT i32 0883 884 bb.1:885 successors: %bb.3(0x40000000), %bb.5(0x40000000)886 887 %11:_(s32) = G_PHI %12(s32), %bb.5, %10(s32), %bb.0888 %13:_(s32) = G_PHI %10(s32), %bb.0, %14(s32), %bb.5889 %15:_(s64) = G_SEXT %13(s32)890 %16:_(s32) = G_CONSTANT i32 2891 %17:_(s64) = G_SHL %15, %16(s32)892 %18:_(p1) = G_PTR_ADD %5, %17(s64)893 %19:_(s32) = G_LOAD %18(p1) :: (load (s32), addrspace 1)894 %20:_(s32) = G_CONSTANT i32 0895 %21:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %19(s32), %20896 %22:_(s1) = G_CONSTANT i1 true897 %23:sreg_32_xm0_xexec(s32) = SI_IF %21(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec898 G_BR %bb.3899 900 bb.2:901 successors: %bb.4(0x80000000)902 903 %24:_(s32) = G_CONSTANT i32 10904 G_STORE %24(s32), %8(p1) :: (store (s32), addrspace 1)905 G_BR %bb.4906 907 bb.3:908 successors: %bb.5(0x80000000)909 910 %25:_(s32) = G_CONSTANT i32 2911 %26:_(s64) = G_SHL %15, %25(s32)912 %27:_(p1) = G_PTR_ADD %2, %26(s64)913 %28:_(s32) = G_LOAD %27(p1) :: (load (s32), addrspace 1)914 %29:_(s32) = G_CONSTANT i32 1915 %30:_(s32) = G_ADD %28, %29916 G_STORE %30(s32), %27(p1) :: (store (s32), addrspace 1)917 %31:_(s32) = G_ADD %13, %29918 %32:_(s32) = G_CONSTANT i32 100919 %33:_(s1) = G_ICMP intpred(ult), %13(s32), %32920 %34:_(s1) = G_CONSTANT i1 false921 G_BR %bb.5922 923 bb.4:924 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32)925 S_ENDPGM 0926 927 bb.5:928 successors: %bb.6(0x04000000), %bb.1(0x7c000000)929 930 %14:_(s32) = G_PHI %31(s32), %bb.3, %9(s32), %bb.1931 %36:sreg_32_xm0_xexec(s1) = G_PHI %34(s1), %bb.3, %22(s1), %bb.1932 %37:_(s1) = G_PHI %33(s1), %bb.3, %22(s1), %bb.1933 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %23(s32)934 %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %37(s1), %11(s32)935 SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec936 G_BR %bb.6937 938 bb.6:939 successors: %bb.2(0x40000000), %bb.4(0x40000000)940 941 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %12(s32)942 %35:sreg_32_xm0_xexec(s32) = SI_IF %36(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec943 G_BR %bb.2944...945 946---947name: irreducible_cfg948legalized: true949tracksRegLiveness: true950body: |951 ; GFX10-LABEL: name: irreducible_cfg952 ; GFX10: bb.0:953 ; GFX10-NEXT: successors: %bb.8(0x80000000)954 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5955 ; GFX10-NEXT: {{ $}}956 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0957 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1958 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2959 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3960 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4961 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5962 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF963 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY4]](s32), [[COPY1]]964 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true965 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[C]]966 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0967 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF968 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[DEF]](s1)969 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)970 ; GFX10-NEXT: G_BR %bb.8971 ; GFX10-NEXT: {{ $}}972 ; GFX10-NEXT: bb.1:973 ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)974 ; GFX10-NEXT: {{ $}}975 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI %52(s1), %bb.5, %51(s1), %bb.8976 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI %45(s1), %bb.5, %44(s1), %bb.8977 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI]](s1)978 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)979 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[COPY9]](s1)980 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %17(s32)981 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true982 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 %40(s1), $exec_lo, implicit-def $scc983 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY10]](s1), implicit-def $scc984 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc985 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[C2]](s1)986 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[COPY11]](s1)987 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY8]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec988 ; GFX10-NEXT: G_BR %bb.2989 ; GFX10-NEXT: {{ $}}990 ; GFX10-NEXT: bb.2:991 ; GFX10-NEXT: successors: %bb.4(0x80000000)992 ; GFX10-NEXT: {{ $}}993 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY4]](s32), [[COPY]]994 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0995 ; GFX10-NEXT: G_BR %bb.4996 ; GFX10-NEXT: {{ $}}997 ; GFX10-NEXT: bb.3:998 ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.8(0x7c000000)999 ; GFX10-NEXT: {{ $}}1000 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:sreg_32(s1) = PHI [[COPY11]](s1), %bb.1, %59(s1), %bb.71001 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI %23(s1), %bb.7, [[DEF]](s1), %bb.11002 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[PHI2]](s1)1003 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)1004 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY13]](s1), %27(s32)1005 ; GFX10-NEXT: [[COPY14:%[0-9]+]]:sreg_32(s1) = COPY [[COPY9]](s1)1006 ; GFX10-NEXT: [[COPY15:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)1007 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.8, implicit-def $exec, implicit-def $scc, implicit $exec1008 ; GFX10-NEXT: G_BR %bb.61009 ; GFX10-NEXT: {{ $}}1010 ; GFX10-NEXT: bb.4:1011 ; GFX10-NEXT: successors: %bb.7(0x04000000), %bb.4(0x7c000000)1012 ; GFX10-NEXT: {{ $}}1013 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[C3]](s32), %bb.2, %29(s32), %bb.41014 ; GFX10-NEXT: [[INT1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ICMP1]](s1), [[PHI4]](s32)1015 ; GFX10-NEXT: SI_LOOP [[INT1]](s32), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec1016 ; GFX10-NEXT: G_BR %bb.71017 ; GFX10-NEXT: {{ $}}1018 ; GFX10-NEXT: bb.5:1019 ; GFX10-NEXT: successors: %bb.1(0x80000000)1020 ; GFX10-NEXT: {{ $}}1021 ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY5]](s32), [[COPY]]1022 ; GFX10-NEXT: [[COPY16:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)1023 ; GFX10-NEXT: [[FREEZE:%[0-9]+]]:_(s1) = G_FREEZE [[ICMP]]1024 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true1025 ; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[FREEZE]], [[C4]]1026 ; GFX10-NEXT: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP2]], [[XOR1]]1027 ; GFX10-NEXT: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[OR]], [[C4]]1028 ; GFX10-NEXT: [[COPY17:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[XOR2]](s1)1029 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 %46(s1), $exec_lo, implicit-def $scc1030 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY16]](s1), implicit-def $scc1031 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc1032 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 %53(s1), $exec_lo, implicit-def $scc1033 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY17]](s1), implicit-def $scc1034 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc1035 ; GFX10-NEXT: G_BR %bb.11036 ; GFX10-NEXT: {{ $}}1037 ; GFX10-NEXT: bb.6:1038 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)1039 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[S_OR_B32_]](s1), [[COPY3]], [[COPY2]]1040 ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[SELECT]](s32)1041 ; GFX10-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)1042 ; GFX10-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr01043 ; GFX10-NEXT: {{ $}}1044 ; GFX10-NEXT: bb.7:1045 ; GFX10-NEXT: successors: %bb.3(0x80000000)1046 ; GFX10-NEXT: {{ $}}1047 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT1]](s32)1048 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 false1049 ; GFX10-NEXT: [[COPY18:%[0-9]+]]:sreg_32(s1) = COPY [[C5]](s1)1050 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s1) = G_CONSTANT i1 true1051 ; GFX10-NEXT: [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY12]](s1), $exec_lo, implicit-def $scc1052 ; GFX10-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY18]](s1), implicit-def $scc1053 ; GFX10-NEXT: [[S_OR_B32_3:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc1054 ; GFX10-NEXT: G_BR %bb.31055 ; GFX10-NEXT: {{ $}}1056 ; GFX10-NEXT: bb.8:1057 ; GFX10-NEXT: successors: %bb.5(0x40000000), %bb.1(0x40000000)1058 ; GFX10-NEXT: {{ $}}1059 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[COPY7]](s1), %bb.0, [[COPY15]](s1), %bb.31060 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:sreg_32(s1) = PHI [[COPY6]](s1), %bb.0, [[COPY14]](s1), %bb.31061 ; GFX10-NEXT: [[PHI7:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, [[S_OR_B32_]](s1), %bb.31062 ; GFX10-NEXT: [[PHI8:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.3, [[C1]](s32), %bb.01063 ; GFX10-NEXT: [[COPY19:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI5]](s1)1064 ; GFX10-NEXT: [[COPY20:%[0-9]+]]:sreg_32(s1) = COPY [[PHI6]](s1)1065 ; GFX10-NEXT: [[COPY21:%[0-9]+]]:sreg_32(s1) = COPY [[PHI7]](s1)1066 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s1) = G_CONSTANT i1 true1067 ; GFX10-NEXT: [[COPY22:%[0-9]+]]:sreg_32(s1) = COPY [[COPY20]](s1)1068 ; GFX10-NEXT: [[COPY23:%[0-9]+]]:sreg_32(s1) = COPY [[COPY22]](s1)1069 ; GFX10-NEXT: [[COPY24:%[0-9]+]]:sreg_32(s1) = COPY [[C7]](s1)1070 ; GFX10-NEXT: [[COPY25:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[COPY24]](s1)1071 ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY19]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec1072 ; GFX10-NEXT: G_BR %bb.51073 bb.0:1074 successors: %bb.8(0x80000000)1075 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr51076 1077 %0:_(s32) = COPY $vgpr01078 %1:_(s32) = COPY $vgpr11079 %2:_(s32) = COPY $vgpr21080 %3:_(s32) = COPY $vgpr31081 %4:_(s32) = COPY $vgpr41082 %5:_(s32) = COPY $vgpr51083 %6:_(s1) = G_IMPLICIT_DEF1084 %7:_(s1) = G_ICMP intpred(sgt), %4(s32), %11085 %8:_(s1) = G_CONSTANT i1 true1086 %9:_(s1) = G_XOR %7, %81087 %10:_(s32) = G_CONSTANT i32 01088 G_BR %bb.81089 1090 bb.1:1091 successors: %bb.2(0x40000000), %bb.3(0x40000000)1092 1093 %11:_(s1) = G_PHI %12(s1), %bb.5, %13(s1), %bb.81094 %14:sreg_32_xm0_xexec(s1) = G_PHI %15(s1), %bb.5, %16(s1), %bb.81095 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %17(s32)1096 %18:_(s1) = G_CONSTANT i1 true1097 %19:sreg_32_xm0_xexec(s32) = SI_IF %14(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec1098 G_BR %bb.21099 1100 bb.2:1101 successors: %bb.4(0x80000000)1102 1103 %20:_(s1) = G_ICMP intpred(sle), %4(s32), %01104 %21:_(s32) = G_CONSTANT i32 01105 G_BR %bb.41106 1107 bb.3:1108 successors: %bb.6(0x04000000), %bb.8(0x7c000000)1109 1110 %22:_(s1) = G_PHI %23(s1), %bb.7, %6(s1), %bb.11111 %24:_(s1) = G_PHI %25(s1), %bb.7, %18(s1), %bb.11112 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %19(s32)1113 %26:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %24(s1), %27(s32)1114 SI_LOOP %26(s32), %bb.8, implicit-def $exec, implicit-def $scc, implicit $exec1115 G_BR %bb.61116 1117 bb.4:1118 successors: %bb.7(0x04000000), %bb.4(0x7c000000)1119 1120 %28:_(s32) = G_PHI %21(s32), %bb.2, %29(s32), %bb.41121 %29:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %20(s1), %28(s32)1122 SI_LOOP %29(s32), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec1123 G_BR %bb.71124 1125 bb.5:1126 successors: %bb.1(0x80000000)1127 1128 %12:_(s1) = G_ICMP intpred(sgt), %5(s32), %01129 %30:_(s1) = G_FREEZE %71130 %31:_(s1) = G_CONSTANT i1 true1131 %32:_(s1) = G_XOR %30, %311132 %33:_(s1) = G_OR %12, %321133 %15:_(s1) = G_XOR %33, %311134 G_BR %bb.11135 1136 bb.6:1137 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %26(s32)1138 %34:_(s32) = G_SELECT %11(s1), %3, %21139 %35:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %34(s32)1140 $sgpr0 = COPY %35(s32)1141 SI_RETURN_TO_EPILOG implicit $sgpr01142 1143 bb.7:1144 successors: %bb.3(0x80000000)1145 1146 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %29(s32)1147 %25:_(s1) = G_CONSTANT i1 false1148 %23:_(s1) = G_CONSTANT i1 true1149 G_BR %bb.31150 1151 bb.8:1152 successors: %bb.5(0x40000000), %bb.1(0x40000000)1153 1154 %27:_(s32) = G_PHI %26(s32), %bb.3, %10(s32), %bb.01155 %13:_(s1) = G_PHI %6(s1), %bb.0, %11(s1), %bb.31156 %36:sreg_32_xm0_xexec(s1) = G_PHI %9(s1), %bb.0, %22(s1), %bb.31157 %16:_(s1) = G_CONSTANT i1 true1158 %17:sreg_32_xm0_xexec(s32) = SI_IF %36(s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec1159 G_BR %bb.51160...1161 1162# Keep original test that had phi with three incomings.1163# FixIrreducible no longer generates such phi.1164---1165name: irreducible_cfg_phi_with_three_incomings1166legalized: true1167tracksRegLiveness: true1168body: |1169 ; GFX10-LABEL: name: irreducible_cfg_phi_with_three_incomings1170 ; GFX10: bb.0:1171 ; GFX10-NEXT: successors: %bb.7(0x80000000)1172 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr51173 ; GFX10-NEXT: {{ $}}1174 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr01175 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr11176 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr21177 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr31178 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr41179 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr51180 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF1181 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY4]](s32), [[COPY1]]1182 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01183 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF1184 ; GFX10-NEXT: [[DEF2:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF1185 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)1186 ; GFX10-NEXT: G_BR %bb.71187 ; GFX10-NEXT: {{ $}}1188 ; GFX10-NEXT: bb.1:1189 ; GFX10-NEXT: successors: %bb.3(0x80000000)1190 ; GFX10-NEXT: {{ $}}1191 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY4]](s32), [[COPY]]1192 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01193 ; GFX10-NEXT: G_BR %bb.31194 ; GFX10-NEXT: {{ $}}1195 ; GFX10-NEXT: bb.2:1196 ; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.7(0x40000000)1197 ; GFX10-NEXT: {{ $}}1198 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI %52(s1), %bb.6, %56(s1), %bb.71199 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI %41(s1), %bb.6, %40(s1), %bb.71200 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s1) = G_PHI %12(s1), %bb.6, [[DEF]](s1), %bb.71201 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI2]](s1)1202 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI]](s1)1203 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)1204 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)1205 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY9]](s1), %17(s32)1206 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc1207 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY7]](s1), implicit-def $scc1208 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc1209 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[S_OR_B32_]](s1)1210 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec1211 ; GFX10-NEXT: G_BR %bb.41212 ; GFX10-NEXT: {{ $}}1213 ; GFX10-NEXT: bb.3:1214 ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.3(0x7c000000)1215 ; GFX10-NEXT: {{ $}}1216 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1, %19(s32), %bb.31217 ; GFX10-NEXT: [[INT1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ICMP1]](s1), [[PHI3]](s32)1218 ; GFX10-NEXT: SI_LOOP [[INT1]](s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec1219 ; GFX10-NEXT: G_BR %bb.61220 ; GFX10-NEXT: {{ $}}1221 ; GFX10-NEXT: bb.4:1222 ; GFX10-NEXT: successors: %bb.5(0x04000000), %bb.7(0x7c000000)1223 ; GFX10-NEXT: {{ $}}1224 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)1225 ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY5]](s32), [[COPY]]1226 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)1227 ; GFX10-NEXT: [[FREEZE:%[0-9]+]]:_(s1) = G_FREEZE [[ICMP]]1228 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true1229 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[C2]](s1)1230 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[FREEZE]], [[C2]]1231 ; GFX10-NEXT: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP2]], [[XOR]]1232 ; GFX10-NEXT: [[INT2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[OR]](s1), %26(s32)1233 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 01234 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 %34(s1), $exec_lo, implicit-def $scc1235 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc1236 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc1237 ; GFX10-NEXT: [[DEF3:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF1238 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc1239 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY12]](s1), implicit-def $scc1240 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc1241 ; GFX10-NEXT: SI_LOOP [[INT2]](s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec1242 ; GFX10-NEXT: G_BR %bb.51243 ; GFX10-NEXT: {{ $}}1244 ; GFX10-NEXT: bb.5:1245 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT2]](s32)1246 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[S_OR_B32_1]](s1), [[COPY3]], [[COPY2]]1247 ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[SELECT]](s32)1248 ; GFX10-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)1249 ; GFX10-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr01250 ; GFX10-NEXT: {{ $}}1251 ; GFX10-NEXT: bb.6:1252 ; GFX10-NEXT: successors: %bb.2(0x80000000)1253 ; GFX10-NEXT: {{ $}}1254 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT1]](s32)1255 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 false1256 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[C4]](s1)1257 ; GFX10-NEXT: [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 %48(s1), $exec_lo, implicit-def $scc1258 ; GFX10-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY13]](s1), implicit-def $scc1259 ; GFX10-NEXT: [[S_OR_B32_3:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc1260 ; GFX10-NEXT: [[DEF4:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF1261 ; GFX10-NEXT: G_BR %bb.21262 ; GFX10-NEXT: {{ $}}1263 ; GFX10-NEXT: bb.7:1264 ; GFX10-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)1265 ; GFX10-NEXT: {{ $}}1266 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[COPY6]](s1), %bb.0, [[S_OR_B32_]](s1), %bb.2, [[S_OR_B32_2]](s1), %bb.41267 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32(s1) = PHI [[DEF2]](s1), %bb.0, [[PHI1]](s1), %bb.2, [[DEF3]](s1), %bb.41268 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, [[PHI6]](s1), %bb.2, [[S_OR_B32_1]](s1), %bb.41269 ; GFX10-NEXT: [[PHI7:%[0-9]+]]:_(s32) = G_PHI [[INT2]](s32), %bb.4, [[PHI7]](s32), %bb.2, [[C]](s32), %bb.01270 ; GFX10-NEXT: [[PHI8:%[0-9]+]]:_(s32) = G_PHI [[C3]](s32), %bb.4, [[INT]](s32), %bb.2, [[C]](s32), %bb.01271 ; GFX10-NEXT: [[COPY14:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI4]](s1)1272 ; GFX10-NEXT: [[COPY15:%[0-9]+]]:sreg_32(s1) = COPY [[PHI5]](s1)1273 ; GFX10-NEXT: [[COPY16:%[0-9]+]]:sreg_32(s1) = COPY [[PHI6]](s1)1274 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 true1275 ; GFX10-NEXT: [[COPY17:%[0-9]+]]:sreg_32(s1) = COPY [[C5]](s1)1276 ; GFX10-NEXT: [[S_ANDN2_B32_4:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY15]](s1), $exec_lo, implicit-def $scc1277 ; GFX10-NEXT: [[S_AND_B32_4:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY17]](s1), implicit-def $scc1278 ; GFX10-NEXT: [[S_OR_B32_4:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_4]](s1), [[S_AND_B32_4]](s1), implicit-def $scc1279 ; GFX10-NEXT: [[COPY18:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_4]](s1)1280 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY14]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec1281 ; GFX10-NEXT: G_BR %bb.11282 bb.0:1283 successors: %bb.7(0x80000000)1284 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr51285 1286 %0:_(s32) = COPY $vgpr01287 %1:_(s32) = COPY $vgpr11288 %2:_(s32) = COPY $vgpr21289 %3:_(s32) = COPY $vgpr31290 %4:_(s32) = COPY $vgpr41291 %5:_(s32) = COPY $vgpr51292 %6:_(s1) = G_IMPLICIT_DEF1293 %7:_(s1) = G_ICMP intpred(sgt), %4(s32), %11294 %8:_(s32) = G_CONSTANT i32 01295 G_BR %bb.71296 1297 bb.1:1298 successors: %bb.3(0x80000000)1299 1300 %9:_(s1) = G_ICMP intpred(sle), %4(s32), %01301 %10:_(s32) = G_CONSTANT i32 01302 G_BR %bb.31303 1304 bb.2:1305 successors: %bb.4(0x40000000), %bb.7(0x40000000)1306 1307 %11:_(s1) = G_PHI %12(s1), %bb.6, %6(s1), %bb.71308 %13:_(s1) = G_PHI %12(s1), %bb.6, %14(s1), %bb.71309 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)1310 %16:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %13(s1), %17(s32)1311 SI_LOOP %16(s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec1312 G_BR %bb.41313 1314 bb.3:1315 successors: %bb.6(0x04000000), %bb.3(0x7c000000)1316 1317 %18:_(s32) = G_PHI %10(s32), %bb.1, %19(s32), %bb.31318 %19:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %9(s1), %18(s32)1319 SI_LOOP %19(s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec1320 G_BR %bb.61321 1322 bb.4:1323 successors: %bb.5(0x04000000), %bb.7(0x7c000000)1324 1325 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %16(s32)1326 %20:_(s1) = G_ICMP intpred(sgt), %5(s32), %01327 %21:_(s1) = G_FREEZE %71328 %22:_(s1) = G_CONSTANT i1 true1329 %23:_(s1) = G_XOR %21, %221330 %24:_(s1) = G_OR %20, %231331 %25:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %24(s1), %26(s32)1332 %27:_(s32) = G_CONSTANT i32 01333 SI_LOOP %25(s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec1334 G_BR %bb.51335 1336 bb.5:1337 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %25(s32)1338 %28:_(s32) = G_SELECT %20(s1), %3, %21339 %29:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %28(s32)1340 $sgpr0 = COPY %29(s32)1341 SI_RETURN_TO_EPILOG implicit $sgpr01342 1343 bb.6:1344 successors: %bb.2(0x80000000)1345 1346 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %19(s32)1347 %12:_(s1) = G_CONSTANT i1 false1348 G_BR %bb.21349 1350 bb.7:1351 successors: %bb.1(0x40000000), %bb.2(0x40000000)1352 1353 %26:_(s32) = G_PHI %25(s32), %bb.4, %26(s32), %bb.2, %8(s32), %bb.01354 %17:_(s32) = G_PHI %27(s32), %bb.4, %16(s32), %bb.2, %8(s32), %bb.01355 %30:sreg_32_xm0_xexec(s1) = G_PHI %7(s1), %bb.0, %11(s1), %bb.2, %22(s1), %bb.41356 %14:_(s1) = G_CONSTANT i1 true1357 %15:sreg_32_xm0_xexec(s32) = SI_IF %30(s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec1358 G_BR %bb.11359...1360