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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s3 4---5name: temporal_divergent_i1_phi6legalized: true7tracksRegLiveness: true8body: |9 ; GFX10-LABEL: name: temporal_divergent_i1_phi10 ; GFX10: bb.0:11 ; GFX10-NEXT: successors: %bb.1(0x80000000)12 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr213 ; GFX10-NEXT: {{ $}}14 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr015 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr116 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr217 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)18 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 019 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true20 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF21 ; GFX10-NEXT: {{ $}}22 ; GFX10-NEXT: bb.1:23 ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)24 ; GFX10-NEXT: {{ $}}25 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %19(s1), %bb.126 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C]](s32), %bb.027 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %9(s32), %bb.128 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C1]](s1), %bb.0, %11(s1), %bb.129 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)30 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)31 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true32 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI3]], [[C2]]33 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI2]](s32)34 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]35 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 136 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C3]]37 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI1]](s32)38 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY4]](s1), $exec_lo, implicit-def $scc39 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY3]](s1), implicit-def $scc40 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc41 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec42 ; GFX10-NEXT: G_BR %bb.243 ; GFX10-NEXT: {{ $}}44 ; GFX10-NEXT: bb.2:45 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)46 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+0047 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+0048 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[S_OR_B32_]](s1), [[C5]], [[C4]]49 ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32))50 ; GFX10-NEXT: SI_RETURN51 bb.0:52 successors: %bb.1(0x80000000)53 liveins: $vgpr0, $vgpr1, $vgpr254 55 %0:_(s32) = COPY $vgpr056 %1:_(s32) = COPY $vgpr157 %2:_(s32) = COPY $vgpr258 %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32)59 %4:_(s32) = G_CONSTANT i32 060 %5:_(s1) = G_CONSTANT i1 true61 62 bb.1:63 successors: %bb.2(0x04000000), %bb.1(0x7c000000)64 65 %6:_(s32) = G_PHI %7(s32), %bb.1, %4(s32), %bb.066 %8:_(s32) = G_PHI %4(s32), %bb.0, %9(s32), %bb.167 %10:_(s1) = G_PHI %5(s1), %bb.0, %11(s1), %bb.168 %12:_(s1) = G_CONSTANT i1 true69 %11:_(s1) = G_XOR %10, %1270 %13:_(s32) = G_UITOFP %8(s32)71 %14:_(s1) = G_FCMP floatpred(ogt), %13(s32), %072 %15:_(s32) = G_CONSTANT i32 173 %9:_(s32) = G_ADD %8, %1574 %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %14(s1), %6(s32)75 SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec76 G_BR %bb.277 78 bb.2:79 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %7(s32)80 %16:_(s32) = G_FCONSTANT float 0.000000e+0081 %17:_(s32) = G_FCONSTANT float 1.000000e+0082 %18:_(s32) = G_SELECT %10(s1), %17, %1683 G_STORE %18(s32), %3(p0) :: (store (s32))84 SI_RETURN85...86 87---88name: temporal_divergent_i1_non_phi89legalized: true90tracksRegLiveness: true91body: |92 ; GFX10-LABEL: name: temporal_divergent_i1_non_phi93 ; GFX10: bb.0:94 ; GFX10-NEXT: successors: %bb.1(0x80000000)95 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr296 ; GFX10-NEXT: {{ $}}97 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr098 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr199 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2100 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)101 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0102 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true103 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF104 ; GFX10-NEXT: {{ $}}105 ; GFX10-NEXT: bb.1:106 ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)107 ; GFX10-NEXT: {{ $}}108 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %19(s1), %bb.1109 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C]](s32), %bb.0110 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %9(s32), %bb.1111 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C1]](s1), %bb.0, %11(s1), %bb.1112 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)113 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true114 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI3]], [[C2]]115 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)116 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI2]](s32)117 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]118 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1119 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C3]]120 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI1]](s32)121 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY3]](s1), $exec_lo, implicit-def $scc122 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY4]](s1), implicit-def $scc123 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc124 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec125 ; GFX10-NEXT: G_BR %bb.2126 ; GFX10-NEXT: {{ $}}127 ; GFX10-NEXT: bb.2:128 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)129 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00130 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00131 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[S_OR_B32_]](s1), [[C5]], [[C4]]132 ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32))133 ; GFX10-NEXT: SI_RETURN134 bb.0:135 successors: %bb.1(0x80000000)136 liveins: $vgpr0, $vgpr1, $vgpr2137 138 %0:_(s32) = COPY $vgpr0139 %1:_(s32) = COPY $vgpr1140 %2:_(s32) = COPY $vgpr2141 %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32)142 %4:_(s32) = G_CONSTANT i32 0143 %5:_(s1) = G_CONSTANT i1 true144 145 bb.1:146 successors: %bb.2(0x04000000), %bb.1(0x7c000000)147 148 %6:_(s32) = G_PHI %7(s32), %bb.1, %4(s32), %bb.0149 %8:_(s32) = G_PHI %4(s32), %bb.0, %9(s32), %bb.1150 %10:_(s1) = G_PHI %5(s1), %bb.0, %11(s1), %bb.1151 %12:_(s1) = G_CONSTANT i1 true152 %11:_(s1) = G_XOR %10, %12153 %13:_(s32) = G_UITOFP %8(s32)154 %14:_(s1) = G_FCMP floatpred(ogt), %13(s32), %0155 %15:_(s32) = G_CONSTANT i32 1156 %9:_(s32) = G_ADD %8, %15157 %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %14(s1), %6(s32)158 SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec159 G_BR %bb.2160 161 bb.2:162 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %7(s32)163 %16:_(s32) = G_FCONSTANT float 0.000000e+00164 %17:_(s32) = G_FCONSTANT float 1.000000e+00165 %18:_(s32) = G_SELECT %11(s1), %17, %16166 G_STORE %18(s32), %3(p0) :: (store (s32))167 SI_RETURN168...169 170---171name: loop_with_1break172legalized: true173tracksRegLiveness: true174body: |175 ; GFX10-LABEL: name: loop_with_1break176 ; GFX10: bb.0:177 ; GFX10-NEXT: successors: %bb.1(0x80000000)178 ; GFX10-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2179 ; GFX10-NEXT: {{ $}}180 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0181 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1182 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)183 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2184 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr0185 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr1186 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)187 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr2188 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr3189 ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY5]](s32), [[COPY6]](s32)190 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF191 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0192 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF193 ; GFX10-NEXT: [[DEF2:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF194 ; GFX10-NEXT: {{ $}}195 ; GFX10-NEXT: bb.1:196 ; GFX10-NEXT: successors: %bb.3(0x50000000), %bb.5(0x30000000)197 ; GFX10-NEXT: {{ $}}198 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF2]](s1), %bb.0, %47(s1), %bb.5199 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %37(s1), %bb.5200 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %13(s32), %bb.5, [[C]](s32), %bb.0201 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %15(s32), %bb.5202 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)203 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)204 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI3]](s32)205 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2206 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C1]](s32)207 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)208 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)209 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0210 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C2]]211 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true212 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[C3]](s1)213 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY7]](s1), $exec_lo, implicit-def $scc214 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc215 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc216 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)217 ; GFX10-NEXT: G_BRCOND [[ICMP]](s1), %bb.3218 ; GFX10-NEXT: G_BR %bb.5219 ; GFX10-NEXT: {{ $}}220 ; GFX10-NEXT: bb.2:221 ; GFX10-NEXT: successors: %bb.4(0x80000000)222 ; GFX10-NEXT: {{ $}}223 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10224 ; GFX10-NEXT: G_STORE [[C4]](s32), [[MV2]](p1) :: (store (s32), addrspace 1)225 ; GFX10-NEXT: G_BR %bb.4226 ; GFX10-NEXT: {{ $}}227 ; GFX10-NEXT: bb.3:228 ; GFX10-NEXT: successors: %bb.5(0x80000000)229 ; GFX10-NEXT: {{ $}}230 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2231 ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C5]](s32)232 ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64)233 ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)234 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1235 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C6]]236 ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1)237 ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI3]], [[C6]]238 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI3]](s32), [[COPY2]]239 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP1]](s1)240 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s1) = G_CONSTANT i1 false241 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc242 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc243 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc244 ; GFX10-NEXT: G_BR %bb.5245 ; GFX10-NEXT: {{ $}}246 ; GFX10-NEXT: bb.4:247 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %34(s32)248 ; GFX10-NEXT: S_ENDPGM 0249 ; GFX10-NEXT: {{ $}}250 ; GFX10-NEXT: bb.5:251 ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000)252 ; GFX10-NEXT: {{ $}}253 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, [[S_OR_B32_1]](s1), %bb.3254 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.3, [[DEF]](s32), %bb.1255 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_PHI [[C7]](s1), %bb.3, [[C3]](s1), %bb.1256 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[PHI4]](s1)257 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[PHI6]](s1)258 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY12]](s1), [[PHI2]](s32)259 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc260 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY13]](s1), implicit-def $scc261 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc262 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec263 ; GFX10-NEXT: G_BR %bb.6264 ; GFX10-NEXT: {{ $}}265 ; GFX10-NEXT: bb.6:266 ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)267 ; GFX10-NEXT: {{ $}}268 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)269 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[S_OR_B32_2]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec270 ; GFX10-NEXT: G_BR %bb.2271 bb.0:272 successors: %bb.1(0x80000000)273 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2274 275 %0:_(s32) = COPY $vgpr0276 %1:_(s32) = COPY $vgpr1277 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)278 %3:_(s32) = COPY $vgpr2279 %4:_(s32) = COPY $sgpr0280 %5:_(s32) = COPY $sgpr1281 %6:_(p1) = G_MERGE_VALUES %4(s32), %5(s32)282 %7:_(s32) = COPY $sgpr2283 %8:_(s32) = COPY $sgpr3284 %9:_(p1) = G_MERGE_VALUES %7(s32), %8(s32)285 %10:_(s32) = G_IMPLICIT_DEF286 %11:_(s32) = G_CONSTANT i32 0287 288 bb.1:289 successors: %bb.3(0x50000000), %bb.5(0x30000000)290 291 %12:_(s32) = G_PHI %13(s32), %bb.5, %11(s32), %bb.0292 %14:_(s32) = G_PHI %11(s32), %bb.0, %15(s32), %bb.5293 %16:_(s64) = G_SEXT %14(s32)294 %17:_(s32) = G_CONSTANT i32 2295 %18:_(s64) = G_SHL %16, %17(s32)296 %19:_(p1) = G_PTR_ADD %6, %18(s64)297 %20:_(s32) = G_LOAD %19(p1) :: (load (s32), addrspace 1)298 %21:_(s32) = G_CONSTANT i32 0299 %22:_(s1) = G_ICMP intpred(ne), %20(s32), %21300 %23:_(s1) = G_CONSTANT i1 true301 G_BRCOND %22(s1), %bb.3302 G_BR %bb.5303 304 bb.2:305 successors: %bb.4(0x80000000)306 307 %24:_(s32) = G_CONSTANT i32 10308 G_STORE %24(s32), %9(p1) :: (store (s32), addrspace 1)309 G_BR %bb.4310 311 bb.3:312 successors: %bb.5(0x80000000)313 314 %25:_(s32) = G_CONSTANT i32 2315 %26:_(s64) = G_SHL %16, %25(s32)316 %27:_(p1) = G_PTR_ADD %2, %26(s64)317 %28:_(s32) = G_LOAD %27(p1) :: (load (s32), addrspace 1)318 %29:_(s32) = G_CONSTANT i32 1319 %30:_(s32) = G_ADD %28, %29320 G_STORE %30(s32), %27(p1) :: (store (s32), addrspace 1)321 %31:_(s32) = G_ADD %14, %29322 %32:_(s1) = G_ICMP intpred(ult), %14(s32), %3323 %33:_(s1) = G_CONSTANT i1 false324 G_BR %bb.5325 326 bb.4:327 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %34(s32)328 S_ENDPGM 0329 330 bb.5:331 successors: %bb.6(0x04000000), %bb.1(0x7c000000)332 333 %15:_(s32) = G_PHI %31(s32), %bb.3, %10(s32), %bb.1334 %35:sreg_32_xm0_xexec(s1) = G_PHI %33(s1), %bb.3, %23(s1), %bb.1335 %36:_(s1) = G_PHI %32(s1), %bb.3, %23(s1), %bb.1336 %13:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %36(s1), %12(s32)337 SI_LOOP %13(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec338 G_BR %bb.6339 340 bb.6:341 successors: %bb.2(0x40000000), %bb.4(0x40000000)342 343 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %13(s32)344 %34:sreg_32_xm0_xexec(s32) = SI_IF %35(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec345 G_BR %bb.2346...347 348---349name: nested_loops_temporal_divergence_inner350legalized: true351tracksRegLiveness: true352body: |353 ; GFX10-LABEL: name: nested_loops_temporal_divergence_inner354 ; GFX10: bb.0:355 ; GFX10-NEXT: successors: %bb.1(0x80000000)356 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7357 ; GFX10-NEXT: {{ $}}358 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0359 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1360 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2361 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3362 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)363 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4364 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5365 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)366 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00367 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C]]368 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0369 ; GFX10-NEXT: {{ $}}370 ; GFX10-NEXT: bb.1:371 ; GFX10-NEXT: successors: %bb.2(0x80000000)372 ; GFX10-NEXT: {{ $}}373 ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.3, [[C1]](s32), %bb.0374 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %14(s32), %bb.3375 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32)376 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2377 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)378 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[MV]], [[SHL]](s64)379 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32))380 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0381 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF382 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[FCMP]](s1)383 ; GFX10-NEXT: {{ $}}384 ; GFX10-NEXT: bb.2:385 ; GFX10-NEXT: successors: %bb.3(0x04000000), %bb.2(0x7c000000)386 ; GFX10-NEXT: {{ $}}387 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:sreg_32(s1) = PHI [[COPY6]](s1), %bb.1, %43(s1), %bb.2388 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.1, %35(s1), %bb.2389 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[C3]](s32), %bb.1, %22(s32), %bb.2390 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s32) = G_PHI %24(s32), %bb.2, [[C3]](s32), %bb.1391 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI2]](s1)392 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)393 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true394 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[COPY7]], [[C4]]395 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)396 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI5]](s32)397 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1398 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI5]], [[C5]]399 ; GFX10-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[LOAD]]400 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP1]](s1), [[PHI4]](s32)401 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc402 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc403 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc404 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)405 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec406 ; GFX10-NEXT: G_BR %bb.3407 ; GFX10-NEXT: {{ $}}408 ; GFX10-NEXT: bb.3:409 ; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000)410 ; GFX10-NEXT: {{ $}}411 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)412 ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[MV1]], [[SEXT]](s64)413 ; GFX10-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[S_OR_B32_]](s1)414 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1415 ; GFX10-NEXT: G_STORE [[ZEXT]](s32), [[PTR_ADD1]](p0) :: (store (s8))416 ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C6]]417 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI1]](s32), [[COPY1]]418 ; GFX10-NEXT: [[INT1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ICMP]](s1), [[PHI]](s32)419 ; GFX10-NEXT: SI_LOOP [[INT1]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec420 ; GFX10-NEXT: G_BR %bb.4421 ; GFX10-NEXT: {{ $}}422 ; GFX10-NEXT: bb.4:423 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT1]](s32)424 ; GFX10-NEXT: SI_RETURN425 bb.0:426 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7427 428 %0:_(s32) = COPY $vgpr0429 %1:_(s32) = COPY $vgpr1430 %2:_(s32) = COPY $vgpr2431 %3:_(s32) = COPY $vgpr3432 %4:_(p0) = G_MERGE_VALUES %2(s32), %3(s32)433 %5:_(s32) = COPY $vgpr4434 %6:_(s32) = COPY $vgpr5435 %7:_(p0) = G_MERGE_VALUES %5(s32), %6(s32)436 %8:_(s32) = G_FCONSTANT float 1.000000e+00437 %9:_(s1) = G_FCMP floatpred(ogt), %0(s32), %8438 %10:_(s32) = G_CONSTANT i32 0439 440 bb.1:441 %11:_(s32) = G_PHI %12(s32), %bb.3, %10(s32), %bb.0442 %13:_(s32) = G_PHI %10(s32), %bb.0, %14(s32), %bb.3443 %15:_(s64) = G_SEXT %13(s32)444 %16:_(s32) = G_CONSTANT i32 2445 %17:_(s64) = G_SHL %15, %16(s32)446 %18:_(p0) = G_PTR_ADD %4, %17(s64)447 %19:_(s32) = G_LOAD %18(p0) :: (load (s32))448 %20:_(s32) = G_CONSTANT i32 0449 450 bb.2:451 successors: %bb.3(0x04000000), %bb.2(0x7c000000)452 453 %21:_(s32) = G_PHI %20(s32), %bb.1, %22(s32), %bb.2454 %23:_(s32) = G_PHI %24(s32), %bb.2, %20(s32), %bb.1455 %25:_(s1) = G_PHI %26(s1), %bb.2, %9(s1), %bb.1456 %27:_(s1) = G_CONSTANT i1 true457 %26:_(s1) = G_XOR %25, %27458 %28:_(s32) = G_UITOFP %23(s32)459 %29:_(s32) = G_CONSTANT i32 1460 %24:_(s32) = G_ADD %23, %29461 %30:_(s1) = G_FCMP floatpred(ogt), %28(s32), %19462 %22:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %30(s1), %21(s32)463 SI_LOOP %22(s32), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec464 G_BR %bb.3465 466 bb.3:467 successors: %bb.4(0x04000000), %bb.1(0x7c000000)468 469 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %22(s32)470 %31:_(p0) = G_PTR_ADD %7, %15(s64)471 %32:_(s32) = G_ZEXT %26(s1)472 %33:_(s32) = G_CONSTANT i32 1473 G_STORE %32(s32), %31(p0) :: (store (s8))474 %14:_(s32) = G_ADD %13, %33475 %34:_(s1) = G_ICMP intpred(ult), %13(s32), %1476 %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %34(s1), %11(s32)477 SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec478 G_BR %bb.4479 480 bb.4:481 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %12(s32)482 SI_RETURN483...484 485---486name: nested_loops_temporal_divergence_outer487legalized: true488tracksRegLiveness: true489body: |490 ; GFX10-LABEL: name: nested_loops_temporal_divergence_outer491 ; GFX10: bb.0:492 ; GFX10-NEXT: successors: %bb.1(0x80000000)493 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7494 ; GFX10-NEXT: {{ $}}495 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0496 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1497 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2498 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3499 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)500 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4501 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5502 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)503 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00504 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C]]505 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0506 ; GFX10-NEXT: {{ $}}507 ; GFX10-NEXT: bb.1:508 ; GFX10-NEXT: successors: %bb.2(0x80000000)509 ; GFX10-NEXT: {{ $}}510 ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.3, [[C1]](s32), %bb.0511 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %14(s32), %bb.3512 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32)513 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2514 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)515 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[MV]], [[SHL]](s64)516 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32))517 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0518 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF519 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[FCMP]](s1)520 ; GFX10-NEXT: {{ $}}521 ; GFX10-NEXT: bb.2:522 ; GFX10-NEXT: successors: %bb.3(0x04000000), %bb.2(0x7c000000)523 ; GFX10-NEXT: {{ $}}524 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:sreg_32(s1) = PHI [[COPY6]](s1), %bb.1, %43(s1), %bb.2525 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.1, %35(s1), %bb.2526 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[C3]](s32), %bb.1, %22(s32), %bb.2527 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s32) = G_PHI %24(s32), %bb.2, [[C3]](s32), %bb.1528 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI2]](s1)529 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)530 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true531 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[COPY7]], [[C4]]532 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)533 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI5]](s32)534 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1535 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI5]], [[C5]]536 ; GFX10-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[LOAD]]537 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP1]](s1), [[PHI4]](s32)538 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc539 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc540 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc541 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)542 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec543 ; GFX10-NEXT: G_BR %bb.3544 ; GFX10-NEXT: {{ $}}545 ; GFX10-NEXT: bb.3:546 ; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000)547 ; GFX10-NEXT: {{ $}}548 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)549 ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[MV1]], [[SEXT]](s64)550 ; GFX10-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[S_OR_B32_]](s1)551 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1552 ; GFX10-NEXT: G_STORE [[ZEXT]](s32), [[PTR_ADD1]](p0) :: (store (s8))553 ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C6]]554 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI1]](s32), [[COPY1]]555 ; GFX10-NEXT: [[INT1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ICMP]](s1), [[PHI]](s32)556 ; GFX10-NEXT: SI_LOOP [[INT1]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec557 ; GFX10-NEXT: G_BR %bb.4558 ; GFX10-NEXT: {{ $}}559 ; GFX10-NEXT: bb.4:560 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT1]](s32)561 ; GFX10-NEXT: SI_RETURN562 bb.0:563 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7564 565 %0:_(s32) = COPY $vgpr0566 %1:_(s32) = COPY $vgpr1567 %2:_(s32) = COPY $vgpr2568 %3:_(s32) = COPY $vgpr3569 %4:_(p0) = G_MERGE_VALUES %2(s32), %3(s32)570 %5:_(s32) = COPY $vgpr4571 %6:_(s32) = COPY $vgpr5572 %7:_(p0) = G_MERGE_VALUES %5(s32), %6(s32)573 %8:_(s32) = G_FCONSTANT float 1.000000e+00574 %9:_(s1) = G_FCMP floatpred(ogt), %0(s32), %8575 %10:_(s32) = G_CONSTANT i32 0576 577 bb.1:578 %11:_(s32) = G_PHI %12(s32), %bb.3, %10(s32), %bb.0579 %13:_(s32) = G_PHI %10(s32), %bb.0, %14(s32), %bb.3580 %15:_(s64) = G_SEXT %13(s32)581 %16:_(s32) = G_CONSTANT i32 2582 %17:_(s64) = G_SHL %15, %16(s32)583 %18:_(p0) = G_PTR_ADD %4, %17(s64)584 %19:_(s32) = G_LOAD %18(p0) :: (load (s32))585 %20:_(s32) = G_CONSTANT i32 0586 587 bb.2:588 successors: %bb.3(0x04000000), %bb.2(0x7c000000)589 590 %21:_(s32) = G_PHI %20(s32), %bb.1, %22(s32), %bb.2591 %23:_(s32) = G_PHI %24(s32), %bb.2, %20(s32), %bb.1592 %25:_(s1) = G_PHI %26(s1), %bb.2, %9(s1), %bb.1593 %27:_(s1) = G_CONSTANT i1 true594 %26:_(s1) = G_XOR %25, %27595 %28:_(s32) = G_UITOFP %23(s32)596 %29:_(s32) = G_CONSTANT i32 1597 %24:_(s32) = G_ADD %23, %29598 %30:_(s1) = G_FCMP floatpred(ogt), %28(s32), %19599 %22:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %30(s1), %21(s32)600 SI_LOOP %22(s32), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec601 G_BR %bb.3602 603 bb.3:604 successors: %bb.4(0x04000000), %bb.1(0x7c000000)605 606 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %22(s32)607 %31:_(p0) = G_PTR_ADD %7, %15(s64)608 %32:_(s32) = G_ZEXT %26(s1)609 %33:_(s32) = G_CONSTANT i32 1610 G_STORE %32(s32), %31(p0) :: (store (s8))611 %14:_(s32) = G_ADD %13, %33612 %34:_(s1) = G_ICMP intpred(ult), %13(s32), %1613 %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %34(s1), %11(s32)614 SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec615 G_BR %bb.4616 617 bb.4:618 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %12(s32)619 SI_RETURN620...621 622---623name: nested_loops_temporal_divergence_both624legalized: true625tracksRegLiveness: true626body: |627 ; GFX10-LABEL: name: nested_loops_temporal_divergence_both628 ; GFX10: bb.0:629 ; GFX10-NEXT: successors: %bb.1(0x80000000)630 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7631 ; GFX10-NEXT: {{ $}}632 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0633 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1634 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2635 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3636 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)637 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4638 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5639 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)640 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6641 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7642 ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)643 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00644 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s32), [[C]]645 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0646 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF647 ; GFX10-NEXT: {{ $}}648 ; GFX10-NEXT: bb.1:649 ; GFX10-NEXT: successors: %bb.2(0x80000000)650 ; GFX10-NEXT: {{ $}}651 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %39(s1), %bb.3652 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %15(s32), %bb.3, [[C1]](s32), %bb.0653 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %17(s32), %bb.3654 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI2]](s32)655 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2656 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)657 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[MV]], [[SHL]](s64)658 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32))659 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0660 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[FCMP]](s1)661 ; GFX10-NEXT: {{ $}}662 ; GFX10-NEXT: bb.2:663 ; GFX10-NEXT: successors: %bb.3(0x04000000), %bb.2(0x7c000000)664 ; GFX10-NEXT: {{ $}}665 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[COPY8]](s1), %bb.1, %48(s1), %bb.2666 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:sreg_32(s1) = PHI [[PHI]](s1), %bb.1, %39(s1), %bb.2667 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s32) = G_PHI [[C3]](s32), %bb.1, %25(s32), %bb.2668 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s32) = G_PHI %27(s32), %bb.2, [[C3]](s32), %bb.1669 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)670 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[PHI4]](s1)671 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true672 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[COPY9]], [[C4]]673 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)674 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI6]](s32)675 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1676 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI6]], [[C5]]677 ; GFX10-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[LOAD]]678 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP1]](s1), [[PHI5]](s32)679 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc680 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc681 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc682 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)683 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec684 ; GFX10-NEXT: G_BR %bb.3685 ; GFX10-NEXT: {{ $}}686 ; GFX10-NEXT: bb.3:687 ; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000)688 ; GFX10-NEXT: {{ $}}689 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)690 ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[MV1]], [[SEXT]](s64)691 ; GFX10-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[S_OR_B32_]](s1)692 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1693 ; GFX10-NEXT: G_STORE [[ZEXT]](s32), [[PTR_ADD1]](p0) :: (store (s8))694 ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C6]]695 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI2]](s32), [[COPY1]]696 ; GFX10-NEXT: [[INT1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ICMP]](s1), [[PHI1]](s32)697 ; GFX10-NEXT: SI_LOOP [[INT1]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec698 ; GFX10-NEXT: G_BR %bb.4699 ; GFX10-NEXT: {{ $}}700 ; GFX10-NEXT: bb.4:701 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT1]](s32)702 ; GFX10-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[S_OR_B32_]](s1)703 ; GFX10-NEXT: G_STORE [[ZEXT1]](s32), [[MV2]](p0) :: (store (s8))704 ; GFX10-NEXT: SI_RETURN705 bb.0:706 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7707 708 %0:_(s32) = COPY $vgpr0709 %1:_(s32) = COPY $vgpr1710 %2:_(s32) = COPY $vgpr2711 %3:_(s32) = COPY $vgpr3712 %4:_(p0) = G_MERGE_VALUES %2(s32), %3(s32)713 %5:_(s32) = COPY $vgpr4714 %6:_(s32) = COPY $vgpr5715 %7:_(p0) = G_MERGE_VALUES %5(s32), %6(s32)716 %8:_(s32) = COPY $vgpr6717 %9:_(s32) = COPY $vgpr7718 %10:_(p0) = G_MERGE_VALUES %8(s32), %9(s32)719 %11:_(s32) = G_FCONSTANT float 1.000000e+00720 %12:_(s1) = G_FCMP floatpred(ogt), %0(s32), %11721 %13:_(s32) = G_CONSTANT i32 0722 723 bb.1:724 %14:_(s32) = G_PHI %15(s32), %bb.3, %13(s32), %bb.0725 %16:_(s32) = G_PHI %13(s32), %bb.0, %17(s32), %bb.3726 %18:_(s64) = G_SEXT %16(s32)727 %19:_(s32) = G_CONSTANT i32 2728 %20:_(s64) = G_SHL %18, %19(s32)729 %21:_(p0) = G_PTR_ADD %4, %20(s64)730 %22:_(s32) = G_LOAD %21(p0) :: (load (s32))731 %23:_(s32) = G_CONSTANT i32 0732 733 bb.2:734 successors: %bb.3(0x04000000), %bb.2(0x7c000000)735 736 %24:_(s32) = G_PHI %23(s32), %bb.1, %25(s32), %bb.2737 %26:_(s32) = G_PHI %27(s32), %bb.2, %23(s32), %bb.1738 %28:_(s1) = G_PHI %29(s1), %bb.2, %12(s1), %bb.1739 %30:_(s1) = G_CONSTANT i1 true740 %29:_(s1) = G_XOR %28, %30741 %31:_(s32) = G_UITOFP %26(s32)742 %32:_(s32) = G_CONSTANT i32 1743 %27:_(s32) = G_ADD %26, %32744 %33:_(s1) = G_FCMP floatpred(ogt), %31(s32), %22745 %25:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %33(s1), %24(s32)746 SI_LOOP %25(s32), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec747 G_BR %bb.3748 749 bb.3:750 successors: %bb.4(0x04000000), %bb.1(0x7c000000)751 752 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %25(s32)753 %34:_(p0) = G_PTR_ADD %7, %18(s64)754 %35:_(s32) = G_ZEXT %29(s1)755 %36:_(s32) = G_CONSTANT i32 1756 G_STORE %35(s32), %34(p0) :: (store (s8))757 %17:_(s32) = G_ADD %16, %36758 %37:_(s1) = G_ICMP intpred(ult), %16(s32), %1759 %15:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %37(s1), %14(s32)760 SI_LOOP %15(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec761 G_BR %bb.4762 763 bb.4:764 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)765 %38:_(s32) = G_ZEXT %29(s1)766 G_STORE %38(s32), %10(p0) :: (store (s8))767 SI_RETURN768...769