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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s3 4---5name: temporal_divergent_i326legalized: true7tracksRegLiveness: true8body: |9 ; GFX10-LABEL: name: temporal_divergent_i3210 ; GFX10: bb.0:11 ; GFX10-NEXT: successors: %bb.1(0x80000000)12 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr213 ; GFX10-NEXT: {{ $}}14 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr015 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr116 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr217 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)18 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -119 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 020 ; GFX10-NEXT: {{ $}}21 ; GFX10-NEXT: bb.1:22 ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)23 ; GFX10-NEXT: {{ $}}24 ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C1]](s32), %bb.025 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %9(s32), %bb.126 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C2]]28 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32), implicit $exec_lo29 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[ADD]](s32)30 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]31 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI]](s32)32 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec33 ; GFX10-NEXT: G_BR %bb.234 ; GFX10-NEXT: {{ $}}35 ; GFX10-NEXT: bb.2:36 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)37 ; GFX10-NEXT: G_STORE [[COPY3]](s32), [[MV]](p0) :: (store (s32))38 ; GFX10-NEXT: SI_RETURN39 bb.0:40 successors: %bb.1(0x80000000)41 liveins: $vgpr0, $vgpr1, $vgpr242 43 %0:_(s32) = COPY $vgpr044 %1:_(s32) = COPY $vgpr145 %2:_(s32) = COPY $vgpr246 %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32)47 %4:_(s32) = G_CONSTANT i32 -148 %5:_(s32) = G_CONSTANT i32 049 50 bb.1:51 successors: %bb.2(0x04000000), %bb.1(0x7c000000)52 53 %6:_(s32) = G_PHI %7(s32), %bb.1, %5(s32), %bb.054 %8:_(s32) = G_PHI %4(s32), %bb.0, %9(s32), %bb.155 %10:_(s32) = G_CONSTANT i32 156 %9:_(s32) = G_ADD %8, %1057 %11:_(s32) = G_UITOFP %9(s32)58 %12:_(s1) = G_FCMP floatpred(ogt), %11(s32), %059 %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %12(s1), %6(s32)60 SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec61 G_BR %bb.262 63 bb.2:64 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %7(s32)65 G_STORE %9(s32), %3(p0) :: (store (s32))66 SI_RETURN67...68 69---70name: temporal_divergent_i32_multiple_use71legalized: true72tracksRegLiveness: true73body: |74 ; GFX10-LABEL: name: temporal_divergent_i32_multiple_use75 ; GFX10: bb.0:76 ; GFX10-NEXT: successors: %bb.1(0x80000000)77 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr478 ; GFX10-NEXT: {{ $}}79 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr080 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr181 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr282 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)83 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr384 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr485 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)86 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -187 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 088 ; GFX10-NEXT: {{ $}}89 ; GFX10-NEXT: bb.1:90 ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)91 ; GFX10-NEXT: {{ $}}92 ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %10(s32), %bb.1, [[C1]](s32), %bb.093 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %12(s32), %bb.194 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 195 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C2]]96 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32), implicit $exec_lo97 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[ADD]](s32)98 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]99 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI]](s32)100 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec101 ; GFX10-NEXT: G_BR %bb.2102 ; GFX10-NEXT: {{ $}}103 ; GFX10-NEXT: bb.2:104 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)105 ; GFX10-NEXT: G_STORE [[COPY5]](s32), [[MV]](p0) :: (store (s32))106 ; GFX10-NEXT: G_STORE [[COPY5]](s32), [[MV1]](p0) :: (store (s32))107 ; GFX10-NEXT: SI_RETURN108 bb.0:109 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4110 111 %0:_(s32) = COPY $vgpr0112 %1:_(s32) = COPY $vgpr1113 %2:_(s32) = COPY $vgpr2114 %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32)115 %4:_(s32) = COPY $vgpr3116 %5:_(s32) = COPY $vgpr4117 %6:_(p0) = G_MERGE_VALUES %4(s32), %5(s32)118 %7:_(s32) = G_CONSTANT i32 -1119 %8:_(s32) = G_CONSTANT i32 0120 121 bb.1:122 successors: %bb.2(0x04000000), %bb.1(0x7c000000)123 124 %9:_(s32) = G_PHI %10(s32), %bb.1, %8(s32), %bb.0125 %11:_(s32) = G_PHI %7(s32), %bb.0, %12(s32), %bb.1126 %13:_(s32) = G_CONSTANT i32 1127 %12:_(s32) = G_ADD %11, %13128 %14:_(s32) = G_UITOFP %12(s32)129 %15:_(s1) = G_FCMP floatpred(ogt), %14(s32), %0130 %10:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %15(s1), %9(s32)131 SI_LOOP %10(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec132 G_BR %bb.2133 134 bb.2:135 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %10(s32)136 G_STORE %12(s32), %3(p0) :: (store (s32))137 G_STORE %12(s32), %6(p0) :: (store (s32))138 SI_RETURN139...140