254 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s3 4; Make sure the branch targets are correct after lowering llvm.amdgcn.if5 6define i32 @divergent_if_swap_brtarget_order0(i32 %value) {7; CHECK-LABEL: divergent_if_swap_brtarget_order0:8; CHECK: ; %bb.0: ; %entry9; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v011; CHECK-NEXT: ; implicit-def: $vgpr012; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc13; CHECK-NEXT: s_cbranch_execz .LBB0_214; CHECK-NEXT: ; %bb.1: ; %if.true15; CHECK-NEXT: global_load_dword v0, v[0:1], off glc16; CHECK-NEXT: s_waitcnt vmcnt(0)17; CHECK-NEXT: .LBB0_2: ; %endif18; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]19; CHECK-NEXT: s_setpc_b64 s[30:31]20entry:21 %c = icmp ne i32 %value, 022 br i1 %c, label %if.true, label %endif23 24if.true:25 %val = load volatile i32, ptr addrspace(1) poison26 br label %endif27 28endif:29 %v = phi i32 [ %val, %if.true ], [ poison, %entry ]30 ret i32 %v31}32 33define i32 @divergent_if_swap_brtarget_order1(i32 %value) {34; CHECK-LABEL: divergent_if_swap_brtarget_order1:35; CHECK: ; %bb.0: ; %entry36; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)37; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v038; CHECK-NEXT: ; implicit-def: $vgpr039; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc40; CHECK-NEXT: s_cbranch_execz .LBB1_241; CHECK-NEXT: ; %bb.1: ; %if.true42; CHECK-NEXT: global_load_dword v0, v[0:1], off glc43; CHECK-NEXT: s_waitcnt vmcnt(0)44; CHECK-NEXT: .LBB1_2: ; %endif45; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]46; CHECK-NEXT: s_setpc_b64 s[30:31]47entry:48 %c = icmp ne i32 %value, 049 br i1 %c, label %if.true, label %endif50 51endif:52 %v = phi i32 [ %val, %if.true ], [ poison, %entry ]53 ret i32 %v54 55if.true:56 %val = load volatile i32, ptr addrspace(1) poison57 br label %endif58}59 60; Make sure and 1 is inserted on llvm.amdgcn.if61define i32 @divergent_if_nonboolean_condition0(i32 %value) {62; CHECK-LABEL: divergent_if_nonboolean_condition0:63; CHECK: ; %bb.0: ; %entry64; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)65; CHECK-NEXT: v_and_b32_e32 v0, 1, v066; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v067; CHECK-NEXT: ; implicit-def: $vgpr068; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc69; CHECK-NEXT: s_cbranch_execz .LBB2_270; CHECK-NEXT: ; %bb.1: ; %if.true71; CHECK-NEXT: global_load_dword v0, v[0:1], off glc72; CHECK-NEXT: s_waitcnt vmcnt(0)73; CHECK-NEXT: .LBB2_2: ; %endif74; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]75; CHECK-NEXT: s_setpc_b64 s[30:31]76entry:77 %c = trunc i32 %value to i178 br i1 %c, label %if.true, label %endif79 80if.true:81 %val = load volatile i32, ptr addrspace(1) poison82 br label %endif83 84endif:85 %v = phi i32 [ %val, %if.true ], [ poison, %entry ]86 ret i32 %v87}88 89; Make sure and 1 is inserted on llvm.amdgcn.if90define i32 @divergent_if_nonboolean_condition1(ptr addrspace(1) %ptr) {91; CHECK-LABEL: divergent_if_nonboolean_condition1:92; CHECK: ; %bb.0: ; %entry93; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)94; CHECK-NEXT: global_load_dword v0, v[0:1], off95; CHECK-NEXT: s_waitcnt vmcnt(0)96; CHECK-NEXT: v_and_b32_e32 v0, 1, v097; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v098; CHECK-NEXT: ; implicit-def: $vgpr099; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc100; CHECK-NEXT: s_cbranch_execz .LBB3_2101; CHECK-NEXT: ; %bb.1: ; %if.true102; CHECK-NEXT: global_load_dword v0, v[0:1], off glc103; CHECK-NEXT: s_waitcnt vmcnt(0)104; CHECK-NEXT: .LBB3_2: ; %endif105; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]106; CHECK-NEXT: s_setpc_b64 s[30:31]107entry:108 %value = load i32, ptr addrspace(1) %ptr109 %c = trunc i32 %value to i1110 br i1 %c, label %if.true, label %endif111 112if.true:113 %val = load volatile i32, ptr addrspace(1) poison114 br label %endif115 116endif:117 %v = phi i32 [ %val, %if.true ], [ poison, %entry ]118 ret i32 %v119}120 121@external_constant = external addrspace(4) constant i32, align 4122@const.ptr = external addrspace(4) constant ptr, align 4123 124; Make sure this case compiles. G_ICMP was mis-mapped due to having125; the result register class constrained by llvm.amdgcn.if lowering.126define void @constrained_if_register_class() {127; CHECK-LABEL: constrained_if_register_class:128; CHECK: ; %bb.0: ; %bb129; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)130; CHECK-NEXT: s_getpc_b64 s[4:5]131; CHECK-NEXT: s_add_u32 s4, s4, external_constant@gotpcrel32@lo+4132; CHECK-NEXT: s_addc_u32 s5, s5, external_constant@gotpcrel32@hi+12133; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0134; CHECK-NEXT: s_waitcnt lgkmcnt(0)135; CHECK-NEXT: s_load_dword s4, s[4:5], 0x0136; CHECK-NEXT: s_waitcnt lgkmcnt(0)137; CHECK-NEXT: s_cmp_lg_u32 s4, 0138; CHECK-NEXT: s_cbranch_scc0 .LBB4_2139; CHECK-NEXT: ; %bb.1: ; %bb12140; CHECK-NEXT: s_setpc_b64 s[30:31]141; CHECK-NEXT: .LBB4_2: ; %bb2142; CHECK-NEXT: s_getpc_b64 s[4:5]143; CHECK-NEXT: s_add_u32 s4, s4, const.ptr@gotpcrel32@lo+4144; CHECK-NEXT: s_addc_u32 s5, s5, const.ptr@gotpcrel32@hi+12145; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0146; CHECK-NEXT: s_mov_b32 s6, -1147; CHECK-NEXT: s_waitcnt lgkmcnt(0)148; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0149; CHECK-NEXT: s_waitcnt lgkmcnt(0)150; CHECK-NEXT: v_mov_b32_e32 v0, s4151; CHECK-NEXT: v_mov_b32_e32 v1, s5152; CHECK-NEXT: flat_load_dword v0, v[0:1]153; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)154; CHECK-NEXT: v_cmp_ngt_f32_e32 vcc, 1.0, v0155; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc156; CHECK-NEXT: ; %bb.3: ; %bb7157; CHECK-NEXT: s_mov_b32 s6, 0158; CHECK-NEXT: ; %bb.4: ; %bb8159; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]160; CHECK-NEXT: v_cmp_eq_u32_e64 s[6:7], s6, 0161; CHECK-NEXT: s_and_saveexec_b64 s[4:5], s[6:7]162; CHECK-NEXT: s_cbranch_execz .LBB4_6163; CHECK-NEXT: ; %bb.5: ; %bb11164; CHECK-NEXT: v_mov_b32_e32 v0, 4.0165; CHECK-NEXT: buffer_store_dword v0, v0, s[0:3], 0 offen166; CHECK-NEXT: .LBB4_6: ; %Flow167; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]168; CHECK-NEXT: s_waitcnt vmcnt(0)169; CHECK-NEXT: s_setpc_b64 s[30:31]170bb:171 %tmp = load i32, ptr addrspace(4) @external_constant172 %tmp1 = icmp ne i32 %tmp, 0173 br i1 %tmp1, label %bb12, label %bb2174 175bb2:176 %ptr = load ptr, ptr addrspace(4) @const.ptr177 %tmp4 = load float, ptr %ptr, align 4178 %tmp5 = fcmp olt float %tmp4, 1.0179 %tmp6 = or i1 %tmp5, false180 br i1 %tmp6, label %bb8, label %bb7181 182bb7:183 br label %bb8184 185bb8:186 %tmp9 = phi i32 [ 0, %bb7 ], [ -1, %bb2 ]187 %tmp10 = icmp eq i32 %tmp9, 0188 br i1 %tmp10, label %bb11, label %bb12189 190bb11:191 store float 4.0, ptr addrspace(5) poison, align 4192 br label %bb12193 194bb12:195 ret void196}197 198define amdgpu_kernel void @break_loop(i32 %arg) {199; CHECK-LABEL: break_loop:200; CHECK: ; %bb.0: ; %bb201; CHECK-NEXT: s_load_dword s0, s[8:9], 0x0202; CHECK-NEXT: ; implicit-def: $sgpr2_sgpr3203; CHECK-NEXT: ; implicit-def: $vgpr1204; CHECK-NEXT: s_waitcnt lgkmcnt(0)205; CHECK-NEXT: v_subrev_u32_e32 v0, s0, v0206; CHECK-NEXT: s_mov_b64 s[0:1], 0207; CHECK-NEXT: s_branch .LBB5_2208; CHECK-NEXT: .LBB5_1: ; %Flow209; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1210; CHECK-NEXT: s_and_b64 s[4:5], exec, s[2:3]211; CHECK-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]212; CHECK-NEXT: s_andn2_b64 exec, exec, s[0:1]213; CHECK-NEXT: s_cbranch_execz .LBB5_4214; CHECK-NEXT: .LBB5_2: ; %bb1215; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1216; CHECK-NEXT: v_add_u32_e32 v1, 1, v1217; CHECK-NEXT: s_andn2_b64 s[2:3], s[2:3], exec218; CHECK-NEXT: s_and_b64 s[4:5], exec, -1219; CHECK-NEXT: v_cmp_le_i32_e32 vcc, 0, v1220; CHECK-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]221; CHECK-NEXT: s_cbranch_vccnz .LBB5_1222; CHECK-NEXT: ; %bb.3: ; %bb4223; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1224; CHECK-NEXT: global_load_dword v2, v[0:1], off glc225; CHECK-NEXT: s_waitcnt vmcnt(0)226; CHECK-NEXT: s_andn2_b64 s[2:3], s[2:3], exec227; CHECK-NEXT: v_cmp_ge_i32_e32 vcc, v0, v2228; CHECK-NEXT: s_and_b64 s[4:5], exec, vcc229; CHECK-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]230; CHECK-NEXT: s_branch .LBB5_1231; CHECK-NEXT: .LBB5_4: ; %bb9232; CHECK-NEXT: s_endpgm233bb:234 %id = call i32 @llvm.amdgcn.workitem.id.x()235 %tmp = sub i32 %id, %arg236 br label %bb1237 238bb1:239 %lsr.iv = phi i32 [ poison, %bb ], [ %lsr.iv.next, %bb4 ]240 %lsr.iv.next = add i32 %lsr.iv, 1241 %cmp0 = icmp slt i32 %lsr.iv.next, 0242 br i1 %cmp0, label %bb4, label %bb9243 244bb4:245 %load = load volatile i32, ptr addrspace(1) poison, align 4246 %cmp1 = icmp slt i32 %tmp, %load247 br i1 %cmp1, label %bb1, label %bb9248 249bb9:250 ret void251}252 253declare i32 @llvm.amdgcn.workitem.id.x()254