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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; Denormal mode shouldn't matter for f16, check with and without flushing.3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GFX6,GFX6-IEEE %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX6,GFX6-FLUSH %s5 6; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GFX89,GFX8,GFX8-IEEE %s7; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX89,GFX8,GFX8-FLUSH %s8 9; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GFX89,GFX9,GFX9-IEEE %s10; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX89,GFX9,GFX9-FLUSH %s11 12; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10,GFX10-IEEE %s13; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10,GFX10-FLUSH %s14 15; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-IEEE %s16; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FLUSH %s17 18define half @v_fdiv_f16(half %a, half %b) {19; GFX6-IEEE-LABEL: v_fdiv_f16:20; GFX6-IEEE: ; %bb.0:21; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)22; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v023; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v124; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v025; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v226; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v027; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.028; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v329; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v330; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v431; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v532; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v433; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v534; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v035; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v036; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]37;38; GFX6-FLUSH-LABEL: v_fdiv_f16:39; GFX6-FLUSH: ; %bb.0:40; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)41; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v042; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v143; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v044; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v245; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v046; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 347; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.048; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v349; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v350; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v451; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v552; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v453; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 054; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v555; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v056; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 057; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v058; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]59;60; GFX8-IEEE-LABEL: v_fdiv_f16:61; GFX8-IEEE: ; %bb.0:62; GFX8-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)63; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v164; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v065; GFX8-IEEE-NEXT: v_rcp_f32_e32 v4, v266; GFX8-IEEE-NEXT: v_mul_f32_e32 v5, v3, v467; GFX8-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v568; GFX8-IEEE-NEXT: v_add_f32_e32 v6, v6, v369; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v470; GFX8-IEEE-NEXT: v_add_f32_e32 v5, v6, v571; GFX8-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v572; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v373; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v2, v474; GFX8-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v275; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v576; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v277; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v078; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]79;80; GFX8-FLUSH-LABEL: v_fdiv_f16:81; GFX8-FLUSH: ; %bb.0:82; GFX8-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)83; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v184; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v085; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v4, v286; GFX8-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v487; GFX8-FLUSH-NEXT: v_mad_f32 v6, -v2, v5, v388; GFX8-FLUSH-NEXT: v_mac_f32_e32 v5, v6, v489; GFX8-FLUSH-NEXT: v_mad_f32 v2, -v2, v5, v390; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v491; GFX8-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v292; GFX8-FLUSH-NEXT: v_add_f32_e32 v2, v2, v593; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v294; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v095; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]96;97; GFX9-IEEE-LABEL: v_fdiv_f16:98; GFX9-IEEE: ; %bb.0:99; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)100; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v1101; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v0102; GFX9-IEEE-NEXT: v_rcp_f32_e32 v4, v2103; GFX9-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4104; GFX9-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v5105; GFX9-IEEE-NEXT: v_add_f32_e32 v6, v6, v3106; GFX9-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4107; GFX9-IEEE-NEXT: v_add_f32_e32 v5, v6, v5108; GFX9-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v5109; GFX9-IEEE-NEXT: v_add_f32_e32 v2, v2, v3110; GFX9-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4111; GFX9-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2112; GFX9-IEEE-NEXT: v_add_f32_e32 v2, v2, v5113; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2114; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v0115; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31]116;117; GFX9-FLUSH-LABEL: v_fdiv_f16:118; GFX9-FLUSH: ; %bb.0:119; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)120; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v1121; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v0122; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v2123; GFX9-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v2124; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]125; GFX9-FLUSH-NEXT: v_mac_f32_e32 v3, v4, v2126; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]127; GFX9-FLUSH-NEXT: v_mul_f32_e32 v2, v4, v2128; GFX9-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2129; GFX9-FLUSH-NEXT: v_add_f32_e32 v2, v2, v3130; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2131; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0132; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31]133;134; GFX10-IEEE-LABEL: v_fdiv_f16:135; GFX10-IEEE: ; %bb.0:136; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)137; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v1138; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v0139; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2140; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3141; GFX10-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v5142; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v6, v4143; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v3144; GFX10-IEEE-NEXT: v_add_f32_e32 v5, v6, v5145; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v5146; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v4147; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v3148; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2149; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v5150; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2151; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v0152; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]153;154; GFX10-FLUSH-LABEL: v_fdiv_f16:155; GFX10-FLUSH: ; %bb.0:156; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)157; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v1158; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v0159; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2160; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3161; GFX10-FLUSH-NEXT: v_mad_f32 v6, -v2, v5, v4162; GFX10-FLUSH-NEXT: v_mac_f32_e32 v5, v6, v3163; GFX10-FLUSH-NEXT: v_mad_f32 v2, -v2, v5, v4164; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v3165; GFX10-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2166; GFX10-FLUSH-NEXT: v_add_f32_e32 v2, v2, v5167; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2168; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0169; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]170;171; GFX11-LABEL: v_fdiv_f16:172; GFX11: ; %bb.0:173; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)174; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1175; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v0176; GFX11-NEXT: v_rcp_f32_e32 v2, v2177; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)178; GFX11-NEXT: v_mul_f32_e32 v3, v3, v2179; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]180; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v2181; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]182; GFX11-NEXT: v_mul_f32_e32 v2, v4, v2183; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v2184; GFX11-NEXT: v_add_f32_e32 v2, v2, v3185; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2186; GFX11-NEXT: v_div_fixup_f16 v0, v2, v1, v0187; GFX11-NEXT: s_setpc_b64 s[30:31]188 %fdiv = fdiv half %a, %b189 ret half %fdiv190}191 192define half @v_fdiv_f16_afn(half %a, half %b) {193; GFX6-LABEL: v_fdiv_f16_afn:194; GFX6: ; %bb.0:195; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)196; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1197; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0198; GFX6-NEXT: v_rcp_f32_e32 v1, v1199; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1200; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0201; GFX6-NEXT: s_setpc_b64 s[30:31]202;203; GFX89-LABEL: v_fdiv_f16_afn:204; GFX89: ; %bb.0:205; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)206; GFX89-NEXT: v_rcp_f16_e32 v1, v1207; GFX89-NEXT: v_mul_f16_e32 v0, v0, v1208; GFX89-NEXT: s_setpc_b64 s[30:31]209;210; GFX10-LABEL: v_fdiv_f16_afn:211; GFX10: ; %bb.0:212; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)213; GFX10-NEXT: v_rcp_f16_e32 v1, v1214; GFX10-NEXT: v_mul_f16_e32 v0, v0, v1215; GFX10-NEXT: s_setpc_b64 s[30:31]216;217; GFX11-LABEL: v_fdiv_f16_afn:218; GFX11: ; %bb.0:219; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)220; GFX11-NEXT: v_rcp_f16_e32 v1, v1221; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)222; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1223; GFX11-NEXT: s_setpc_b64 s[30:31]224 %fdiv = fdiv afn half %a, %b225 ret half %fdiv226}227 228define half @v_fdiv_f16_ulp25(half %a, half %b) {229; GFX6-IEEE-LABEL: v_fdiv_f16_ulp25:230; GFX6-IEEE: ; %bb.0:231; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)232; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0233; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1234; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0235; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2236; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0237; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0238; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3239; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3240; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4241; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5242; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4243; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5244; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0245; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0246; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]247;248; GFX6-FLUSH-LABEL: v_fdiv_f16_ulp25:249; GFX6-FLUSH: ; %bb.0:250; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)251; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0252; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1253; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0254; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2255; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0256; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3257; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0258; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3259; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3260; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4261; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5262; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4263; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0264; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5265; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0266; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0267; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0268; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]269;270; GFX8-IEEE-LABEL: v_fdiv_f16_ulp25:271; GFX8-IEEE: ; %bb.0:272; GFX8-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)273; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v1274; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v0275; GFX8-IEEE-NEXT: v_rcp_f32_e32 v4, v2276; GFX8-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4277; GFX8-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v5278; GFX8-IEEE-NEXT: v_add_f32_e32 v6, v6, v3279; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4280; GFX8-IEEE-NEXT: v_add_f32_e32 v5, v6, v5281; GFX8-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v5282; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v3283; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4284; GFX8-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2285; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v5286; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2287; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v0288; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]289;290; GFX8-FLUSH-LABEL: v_fdiv_f16_ulp25:291; GFX8-FLUSH: ; %bb.0:292; GFX8-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)293; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v1294; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v0295; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v4, v2296; GFX8-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4297; GFX8-FLUSH-NEXT: v_mad_f32 v6, -v2, v5, v3298; GFX8-FLUSH-NEXT: v_mac_f32_e32 v5, v6, v4299; GFX8-FLUSH-NEXT: v_mad_f32 v2, -v2, v5, v3300; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4301; GFX8-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2302; GFX8-FLUSH-NEXT: v_add_f32_e32 v2, v2, v5303; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2304; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0305; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]306;307; GFX9-IEEE-LABEL: v_fdiv_f16_ulp25:308; GFX9-IEEE: ; %bb.0:309; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)310; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v1311; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v0312; GFX9-IEEE-NEXT: v_rcp_f32_e32 v4, v2313; GFX9-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4314; GFX9-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v5315; GFX9-IEEE-NEXT: v_add_f32_e32 v6, v6, v3316; GFX9-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4317; GFX9-IEEE-NEXT: v_add_f32_e32 v5, v6, v5318; GFX9-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v5319; GFX9-IEEE-NEXT: v_add_f32_e32 v2, v2, v3320; GFX9-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4321; GFX9-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2322; GFX9-IEEE-NEXT: v_add_f32_e32 v2, v2, v5323; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2324; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v0325; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31]326;327; GFX9-FLUSH-LABEL: v_fdiv_f16_ulp25:328; GFX9-FLUSH: ; %bb.0:329; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)330; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v1331; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v0332; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v2333; GFX9-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v2334; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]335; GFX9-FLUSH-NEXT: v_mac_f32_e32 v3, v4, v2336; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]337; GFX9-FLUSH-NEXT: v_mul_f32_e32 v2, v4, v2338; GFX9-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2339; GFX9-FLUSH-NEXT: v_add_f32_e32 v2, v2, v3340; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2341; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0342; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31]343;344; GFX10-IEEE-LABEL: v_fdiv_f16_ulp25:345; GFX10-IEEE: ; %bb.0:346; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)347; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v1348; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v0349; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2350; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3351; GFX10-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v5352; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v6, v4353; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v3354; GFX10-IEEE-NEXT: v_add_f32_e32 v5, v6, v5355; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v5356; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v4357; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v3358; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2359; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v5360; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2361; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v0362; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]363;364; GFX10-FLUSH-LABEL: v_fdiv_f16_ulp25:365; GFX10-FLUSH: ; %bb.0:366; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)367; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v1368; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v0369; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2370; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3371; GFX10-FLUSH-NEXT: v_mad_f32 v6, -v2, v5, v4372; GFX10-FLUSH-NEXT: v_mac_f32_e32 v5, v6, v3373; GFX10-FLUSH-NEXT: v_mad_f32 v2, -v2, v5, v4374; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v3375; GFX10-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2376; GFX10-FLUSH-NEXT: v_add_f32_e32 v2, v2, v5377; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2378; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0379; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]380;381; GFX11-LABEL: v_fdiv_f16_ulp25:382; GFX11: ; %bb.0:383; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)384; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1385; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v0386; GFX11-NEXT: v_rcp_f32_e32 v2, v2387; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)388; GFX11-NEXT: v_mul_f32_e32 v3, v3, v2389; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]390; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v2391; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1]392; GFX11-NEXT: v_mul_f32_e32 v2, v4, v2393; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v2394; GFX11-NEXT: v_add_f32_e32 v2, v2, v3395; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2396; GFX11-NEXT: v_div_fixup_f16 v0, v2, v1, v0397; GFX11-NEXT: s_setpc_b64 s[30:31]398 %fdiv = fdiv half %a, %b399 ret half %fdiv400}401 402define half @v_neg_rcp_f16(half %x) {403; GFX6-IEEE-LABEL: v_neg_rcp_f16:404; GFX6-IEEE: ; %bb.0:405; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)406; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0407; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.0408; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v1409; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.0410; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0411; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v2412; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2413; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3414; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v4415; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3416; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4417; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, -1.0418; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0419; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]420;421; GFX6-FLUSH-LABEL: v_neg_rcp_f16:422; GFX6-FLUSH: ; %bb.0:423; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)424; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0425; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.0426; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v1427; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.0428; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3429; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0430; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v2431; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2432; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3433; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v4434; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3435; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0436; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4437; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, -1.0438; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0439; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0440; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]441;442; GFX89-LABEL: v_neg_rcp_f16:443; GFX89: ; %bb.0:444; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)445; GFX89-NEXT: v_rcp_f16_e64 v0, -v0446; GFX89-NEXT: s_setpc_b64 s[30:31]447;448; GFX10PLUS-LABEL: v_neg_rcp_f16:449; GFX10PLUS: ; %bb.0:450; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)451; GFX10PLUS-NEXT: v_rcp_f16_e64 v0, -v0452; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]453 %fdiv = fdiv half -1.0, %x454 ret half %fdiv455}456 457define half @v_rcp_f16(half %x) {458; GFX6-IEEE-LABEL: v_rcp_f16:459; GFX6-IEEE: ; %bb.0:460; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)461; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0462; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0463; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v1464; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0465; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0466; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v2467; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2468; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3469; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v4470; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3471; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4472; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0473; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0474; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]475;476; GFX6-FLUSH-LABEL: v_rcp_f16:477; GFX6-FLUSH: ; %bb.0:478; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)479; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0480; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0481; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v1482; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0483; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3484; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0485; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v2486; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2487; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3488; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v4489; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3490; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0491; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4492; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0493; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0494; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0495; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]496;497; GFX89-LABEL: v_rcp_f16:498; GFX89: ; %bb.0:499; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)500; GFX89-NEXT: v_rcp_f16_e32 v0, v0501; GFX89-NEXT: s_setpc_b64 s[30:31]502;503; GFX10PLUS-LABEL: v_rcp_f16:504; GFX10PLUS: ; %bb.0:505; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)506; GFX10PLUS-NEXT: v_rcp_f16_e32 v0, v0507; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]508 %fdiv = fdiv half 1.0, %x509 ret half %fdiv510}511 512define half @v_rcp_f16_arcp(half %x) {513; GFX6-IEEE-LABEL: v_rcp_f16_arcp:514; GFX6-IEEE: ; %bb.0:515; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)516; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0517; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0518; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v1519; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0520; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0521; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v2522; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2523; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3524; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v4525; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3526; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4527; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0528; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0529; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]530;531; GFX6-FLUSH-LABEL: v_rcp_f16_arcp:532; GFX6-FLUSH: ; %bb.0:533; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)534; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0535; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0536; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v1537; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0538; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3539; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0540; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v2541; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2542; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3543; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v4544; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3545; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0546; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4547; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0548; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0549; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0550; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]551;552; GFX89-LABEL: v_rcp_f16_arcp:553; GFX89: ; %bb.0:554; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)555; GFX89-NEXT: v_rcp_f16_e32 v0, v0556; GFX89-NEXT: s_setpc_b64 s[30:31]557;558; GFX10PLUS-LABEL: v_rcp_f16_arcp:559; GFX10PLUS: ; %bb.0:560; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)561; GFX10PLUS-NEXT: v_rcp_f16_e32 v0, v0562; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]563 %fdiv = fdiv arcp half 1.0, %x564 ret half %fdiv565}566 567define half @v_rcp_f16_arcp_afn(half %x) {568; GFX6-LABEL: v_rcp_f16_arcp_afn:569; GFX6: ; %bb.0:570; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)571; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0572; GFX6-NEXT: v_rcp_f32_e32 v0, v0573; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0574; GFX6-NEXT: s_setpc_b64 s[30:31]575;576; GFX89-LABEL: v_rcp_f16_arcp_afn:577; GFX89: ; %bb.0:578; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)579; GFX89-NEXT: v_rcp_f16_e32 v0, v0580; GFX89-NEXT: s_setpc_b64 s[30:31]581;582; GFX10PLUS-LABEL: v_rcp_f16_arcp_afn:583; GFX10PLUS: ; %bb.0:584; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)585; GFX10PLUS-NEXT: v_rcp_f16_e32 v0, v0586; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]587 %fdiv = fdiv arcp afn half 1.0, %x588 ret half %fdiv589}590 591define half @v_rcp_f16_ulp25(half %x) {592; GFX6-IEEE-LABEL: v_rcp_f16_ulp25:593; GFX6-IEEE: ; %bb.0:594; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)595; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0596; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0597; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v1598; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0599; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0600; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v2601; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2602; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3603; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v4604; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3605; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4606; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0607; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0608; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]609;610; GFX6-FLUSH-LABEL: v_rcp_f16_ulp25:611; GFX6-FLUSH: ; %bb.0:612; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)613; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0614; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0615; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v1616; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0617; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3618; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0619; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v2620; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2621; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3622; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v4623; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3624; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0625; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4626; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0627; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0628; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0629; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]630;631; GFX89-LABEL: v_rcp_f16_ulp25:632; GFX89: ; %bb.0:633; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)634; GFX89-NEXT: v_rcp_f16_e32 v0, v0635; GFX89-NEXT: s_setpc_b64 s[30:31]636;637; GFX10PLUS-LABEL: v_rcp_f16_ulp25:638; GFX10PLUS: ; %bb.0:639; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)640; GFX10PLUS-NEXT: v_rcp_f16_e32 v0, v0641; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]642 %fdiv = fdiv half 1.0, %x643 ret half %fdiv644}645 646define half @v_fdiv_f16_afn_ulp25(half %a, half %b) {647; GFX6-LABEL: v_fdiv_f16_afn_ulp25:648; GFX6: ; %bb.0:649; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)650; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1651; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0652; GFX6-NEXT: v_rcp_f32_e32 v1, v1653; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1654; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0655; GFX6-NEXT: s_setpc_b64 s[30:31]656;657; GFX89-LABEL: v_fdiv_f16_afn_ulp25:658; GFX89: ; %bb.0:659; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)660; GFX89-NEXT: v_rcp_f16_e32 v1, v1661; GFX89-NEXT: v_mul_f16_e32 v0, v0, v1662; GFX89-NEXT: s_setpc_b64 s[30:31]663;664; GFX10-LABEL: v_fdiv_f16_afn_ulp25:665; GFX10: ; %bb.0:666; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)667; GFX10-NEXT: v_rcp_f16_e32 v1, v1668; GFX10-NEXT: v_mul_f16_e32 v0, v0, v1669; GFX10-NEXT: s_setpc_b64 s[30:31]670;671; GFX11-LABEL: v_fdiv_f16_afn_ulp25:672; GFX11: ; %bb.0:673; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)674; GFX11-NEXT: v_rcp_f16_e32 v1, v1675; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)676; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1677; GFX11-NEXT: s_setpc_b64 s[30:31]678 %fdiv = fdiv afn half %a, %b679 ret half %fdiv680}681 682define half @v_fdiv_f16_arcp_ulp25(half %a, half %b) {683; GFX6-IEEE-LABEL: v_fdiv_f16_arcp_ulp25:684; GFX6-IEEE: ; %bb.0:685; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)686; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0687; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1688; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0689; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2690; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0691; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0692; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3693; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3694; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4695; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5696; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4697; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5698; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0699; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0700; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]701;702; GFX6-FLUSH-LABEL: v_fdiv_f16_arcp_ulp25:703; GFX6-FLUSH: ; %bb.0:704; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)705; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0706; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1707; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0708; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2709; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0710; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3711; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0712; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3713; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3714; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4715; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5716; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4717; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0718; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5719; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0720; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0721; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0722; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]723;724; GFX89-LABEL: v_fdiv_f16_arcp_ulp25:725; GFX89: ; %bb.0:726; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)727; GFX89-NEXT: v_rcp_f16_e32 v1, v1728; GFX89-NEXT: v_mul_f16_e32 v0, v0, v1729; GFX89-NEXT: s_setpc_b64 s[30:31]730;731; GFX10-LABEL: v_fdiv_f16_arcp_ulp25:732; GFX10: ; %bb.0:733; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)734; GFX10-NEXT: v_rcp_f16_e32 v1, v1735; GFX10-NEXT: v_mul_f16_e32 v0, v0, v1736; GFX10-NEXT: s_setpc_b64 s[30:31]737;738; GFX11-LABEL: v_fdiv_f16_arcp_ulp25:739; GFX11: ; %bb.0:740; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)741; GFX11-NEXT: v_rcp_f16_e32 v1, v1742; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)743; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1744; GFX11-NEXT: s_setpc_b64 s[30:31]745 %fdiv = fdiv arcp half %a, %b746 ret half %fdiv747}748 749define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) {750; GFX6-IEEE-LABEL: v_fdiv_v2f16:751; GFX6-IEEE: ; %bb.0:752; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)753; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v0754; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v2755; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v1756; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v3757; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0758; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4759; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0760; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0761; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5762; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5763; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6764; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7765; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6766; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7767; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0768; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1769; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v2770; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1771; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0772; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0773; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v4774; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v4775; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v6, v5776; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6777; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v5778; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6779; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v1780; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1781; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]782;783; GFX6-FLUSH-LABEL: v_fdiv_v2f16:784; GFX6-FLUSH: ; %bb.0:785; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)786; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v0787; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v2788; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0789; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4790; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0791; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3792; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0793; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5794; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5795; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6796; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7797; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6798; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0799; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v1800; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v3801; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7802; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0803; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0804; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0805; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v1806; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v2807; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v1808; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3809; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v4, 1.0810; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v4811; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v4812; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v5813; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6814; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v5815; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0816; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v6817; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1818; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1819; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]820;821; GFX8-IEEE-LABEL: v_fdiv_v2f16:822; GFX8-IEEE: ; %bb.0:823; GFX8-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)824; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v1825; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v0826; GFX8-IEEE-NEXT: v_lshrrev_b32_e32 v6, 16, v1827; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v8, v6828; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v2829; GFX8-IEEE-NEXT: v_lshrrev_b32_e32 v3, 16, v0830; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v7, v3831; GFX8-IEEE-NEXT: v_mul_f32_e32 v9, v4, v5832; GFX8-IEEE-NEXT: v_mul_f32_e64 v10, -v2, v9833; GFX8-IEEE-NEXT: v_add_f32_e32 v10, v10, v4834; GFX8-IEEE-NEXT: v_mul_f32_e32 v10, v10, v5835; GFX8-IEEE-NEXT: v_add_f32_e32 v9, v10, v9836; GFX8-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v9837; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v4838; GFX8-IEEE-NEXT: v_rcp_f32_e32 v4, v8839; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v2, v5840; GFX8-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2841; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v9842; GFX8-IEEE-NEXT: v_mul_f32_e32 v5, v7, v4843; GFX8-IEEE-NEXT: v_mul_f32_e64 v9, -v8, v5844; GFX8-IEEE-NEXT: v_add_f32_e32 v9, v9, v7845; GFX8-IEEE-NEXT: v_mul_f32_e32 v9, v9, v4846; GFX8-IEEE-NEXT: v_add_f32_e32 v5, v9, v5847; GFX8-IEEE-NEXT: v_mul_f32_e64 v8, -v8, v5848; GFX8-IEEE-NEXT: v_add_f32_e32 v7, v8, v7849; GFX8-IEEE-NEXT: v_mul_f32_e32 v4, v7, v4850; GFX8-IEEE-NEXT: v_and_b32_e32 v4, 0xff800000, v4851; GFX8-IEEE-NEXT: v_add_f32_e32 v4, v4, v5852; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2853; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v4, v4854; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v0855; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v4, v6, v3856; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1857; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1858; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]859;860; GFX8-FLUSH-LABEL: v_fdiv_v2f16:861; GFX8-FLUSH: ; %bb.0:862; GFX8-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)863; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v1864; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v0865; GFX8-FLUSH-NEXT: v_lshrrev_b32_e32 v6, 16, v1866; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v8, v6867; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v2868; GFX8-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v0869; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v7, v3870; GFX8-FLUSH-NEXT: v_mul_f32_e32 v9, v4, v5871; GFX8-FLUSH-NEXT: v_mad_f32 v10, -v2, v9, v4872; GFX8-FLUSH-NEXT: v_mac_f32_e32 v9, v10, v5873; GFX8-FLUSH-NEXT: v_mad_f32 v2, -v2, v9, v4874; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v4, v8875; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v5876; GFX8-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2877; GFX8-FLUSH-NEXT: v_add_f32_e32 v2, v2, v9878; GFX8-FLUSH-NEXT: v_mul_f32_e32 v5, v7, v4879; GFX8-FLUSH-NEXT: v_mad_f32 v9, -v8, v5, v7880; GFX8-FLUSH-NEXT: v_mac_f32_e32 v5, v9, v4881; GFX8-FLUSH-NEXT: v_mad_f32 v7, -v8, v5, v7882; GFX8-FLUSH-NEXT: v_mul_f32_e32 v4, v7, v4883; GFX8-FLUSH-NEXT: v_and_b32_e32 v4, 0xff800000, v4884; GFX8-FLUSH-NEXT: v_add_f32_e32 v4, v4, v5885; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2886; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v4887; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0888; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v6, v3889; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1890; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1891; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]892;893; GFX9-IEEE-LABEL: v_fdiv_v2f16:894; GFX9-IEEE: ; %bb.0:895; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)896; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v1897; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v0898; GFX9-IEEE-NEXT: v_lshrrev_b32_e32 v6, 16, v1899; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v8, v6900; GFX9-IEEE-NEXT: v_rcp_f32_e32 v5, v2901; GFX9-IEEE-NEXT: v_lshrrev_b32_e32 v3, 16, v0902; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v7, v3903; GFX9-IEEE-NEXT: v_mul_f32_e32 v9, v4, v5904; GFX9-IEEE-NEXT: v_mul_f32_e64 v10, -v2, v9905; GFX9-IEEE-NEXT: v_add_f32_e32 v10, v10, v4906; GFX9-IEEE-NEXT: v_mul_f32_e32 v10, v10, v5907; GFX9-IEEE-NEXT: v_add_f32_e32 v9, v10, v9908; GFX9-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v9909; GFX9-IEEE-NEXT: v_add_f32_e32 v2, v2, v4910; GFX9-IEEE-NEXT: v_rcp_f32_e32 v4, v8911; GFX9-IEEE-NEXT: v_mul_f32_e32 v2, v2, v5912; GFX9-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2913; GFX9-IEEE-NEXT: v_add_f32_e32 v2, v2, v9914; GFX9-IEEE-NEXT: v_mul_f32_e32 v5, v7, v4915; GFX9-IEEE-NEXT: v_mul_f32_e64 v9, -v8, v5916; GFX9-IEEE-NEXT: v_add_f32_e32 v9, v9, v7917; GFX9-IEEE-NEXT: v_mul_f32_e32 v9, v9, v4918; GFX9-IEEE-NEXT: v_add_f32_e32 v5, v9, v5919; GFX9-IEEE-NEXT: v_mul_f32_e64 v8, -v8, v5920; GFX9-IEEE-NEXT: v_add_f32_e32 v7, v8, v7921; GFX9-IEEE-NEXT: v_mul_f32_e32 v4, v7, v4922; GFX9-IEEE-NEXT: v_and_b32_e32 v4, 0xff800000, v4923; GFX9-IEEE-NEXT: v_add_f32_e32 v4, v4, v5924; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2925; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v4, v4926; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v0927; GFX9-IEEE-NEXT: v_div_fixup_f16 v1, v4, v6, v3928; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v0, v1929; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31]930;931; GFX9-FLUSH-LABEL: v_fdiv_v2f16:932; GFX9-FLUSH: ; %bb.0:933; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)934; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v1935; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v0936; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v5, 16, v1937; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v7, v5938; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v2939; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v0940; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v6, v3941; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v7, v7942; GFX9-FLUSH-NEXT: v_mul_f32_e32 v4, v4, v2943; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v4, v0 op_sel_hi:[1,0,1]944; GFX9-FLUSH-NEXT: v_mac_f32_e32 v4, v8, v2945; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v4, v0 op_sel_hi:[1,0,1]946; GFX9-FLUSH-NEXT: v_mul_f32_e32 v2, v8, v2947; GFX9-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2948; GFX9-FLUSH-NEXT: v_add_f32_e32 v2, v2, v4949; GFX9-FLUSH-NEXT: v_mul_f32_e32 v4, v6, v7950; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v4, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]951; GFX9-FLUSH-NEXT: v_mac_f32_e32 v4, v6, v7952; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v4, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]953; GFX9-FLUSH-NEXT: v_mul_f32_e32 v6, v6, v7954; GFX9-FLUSH-NEXT: v_and_b32_e32 v6, 0xff800000, v6955; GFX9-FLUSH-NEXT: v_add_f32_e32 v4, v6, v4956; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2957; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v4958; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0959; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v5, v3960; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1961; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31]962;963; GFX10-IEEE-LABEL: v_fdiv_v2f16:964; GFX10-IEEE: ; %bb.0:965; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)966; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v1967; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1968; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v5, 16, v0969; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v8, v0970; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v2971; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v3972; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v9, v5973; GFX10-IEEE-NEXT: v_rcp_f32_e32 v7, v4974; GFX10-IEEE-NEXT: v_mul_f32_e32 v10, v8, v6975; GFX10-IEEE-NEXT: v_mul_f32_e32 v11, v9, v7976; GFX10-IEEE-NEXT: v_mul_f32_e64 v12, -v3, v10977; GFX10-IEEE-NEXT: v_mul_f32_e64 v13, -v4, v11978; GFX10-IEEE-NEXT: v_add_f32_e32 v12, v12, v8979; GFX10-IEEE-NEXT: v_add_f32_e32 v13, v13, v9980; GFX10-IEEE-NEXT: v_mul_f32_e32 v12, v12, v6981; GFX10-IEEE-NEXT: v_mul_f32_e32 v13, v13, v7982; GFX10-IEEE-NEXT: v_add_f32_e32 v10, v12, v10983; GFX10-IEEE-NEXT: v_add_f32_e32 v11, v13, v11984; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v10985; GFX10-IEEE-NEXT: v_mul_f32_e64 v4, -v4, v11986; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v8987; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v9988; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v6989; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v4, v7990; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3991; GFX10-IEEE-NEXT: v_and_b32_e32 v4, 0xff800000, v4992; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v10993; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v11994; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3995; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v4, v4996; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v3, v1, v0997; GFX10-IEEE-NEXT: v_div_fixup_f16 v1, v4, v2, v5998; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v0, v1999; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]1000;1001; GFX10-FLUSH-LABEL: v_fdiv_v2f16:1002; GFX10-FLUSH: ; %bb.0:1003; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1004; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v11005; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v11006; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v5, 16, v01007; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v8, v01008; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v21009; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v6, v31010; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v9, v51011; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v7, v41012; GFX10-FLUSH-NEXT: v_mul_f32_e32 v10, v8, v61013; GFX10-FLUSH-NEXT: v_mul_f32_e32 v11, v9, v71014; GFX10-FLUSH-NEXT: v_mad_f32 v12, -v3, v10, v81015; GFX10-FLUSH-NEXT: v_mad_f32 v13, -v4, v11, v91016; GFX10-FLUSH-NEXT: v_mac_f32_e32 v10, v12, v61017; GFX10-FLUSH-NEXT: v_mac_f32_e32 v11, v13, v71018; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v10, v81019; GFX10-FLUSH-NEXT: v_mad_f32 v4, -v4, v11, v91020; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v61021; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v4, v71022; GFX10-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v31023; GFX10-FLUSH-NEXT: v_and_b32_e32 v4, 0xff800000, v41024; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v101025; GFX10-FLUSH-NEXT: v_add_f32_e32 v4, v4, v111026; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v31027; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v41028; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v1, v01029; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v2, v51030; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v11031; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]1032;1033; GFX11-LABEL: v_fdiv_v2f16:1034; GFX11: ; %bb.0:1035; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1036; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v11037; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v11038; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v01039; GFX11-NEXT: v_cvt_f32_f16_e32 v6, v01040; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v21041; GFX11-NEXT: v_rcp_f32_e32 v3, v31042; GFX11-NEXT: v_cvt_f32_f16_e32 v7, v51043; GFX11-NEXT: v_rcp_f32_e32 v4, v41044; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1045; GFX11-NEXT: v_dual_mul_f32 v6, v6, v3 :: v_dual_mul_f32 v7, v7, v41046; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]1047; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]1048; GFX11-NEXT: v_dual_fmac_f32 v6, v8, v3 :: v_dual_fmac_f32 v7, v9, v41049; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]1050; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]1051; GFX11-NEXT: v_dual_mul_f32 v3, v8, v3 :: v_dual_mul_f32 v4, v9, v41052; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v31053; GFX11-NEXT: v_dual_add_f32 v3, v3, v6 :: v_dual_and_b32 v4, 0xff800000, v41054; GFX11-NEXT: v_add_f32_e32 v4, v4, v71055; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v31056; GFX11-NEXT: v_cvt_f16_f32_e32 v4, v41057; GFX11-NEXT: v_div_fixup_f16 v0, v3, v1, v01058; GFX11-NEXT: v_div_fixup_f16 v1, v4, v2, v51059; GFX11-NEXT: v_pack_b32_f16 v0, v0, v11060; GFX11-NEXT: s_setpc_b64 s[30:31]1061 %fdiv = fdiv <2 x half> %a, %b1062 ret <2 x half> %fdiv1063}1064 1065define <2 x half> @v_fdiv_v2f16_afn(<2 x half> %a, <2 x half> %b) {1066; GFX6-LABEL: v_fdiv_v2f16_afn:1067; GFX6: ; %bb.0:1068; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1069; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v21070; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v31071; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v01072; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v11073; GFX6-NEXT: v_rcp_f32_e32 v2, v21074; GFX6-NEXT: v_rcp_f32_e32 v3, v31075; GFX6-NEXT: v_mul_f32_e32 v0, v0, v21076; GFX6-NEXT: v_mul_f32_e32 v1, v1, v31077; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v01078; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v11079; GFX6-NEXT: s_setpc_b64 s[30:31]1080;1081; GFX8-LABEL: v_fdiv_v2f16_afn:1082; GFX8: ; %bb.0:1083; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1084; GFX8-NEXT: v_rcp_f16_e32 v2, v11085; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_11086; GFX8-NEXT: v_mul_f16_e32 v2, v0, v21087; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1088; GFX8-NEXT: v_or_b32_e32 v0, v2, v01089; GFX8-NEXT: s_setpc_b64 s[30:31]1090;1091; GFX9-LABEL: v_fdiv_v2f16_afn:1092; GFX9: ; %bb.0:1093; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1094; GFX9-NEXT: v_rcp_f16_e32 v2, v11095; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_11096; GFX9-NEXT: v_mul_f16_e32 v2, v0, v21097; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1098; GFX9-NEXT: v_pack_b32_f16 v0, v2, v01099; GFX9-NEXT: s_setpc_b64 s[30:31]1100;1101; GFX10-LABEL: v_fdiv_v2f16_afn:1102; GFX10: ; %bb.0:1103; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1104; GFX10-NEXT: v_rcp_f16_e32 v2, v11105; GFX10-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_11106; GFX10-NEXT: v_mul_f16_e32 v2, v0, v21107; GFX10-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1108; GFX10-NEXT: v_pack_b32_f16 v0, v2, v01109; GFX10-NEXT: s_setpc_b64 s[30:31]1110;1111; GFX11-LABEL: v_fdiv_v2f16_afn:1112; GFX11: ; %bb.0:1113; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1114; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v11115; GFX11-NEXT: v_rcp_f16_e32 v1, v11116; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v01117; GFX11-NEXT: v_rcp_f16_e32 v2, v21118; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1119; GFX11-NEXT: v_mul_f16_e32 v0, v0, v11120; GFX11-NEXT: v_mul_f16_e32 v1, v3, v21121; GFX11-NEXT: v_pack_b32_f16 v0, v0, v11122; GFX11-NEXT: s_setpc_b64 s[30:31]1123 %fdiv = fdiv afn <2 x half> %a, %b1124 ret <2 x half> %fdiv1125}1126 1127define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) {1128; GFX6-IEEE-LABEL: v_fdiv_v2f16_ulp25:1129; GFX6-IEEE: ; %bb.0:1130; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1131; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v01132; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v21133; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v11134; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v31135; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v01136; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v41137; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v01138; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.01139; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v51140; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v51141; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v61142; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v71143; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v61144; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v71145; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v01146; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v11147; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v21148; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v11149; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v01150; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.01151; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v41152; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v41153; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v6, v51154; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v61155; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v51156; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v61157; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v11158; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v11159; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]1160;1161; GFX6-FLUSH-LABEL: v_fdiv_v2f16_ulp25:1162; GFX6-FLUSH: ; %bb.0:1163; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1164; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v01165; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v21166; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v01167; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v41168; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v01169; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31170; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.01171; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v51172; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v51173; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v61174; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v71175; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v61176; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01177; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v11178; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v31179; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v71180; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v01181; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 01182; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v01183; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v11184; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v21185; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v11186; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31187; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v4, 1.01188; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v41189; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v41190; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v51191; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v61192; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v51193; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01194; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v61195; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v11196; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v11197; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]1198;1199; GFX8-IEEE-LABEL: v_fdiv_v2f16_ulp25:1200; GFX8-IEEE: ; %bb.0:1201; GFX8-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1202; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v11203; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v01204; GFX8-IEEE-NEXT: v_lshrrev_b32_e32 v6, 16, v11205; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v8, v61206; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v21207; GFX8-IEEE-NEXT: v_lshrrev_b32_e32 v3, 16, v01208; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v7, v31209; GFX8-IEEE-NEXT: v_mul_f32_e32 v9, v4, v51210; GFX8-IEEE-NEXT: v_mul_f32_e64 v10, -v2, v91211; GFX8-IEEE-NEXT: v_add_f32_e32 v10, v10, v41212; GFX8-IEEE-NEXT: v_mul_f32_e32 v10, v10, v51213; GFX8-IEEE-NEXT: v_add_f32_e32 v9, v10, v91214; GFX8-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v91215; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v41216; GFX8-IEEE-NEXT: v_rcp_f32_e32 v4, v81217; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v2, v51218; GFX8-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v21219; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v91220; GFX8-IEEE-NEXT: v_mul_f32_e32 v5, v7, v41221; GFX8-IEEE-NEXT: v_mul_f32_e64 v9, -v8, v51222; GFX8-IEEE-NEXT: v_add_f32_e32 v9, v9, v71223; GFX8-IEEE-NEXT: v_mul_f32_e32 v9, v9, v41224; GFX8-IEEE-NEXT: v_add_f32_e32 v5, v9, v51225; GFX8-IEEE-NEXT: v_mul_f32_e64 v8, -v8, v51226; GFX8-IEEE-NEXT: v_add_f32_e32 v7, v8, v71227; GFX8-IEEE-NEXT: v_mul_f32_e32 v4, v7, v41228; GFX8-IEEE-NEXT: v_and_b32_e32 v4, 0xff800000, v41229; GFX8-IEEE-NEXT: v_add_f32_e32 v4, v4, v51230; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v21231; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v4, v41232; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v01233; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v4, v6, v31234; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v11235; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v11236; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]1237;1238; GFX8-FLUSH-LABEL: v_fdiv_v2f16_ulp25:1239; GFX8-FLUSH: ; %bb.0:1240; GFX8-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1241; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v11242; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v01243; GFX8-FLUSH-NEXT: v_lshrrev_b32_e32 v6, 16, v11244; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v8, v61245; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v21246; GFX8-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v01247; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v7, v31248; GFX8-FLUSH-NEXT: v_mul_f32_e32 v9, v4, v51249; GFX8-FLUSH-NEXT: v_mad_f32 v10, -v2, v9, v41250; GFX8-FLUSH-NEXT: v_mac_f32_e32 v9, v10, v51251; GFX8-FLUSH-NEXT: v_mad_f32 v2, -v2, v9, v41252; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v4, v81253; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v51254; GFX8-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v21255; GFX8-FLUSH-NEXT: v_add_f32_e32 v2, v2, v91256; GFX8-FLUSH-NEXT: v_mul_f32_e32 v5, v7, v41257; GFX8-FLUSH-NEXT: v_mad_f32 v9, -v8, v5, v71258; GFX8-FLUSH-NEXT: v_mac_f32_e32 v5, v9, v41259; GFX8-FLUSH-NEXT: v_mad_f32 v7, -v8, v5, v71260; GFX8-FLUSH-NEXT: v_mul_f32_e32 v4, v7, v41261; GFX8-FLUSH-NEXT: v_and_b32_e32 v4, 0xff800000, v41262; GFX8-FLUSH-NEXT: v_add_f32_e32 v4, v4, v51263; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v21264; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v41265; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v01266; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v6, v31267; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v11268; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v11269; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]1270;1271; GFX9-IEEE-LABEL: v_fdiv_v2f16_ulp25:1272; GFX9-IEEE: ; %bb.0:1273; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1274; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v11275; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v01276; GFX9-IEEE-NEXT: v_lshrrev_b32_e32 v6, 16, v11277; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v8, v61278; GFX9-IEEE-NEXT: v_rcp_f32_e32 v5, v21279; GFX9-IEEE-NEXT: v_lshrrev_b32_e32 v3, 16, v01280; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v7, v31281; GFX9-IEEE-NEXT: v_mul_f32_e32 v9, v4, v51282; GFX9-IEEE-NEXT: v_mul_f32_e64 v10, -v2, v91283; GFX9-IEEE-NEXT: v_add_f32_e32 v10, v10, v41284; GFX9-IEEE-NEXT: v_mul_f32_e32 v10, v10, v51285; GFX9-IEEE-NEXT: v_add_f32_e32 v9, v10, v91286; GFX9-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v91287; GFX9-IEEE-NEXT: v_add_f32_e32 v2, v2, v41288; GFX9-IEEE-NEXT: v_rcp_f32_e32 v4, v81289; GFX9-IEEE-NEXT: v_mul_f32_e32 v2, v2, v51290; GFX9-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v21291; GFX9-IEEE-NEXT: v_add_f32_e32 v2, v2, v91292; GFX9-IEEE-NEXT: v_mul_f32_e32 v5, v7, v41293; GFX9-IEEE-NEXT: v_mul_f32_e64 v9, -v8, v51294; GFX9-IEEE-NEXT: v_add_f32_e32 v9, v9, v71295; GFX9-IEEE-NEXT: v_mul_f32_e32 v9, v9, v41296; GFX9-IEEE-NEXT: v_add_f32_e32 v5, v9, v51297; GFX9-IEEE-NEXT: v_mul_f32_e64 v8, -v8, v51298; GFX9-IEEE-NEXT: v_add_f32_e32 v7, v8, v71299; GFX9-IEEE-NEXT: v_mul_f32_e32 v4, v7, v41300; GFX9-IEEE-NEXT: v_and_b32_e32 v4, 0xff800000, v41301; GFX9-IEEE-NEXT: v_add_f32_e32 v4, v4, v51302; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v21303; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v4, v41304; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v01305; GFX9-IEEE-NEXT: v_div_fixup_f16 v1, v4, v6, v31306; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v0, v11307; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31]1308;1309; GFX9-FLUSH-LABEL: v_fdiv_v2f16_ulp25:1310; GFX9-FLUSH: ; %bb.0:1311; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1312; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v11313; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v01314; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v5, 16, v11315; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v7, v51316; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v21317; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v01318; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v6, v31319; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v7, v71320; GFX9-FLUSH-NEXT: v_mul_f32_e32 v4, v4, v21321; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v4, v0 op_sel_hi:[1,0,1]1322; GFX9-FLUSH-NEXT: v_mac_f32_e32 v4, v8, v21323; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v4, v0 op_sel_hi:[1,0,1]1324; GFX9-FLUSH-NEXT: v_mul_f32_e32 v2, v8, v21325; GFX9-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v21326; GFX9-FLUSH-NEXT: v_add_f32_e32 v2, v2, v41327; GFX9-FLUSH-NEXT: v_mul_f32_e32 v4, v6, v71328; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v4, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]1329; GFX9-FLUSH-NEXT: v_mac_f32_e32 v4, v6, v71330; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v4, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]1331; GFX9-FLUSH-NEXT: v_mul_f32_e32 v6, v6, v71332; GFX9-FLUSH-NEXT: v_and_b32_e32 v6, 0xff800000, v61333; GFX9-FLUSH-NEXT: v_add_f32_e32 v4, v6, v41334; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v21335; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v41336; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v01337; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v5, v31338; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v11339; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31]1340;1341; GFX10-IEEE-LABEL: v_fdiv_v2f16_ulp25:1342; GFX10-IEEE: ; %bb.0:1343; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1344; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v11345; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v11346; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v5, 16, v01347; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v8, v01348; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v21349; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v31350; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v9, v51351; GFX10-IEEE-NEXT: v_rcp_f32_e32 v7, v41352; GFX10-IEEE-NEXT: v_mul_f32_e32 v10, v8, v61353; GFX10-IEEE-NEXT: v_mul_f32_e32 v11, v9, v71354; GFX10-IEEE-NEXT: v_mul_f32_e64 v12, -v3, v101355; GFX10-IEEE-NEXT: v_mul_f32_e64 v13, -v4, v111356; GFX10-IEEE-NEXT: v_add_f32_e32 v12, v12, v81357; GFX10-IEEE-NEXT: v_add_f32_e32 v13, v13, v91358; GFX10-IEEE-NEXT: v_mul_f32_e32 v12, v12, v61359; GFX10-IEEE-NEXT: v_mul_f32_e32 v13, v13, v71360; GFX10-IEEE-NEXT: v_add_f32_e32 v10, v12, v101361; GFX10-IEEE-NEXT: v_add_f32_e32 v11, v13, v111362; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v101363; GFX10-IEEE-NEXT: v_mul_f32_e64 v4, -v4, v111364; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v81365; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v91366; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v61367; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v4, v71368; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v31369; GFX10-IEEE-NEXT: v_and_b32_e32 v4, 0xff800000, v41370; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v101371; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v111372; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v31373; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v4, v41374; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v3, v1, v01375; GFX10-IEEE-NEXT: v_div_fixup_f16 v1, v4, v2, v51376; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v0, v11377; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]1378;1379; GFX10-FLUSH-LABEL: v_fdiv_v2f16_ulp25:1380; GFX10-FLUSH: ; %bb.0:1381; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1382; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v11383; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v11384; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v5, 16, v01385; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v8, v01386; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v21387; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v6, v31388; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v9, v51389; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v7, v41390; GFX10-FLUSH-NEXT: v_mul_f32_e32 v10, v8, v61391; GFX10-FLUSH-NEXT: v_mul_f32_e32 v11, v9, v71392; GFX10-FLUSH-NEXT: v_mad_f32 v12, -v3, v10, v81393; GFX10-FLUSH-NEXT: v_mad_f32 v13, -v4, v11, v91394; GFX10-FLUSH-NEXT: v_mac_f32_e32 v10, v12, v61395; GFX10-FLUSH-NEXT: v_mac_f32_e32 v11, v13, v71396; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v10, v81397; GFX10-FLUSH-NEXT: v_mad_f32 v4, -v4, v11, v91398; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v61399; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v4, v71400; GFX10-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v31401; GFX10-FLUSH-NEXT: v_and_b32_e32 v4, 0xff800000, v41402; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v101403; GFX10-FLUSH-NEXT: v_add_f32_e32 v4, v4, v111404; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v31405; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v41406; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v1, v01407; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v2, v51408; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v11409; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]1410;1411; GFX11-LABEL: v_fdiv_v2f16_ulp25:1412; GFX11: ; %bb.0:1413; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1414; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v11415; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v11416; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v01417; GFX11-NEXT: v_cvt_f32_f16_e32 v6, v01418; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v21419; GFX11-NEXT: v_rcp_f32_e32 v3, v31420; GFX11-NEXT: v_cvt_f32_f16_e32 v7, v51421; GFX11-NEXT: v_rcp_f32_e32 v4, v41422; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1423; GFX11-NEXT: v_dual_mul_f32 v6, v6, v3 :: v_dual_mul_f32 v7, v7, v41424; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]1425; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]1426; GFX11-NEXT: v_dual_fmac_f32 v6, v8, v3 :: v_dual_fmac_f32 v7, v9, v41427; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1]1428; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]1429; GFX11-NEXT: v_dual_mul_f32 v3, v8, v3 :: v_dual_mul_f32 v4, v9, v41430; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v31431; GFX11-NEXT: v_dual_add_f32 v3, v3, v6 :: v_dual_and_b32 v4, 0xff800000, v41432; GFX11-NEXT: v_add_f32_e32 v4, v4, v71433; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v31434; GFX11-NEXT: v_cvt_f16_f32_e32 v4, v41435; GFX11-NEXT: v_div_fixup_f16 v0, v3, v1, v01436; GFX11-NEXT: v_div_fixup_f16 v1, v4, v2, v51437; GFX11-NEXT: v_pack_b32_f16 v0, v0, v11438; GFX11-NEXT: s_setpc_b64 s[30:31]1439 %fdiv = fdiv <2 x half> %a, %b1440 ret <2 x half> %fdiv1441}1442 1443define <2 x half> @v_rcp_v2f16(<2 x half> %x) {1444; GFX6-IEEE-LABEL: v_rcp_v2f16:1445; GFX6-IEEE: ; %bb.0:1446; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1447; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v01448; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v11449; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.01450; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v21451; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.01452; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.01453; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v31454; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v31455; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v41456; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v51457; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v41458; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v51459; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.01460; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.01461; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v21462; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.01463; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v01464; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.01465; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v31466; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v31467; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v41468; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v51469; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v41470; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v51471; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, 1.01472; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v11473; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]1474;1475; GFX6-FLUSH-LABEL: v_rcp_v2f16:1476; GFX6-FLUSH: ; %bb.0:1477; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1478; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v01479; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.01480; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v21481; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.01482; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31483; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.01484; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v31485; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v31486; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v41487; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v51488; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v41489; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01490; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v11491; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v51492; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.01493; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 01494; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v01495; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.01496; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v21497; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.01498; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31499; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.01500; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v31501; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v31502; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v41503; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v51504; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v41505; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01506; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v51507; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.01508; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v11509; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]1510;1511; GFX8-IEEE-LABEL: v_rcp_v2f16:1512; GFX8-IEEE: ; %bb.0:1513; GFX8-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1514; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v01515; GFX8-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v01516; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v21517; GFX8-IEEE-NEXT: v_rcp_f32_e32 v4, v11518; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v31519; GFX8-IEEE-NEXT: v_mul_f32_e64 v6, -v1, v41520; GFX8-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v61521; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v41522; GFX8-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v51523; GFX8-IEEE-NEXT: v_add_f32_e32 v6, v6, v41524; GFX8-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v71525; GFX8-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v61526; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v51527; GFX8-IEEE-NEXT: v_add_f32_e32 v1, 1.0, v11528; GFX8-IEEE-NEXT: v_mul_f32_e32 v1, v1, v41529; GFX8-IEEE-NEXT: v_add_f32_e32 v4, v7, v51530; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v41531; GFX8-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v31532; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v51533; GFX8-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v11534; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v31535; GFX8-IEEE-NEXT: v_add_f32_e32 v1, v1, v61536; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v41537; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v11538; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v31539; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, 1.01540; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, 1.01541; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v11542; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v11543; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]1544;1545; GFX8-FLUSH-LABEL: v_rcp_v2f16:1546; GFX8-FLUSH: ; %bb.0:1547; GFX8-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1548; GFX8-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v01549; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v01550; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v21551; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v4, v11552; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v31553; GFX8-FLUSH-NEXT: v_mad_f32 v6, -v1, v4, 1.01554; GFX8-FLUSH-NEXT: v_mad_f32 v7, -v3, v5, 1.01555; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, v41556; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, v51557; GFX8-FLUSH-NEXT: v_mad_f32 v1, -v1, v6, 1.01558; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, 1.01559; GFX8-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v41560; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v51561; GFX8-FLUSH-NEXT: v_and_b32_e32 v1, 0xff800000, v11562; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v31563; GFX8-FLUSH-NEXT: v_add_f32_e32 v1, v1, v61564; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v71565; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v11566; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v31567; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, 1.01568; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, 1.01569; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v11570; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v11571; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]1572;1573; GFX9-IEEE-LABEL: v_rcp_v2f16:1574; GFX9-IEEE: ; %bb.0:1575; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1576; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v01577; GFX9-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v01578; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v21579; GFX9-IEEE-NEXT: v_rcp_f32_e32 v4, v11580; GFX9-IEEE-NEXT: v_rcp_f32_e32 v5, v31581; GFX9-IEEE-NEXT: v_mul_f32_e64 v6, -v1, v41582; GFX9-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v61583; GFX9-IEEE-NEXT: v_mul_f32_e32 v6, v6, v41584; GFX9-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v51585; GFX9-IEEE-NEXT: v_add_f32_e32 v6, v6, v41586; GFX9-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v71587; GFX9-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v61588; GFX9-IEEE-NEXT: v_mul_f32_e32 v7, v7, v51589; GFX9-IEEE-NEXT: v_add_f32_e32 v1, 1.0, v11590; GFX9-IEEE-NEXT: v_mul_f32_e32 v1, v1, v41591; GFX9-IEEE-NEXT: v_add_f32_e32 v4, v7, v51592; GFX9-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v41593; GFX9-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v31594; GFX9-IEEE-NEXT: v_mul_f32_e32 v3, v3, v51595; GFX9-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v11596; GFX9-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v31597; GFX9-IEEE-NEXT: v_add_f32_e32 v1, v1, v61598; GFX9-IEEE-NEXT: v_add_f32_e32 v3, v3, v41599; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v11600; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v31601; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, 1.01602; GFX9-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, 1.01603; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v0, v11604; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31]1605;1606; GFX9-FLUSH-LABEL: v_rcp_v2f16:1607; GFX9-FLUSH: ; %bb.0:1608; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1609; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v01610; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v01611; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v21612; GFX9-FLUSH-NEXT: v_mov_b32_e32 v4, 1.01613; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v1, v11614; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v3, v31615; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, -v0, v1, v4 op_sel_hi:[1,0,0]1616; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v0, v3, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]1617; GFX9-FLUSH-NEXT: v_mad_f32 v5, v5, v1, v11618; GFX9-FLUSH-NEXT: v_mad_f32 v6, v6, v3, v31619; GFX9-FLUSH-NEXT: v_mad_mix_f32 v7, -v0, v5, v4 op_sel_hi:[1,0,0]1620; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v0, v6, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]1621; GFX9-FLUSH-NEXT: v_mul_f32_e32 v1, v7, v11622; GFX9-FLUSH-NEXT: v_mul_f32_e32 v3, v4, v31623; GFX9-FLUSH-NEXT: v_and_b32_e32 v1, 0xff800000, v11624; GFX9-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v31625; GFX9-FLUSH-NEXT: v_add_f32_e32 v1, v1, v51626; GFX9-FLUSH-NEXT: v_add_f32_e32 v3, v3, v61627; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v11628; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v31629; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, 1.01630; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, 1.01631; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v11632; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31]1633;1634; GFX10-IEEE-LABEL: v_rcp_v2f16:1635; GFX10-IEEE: ; %bb.0:1636; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1637; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v01638; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v01639; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v11640; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v21641; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v31642; GFX10-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v41643; GFX10-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v51644; GFX10-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v61645; GFX10-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v71646; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v41647; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v7, v51648; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v6, v41649; GFX10-IEEE-NEXT: v_add_f32_e32 v7, v7, v51650; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v61651; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v71652; GFX10-IEEE-NEXT: v_add_f32_e32 v2, 1.0, v21653; GFX10-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v31654; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v41655; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v51656; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v21657; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v31658; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v61659; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v71660; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v21661; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v31662; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v0, 1.01663; GFX10-IEEE-NEXT: v_div_fixup_f16 v1, v3, v1, 1.01664; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v0, v11665; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]1666;1667; GFX10-FLUSH-LABEL: v_rcp_v2f16:1668; GFX10-FLUSH: ; %bb.0:1669; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1670; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v01671; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v01672; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v11673; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v4, v21674; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v31675; GFX10-FLUSH-NEXT: v_mad_f32 v6, -v2, v4, 1.01676; GFX10-FLUSH-NEXT: v_mad_f32 v7, -v3, v5, 1.01677; GFX10-FLUSH-NEXT: v_mad_f32 v6, v6, v4, v41678; GFX10-FLUSH-NEXT: v_mad_f32 v7, v7, v5, v51679; GFX10-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, 1.01680; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, 1.01681; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v41682; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v51683; GFX10-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v21684; GFX10-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v31685; GFX10-FLUSH-NEXT: v_add_f32_e32 v2, v2, v61686; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v71687; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v21688; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v31689; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v0, 1.01690; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v1, 1.01691; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v11692; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]1693;1694; GFX11-LABEL: v_rcp_v2f16:1695; GFX11: ; %bb.0:1696; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1697; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v01698; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v01699; GFX11-NEXT: v_mov_b32_e32 v4, 1.01700; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v11701; GFX11-NEXT: v_rcp_f32_e32 v2, v21702; GFX11-NEXT: v_rcp_f32_e32 v3, v31703; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1704; GFX11-NEXT: v_fma_mix_f32 v5, -v0, v2, v4 op_sel_hi:[1,0,0]1705; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v3, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]1706; GFX11-NEXT: v_fma_f32 v5, v5, v2, v21707; GFX11-NEXT: v_fma_f32 v6, v6, v3, v31708; GFX11-NEXT: v_fma_mix_f32 v7, -v0, v5, v4 op_sel_hi:[1,0,0]1709; GFX11-NEXT: v_fma_mix_f32 v4, -v0, v6, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]1710; GFX11-NEXT: v_dual_mul_f32 v2, v7, v2 :: v_dual_mul_f32 v3, v4, v31711; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v21712; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_and_b32 v3, 0xff800000, v31713; GFX11-NEXT: v_add_f32_e32 v3, v3, v61714; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v21715; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v31716; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, 1.01717; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, 1.01718; GFX11-NEXT: v_pack_b32_f16 v0, v0, v11719; GFX11-NEXT: s_setpc_b64 s[30:31]1720 %fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x1721 ret <2 x half> %fdiv1722}1723 1724define <2 x half> @v_neg_rcp_v2f16(<2 x half> %x) {1725; GFX6-IEEE-LABEL: v_neg_rcp_v2f16:1726; GFX6-IEEE: ; %bb.0:1727; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1728; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v01729; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v11730; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, -1.01731; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v21732; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, -1.0, v0, -1.01733; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.01734; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v31735; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v31736; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v41737; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v51738; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v41739; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v51740; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, -1.01741; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -1.01742; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v21743; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, -1.0, v1, -1.01744; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v01745; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.01746; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v31747; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v31748; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v41749; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v51750; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v41751; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v51752; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, -1.01753; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v11754; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]1755;1756; GFX6-FLUSH-LABEL: v_neg_rcp_v2f16:1757; GFX6-FLUSH: ; %bb.0:1758; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1759; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v01760; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, -1.01761; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v21762; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, -1.0, v0, -1.01763; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31764; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.01765; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v31766; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v31767; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v41768; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v51769; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v41770; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01771; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v11772; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v51773; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, -1.01774; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 01775; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v01776; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -1.01777; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v21778; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, -1.0, v1, -1.01779; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31780; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.01781; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v31782; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v31783; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v41784; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v51785; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v41786; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01787; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v51788; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, -1.01789; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v11790; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]1791;1792; GFX8-IEEE-LABEL: v_neg_rcp_v2f16:1793; GFX8-IEEE: ; %bb.0:1794; GFX8-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1795; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v01796; GFX8-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v01797; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v21798; GFX8-IEEE-NEXT: v_rcp_f32_e32 v4, v11799; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v31800; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v1, v41801; GFX8-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v61802; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v41803; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v3, v51804; GFX8-IEEE-NEXT: v_sub_f32_e32 v6, v6, v41805; GFX8-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v71806; GFX8-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v61807; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v51808; GFX8-IEEE-NEXT: v_add_f32_e32 v1, -1.0, v11809; GFX8-IEEE-NEXT: v_mul_f32_e32 v1, v1, v41810; GFX8-IEEE-NEXT: v_sub_f32_e32 v4, v7, v51811; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v41812; GFX8-IEEE-NEXT: v_add_f32_e32 v3, -1.0, v31813; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v51814; GFX8-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v11815; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v31816; GFX8-IEEE-NEXT: v_add_f32_e32 v1, v1, v61817; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v41818; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v11819; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v31820; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, -1.01821; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, -1.01822; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v11823; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v11824; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]1825;1826; GFX8-FLUSH-LABEL: v_neg_rcp_v2f16:1827; GFX8-FLUSH: ; %bb.0:1828; GFX8-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1829; GFX8-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v01830; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v01831; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v21832; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v4, v11833; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v31834; GFX8-FLUSH-NEXT: v_mad_f32 v6, v1, v4, -1.01835; GFX8-FLUSH-NEXT: v_mad_f32 v7, v3, v5, -1.01836; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, -v41837; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, -v51838; GFX8-FLUSH-NEXT: v_mad_f32 v1, -v1, v6, -1.01839; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, -1.01840; GFX8-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v41841; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v51842; GFX8-FLUSH-NEXT: v_and_b32_e32 v1, 0xff800000, v11843; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v31844; GFX8-FLUSH-NEXT: v_add_f32_e32 v1, v1, v61845; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v71846; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v11847; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v31848; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, -1.01849; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, -1.01850; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v11851; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v11852; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]1853;1854; GFX9-IEEE-LABEL: v_neg_rcp_v2f16:1855; GFX9-IEEE: ; %bb.0:1856; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1857; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v01858; GFX9-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v01859; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v21860; GFX9-IEEE-NEXT: v_rcp_f32_e32 v4, v11861; GFX9-IEEE-NEXT: v_rcp_f32_e32 v5, v31862; GFX9-IEEE-NEXT: v_mul_f32_e32 v6, v1, v41863; GFX9-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v61864; GFX9-IEEE-NEXT: v_mul_f32_e32 v6, v6, v41865; GFX9-IEEE-NEXT: v_mul_f32_e32 v7, v3, v51866; GFX9-IEEE-NEXT: v_sub_f32_e32 v6, v6, v41867; GFX9-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v71868; GFX9-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v61869; GFX9-IEEE-NEXT: v_mul_f32_e32 v7, v7, v51870; GFX9-IEEE-NEXT: v_add_f32_e32 v1, -1.0, v11871; GFX9-IEEE-NEXT: v_mul_f32_e32 v1, v1, v41872; GFX9-IEEE-NEXT: v_sub_f32_e32 v4, v7, v51873; GFX9-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v41874; GFX9-IEEE-NEXT: v_add_f32_e32 v3, -1.0, v31875; GFX9-IEEE-NEXT: v_mul_f32_e32 v3, v3, v51876; GFX9-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v11877; GFX9-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v31878; GFX9-IEEE-NEXT: v_add_f32_e32 v1, v1, v61879; GFX9-IEEE-NEXT: v_add_f32_e32 v3, v3, v41880; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v11881; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v31882; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, -1.01883; GFX9-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, -1.01884; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v0, v11885; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31]1886;1887; GFX9-FLUSH-LABEL: v_neg_rcp_v2f16:1888; GFX9-FLUSH: ; %bb.0:1889; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1890; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v01891; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v01892; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v21893; GFX9-FLUSH-NEXT: v_mov_b32_e32 v4, -1.01894; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v1, v11895; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v3, v31896; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, v0, v1, v4 op_sel_hi:[1,0,0]1897; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, v0, v3, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]1898; GFX9-FLUSH-NEXT: v_mad_f32 v5, v5, v1, -v11899; GFX9-FLUSH-NEXT: v_mad_f32 v6, v6, v3, -v31900; GFX9-FLUSH-NEXT: v_mad_mix_f32 v7, -v0, v5, v4 op_sel_hi:[1,0,0]1901; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v0, v6, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]1902; GFX9-FLUSH-NEXT: v_mul_f32_e32 v1, v7, v11903; GFX9-FLUSH-NEXT: v_mul_f32_e32 v3, v4, v31904; GFX9-FLUSH-NEXT: v_and_b32_e32 v1, 0xff800000, v11905; GFX9-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v31906; GFX9-FLUSH-NEXT: v_add_f32_e32 v1, v1, v51907; GFX9-FLUSH-NEXT: v_add_f32_e32 v3, v3, v61908; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v11909; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v31910; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, -1.01911; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, -1.01912; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v11913; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31]1914;1915; GFX10-IEEE-LABEL: v_neg_rcp_v2f16:1916; GFX10-IEEE: ; %bb.0:1917; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1918; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v01919; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v01920; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v11921; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v21922; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v31923; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v2, v41924; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v3, v51925; GFX10-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v61926; GFX10-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v71927; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v41928; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v7, v51929; GFX10-IEEE-NEXT: v_sub_f32_e32 v6, v6, v41930; GFX10-IEEE-NEXT: v_sub_f32_e32 v7, v7, v51931; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v61932; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v71933; GFX10-IEEE-NEXT: v_add_f32_e32 v2, -1.0, v21934; GFX10-IEEE-NEXT: v_add_f32_e32 v3, -1.0, v31935; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v41936; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v51937; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v21938; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v31939; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v61940; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v71941; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v21942; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v31943; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v0, -1.01944; GFX10-IEEE-NEXT: v_div_fixup_f16 v1, v3, v1, -1.01945; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v0, v11946; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]1947;1948; GFX10-FLUSH-LABEL: v_neg_rcp_v2f16:1949; GFX10-FLUSH: ; %bb.0:1950; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1951; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v01952; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v01953; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v11954; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v4, v21955; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v31956; GFX10-FLUSH-NEXT: v_mad_f32 v6, v2, v4, -1.01957; GFX10-FLUSH-NEXT: v_mad_f32 v7, v3, v5, -1.01958; GFX10-FLUSH-NEXT: v_mad_f32 v6, v6, v4, -v41959; GFX10-FLUSH-NEXT: v_mad_f32 v7, v7, v5, -v51960; GFX10-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, -1.01961; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, -1.01962; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v41963; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v51964; GFX10-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v21965; GFX10-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v31966; GFX10-FLUSH-NEXT: v_add_f32_e32 v2, v2, v61967; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v71968; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v21969; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v31970; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v0, -1.01971; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v1, -1.01972; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v11973; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]1974;1975; GFX11-LABEL: v_neg_rcp_v2f16:1976; GFX11: ; %bb.0:1977; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1978; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v01979; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v01980; GFX11-NEXT: v_mov_b32_e32 v4, -1.01981; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v11982; GFX11-NEXT: v_rcp_f32_e32 v2, v21983; GFX11-NEXT: v_rcp_f32_e32 v3, v31984; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1985; GFX11-NEXT: v_fma_mix_f32 v5, v0, v2, v4 op_sel_hi:[1,0,0]1986; GFX11-NEXT: v_fma_mix_f32 v6, v0, v3, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]1987; GFX11-NEXT: v_fma_f32 v5, v5, v2, -v21988; GFX11-NEXT: v_fma_f32 v6, v6, v3, -v31989; GFX11-NEXT: v_fma_mix_f32 v7, -v0, v5, v4 op_sel_hi:[1,0,0]1990; GFX11-NEXT: v_fma_mix_f32 v4, -v0, v6, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]1991; GFX11-NEXT: v_dual_mul_f32 v2, v7, v2 :: v_dual_mul_f32 v3, v4, v31992; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v21993; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_and_b32 v3, 0xff800000, v31994; GFX11-NEXT: v_add_f32_e32 v3, v3, v61995; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v21996; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v31997; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, -1.01998; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, -1.01999; GFX11-NEXT: v_pack_b32_f16 v0, v0, v12000; GFX11-NEXT: s_setpc_b64 s[30:31]2001 %fdiv = fdiv <2 x half> <half -1.0, half -1.0>, %x2002 ret <2 x half> %fdiv2003}2004 2005define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) {2006; GFX6-IEEE-LABEL: v_rcp_v2f16_fabs:2007; GFX6-IEEE: ; %bb.0:2008; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2009; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v12010; GFX6-IEEE-NEXT: v_and_b32_e32 v0, 0xffff, v02011; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v02012; GFX6-IEEE-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02013; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v02014; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v02015; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.02016; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v22017; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.02018; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.02019; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v32020; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v32021; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v42022; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v52023; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v42024; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v02025; GFX6-IEEE-NEXT: v_div_fmas_f32 v0, v2, v3, v52026; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v0, v1, 1.02027; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v02028; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v4, v4, 1.02029; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v12030; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v4, 1.02031; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v2, 1.02032; GFX6-IEEE-NEXT: v_fma_f32 v2, v5, v2, v22033; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v3, v22034; GFX6-IEEE-NEXT: v_fma_f32 v6, -v1, v5, v32035; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v2, v52036; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v5, v32037; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v52038; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v1, v4, 1.02039; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v12040; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]2041;2042; GFX6-FLUSH-LABEL: v_rcp_v2f16_fabs:2043; GFX6-FLUSH: ; %bb.0:2044; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2045; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v12046; GFX6-FLUSH-NEXT: v_and_b32_e32 v0, 0xffff, v02047; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v02048; GFX6-FLUSH-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02049; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v02050; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v02051; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.02052; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v22053; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.02054; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32055; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.02056; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v32057; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v32058; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v42059; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v52060; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v42061; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02062; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v52063; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v02064; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, 1.02065; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 02066; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v02067; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v3, v3, 1.02068; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v12069; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v3, 1.02070; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32071; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v2, 1.02072; GFX6-FLUSH-NEXT: v_fma_f32 v2, v5, v2, v22073; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v22074; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v1, v5, v42075; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v2, v52076; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v5, v42077; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02078; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v52079; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v1, v3, 1.02080; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v12081; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]2082;2083; GFX8-IEEE-LABEL: v_rcp_v2f16_fabs:2084; GFX8-IEEE: ; %bb.0:2085; GFX8-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2086; GFX8-IEEE-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02087; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v02088; GFX8-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v02089; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v22090; GFX8-IEEE-NEXT: v_rcp_f32_e32 v4, v12091; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v32092; GFX8-IEEE-NEXT: v_mul_f32_e64 v6, -v1, v42093; GFX8-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v62094; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v42095; GFX8-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v52096; GFX8-IEEE-NEXT: v_add_f32_e32 v6, v6, v42097; GFX8-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v72098; GFX8-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v62099; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v52100; GFX8-IEEE-NEXT: v_add_f32_e32 v1, 1.0, v12101; GFX8-IEEE-NEXT: v_mul_f32_e32 v1, v1, v42102; GFX8-IEEE-NEXT: v_add_f32_e32 v4, v7, v52103; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v42104; GFX8-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v32105; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v52106; GFX8-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v12107; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v32108; GFX8-IEEE-NEXT: v_add_f32_e32 v1, v1, v62109; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v42110; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v12111; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v32112; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, 1.02113; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, 1.02114; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v12115; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v12116; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]2117;2118; GFX8-FLUSH-LABEL: v_rcp_v2f16_fabs:2119; GFX8-FLUSH: ; %bb.0:2120; GFX8-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2121; GFX8-FLUSH-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02122; GFX8-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v02123; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v02124; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v22125; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v4, v12126; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v32127; GFX8-FLUSH-NEXT: v_mad_f32 v6, -v1, v4, 1.02128; GFX8-FLUSH-NEXT: v_mad_f32 v7, -v3, v5, 1.02129; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, v42130; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, v52131; GFX8-FLUSH-NEXT: v_mad_f32 v1, -v1, v6, 1.02132; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, 1.02133; GFX8-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v42134; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v52135; GFX8-FLUSH-NEXT: v_and_b32_e32 v1, 0xff800000, v12136; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v32137; GFX8-FLUSH-NEXT: v_add_f32_e32 v1, v1, v62138; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v72139; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v12140; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v32141; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, 1.02142; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, 1.02143; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v12144; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v12145; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]2146;2147; GFX9-IEEE-LABEL: v_rcp_v2f16_fabs:2148; GFX9-IEEE: ; %bb.0:2149; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2150; GFX9-IEEE-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02151; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v02152; GFX9-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v02153; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v22154; GFX9-IEEE-NEXT: v_rcp_f32_e32 v4, v12155; GFX9-IEEE-NEXT: v_rcp_f32_e32 v5, v32156; GFX9-IEEE-NEXT: v_mul_f32_e64 v6, -v1, v42157; GFX9-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v62158; GFX9-IEEE-NEXT: v_mul_f32_e32 v6, v6, v42159; GFX9-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v52160; GFX9-IEEE-NEXT: v_add_f32_e32 v6, v6, v42161; GFX9-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v72162; GFX9-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v62163; GFX9-IEEE-NEXT: v_mul_f32_e32 v7, v7, v52164; GFX9-IEEE-NEXT: v_add_f32_e32 v1, 1.0, v12165; GFX9-IEEE-NEXT: v_mul_f32_e32 v1, v1, v42166; GFX9-IEEE-NEXT: v_add_f32_e32 v4, v7, v52167; GFX9-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v42168; GFX9-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v32169; GFX9-IEEE-NEXT: v_mul_f32_e32 v3, v3, v52170; GFX9-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v12171; GFX9-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v32172; GFX9-IEEE-NEXT: v_add_f32_e32 v1, v1, v62173; GFX9-IEEE-NEXT: v_add_f32_e32 v3, v3, v42174; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v12175; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v32176; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, 1.02177; GFX9-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, 1.02178; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v0, v12179; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31]2180;2181; GFX9-FLUSH-LABEL: v_rcp_v2f16_fabs:2182; GFX9-FLUSH: ; %bb.0:2183; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2184; GFX9-FLUSH-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v02185; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v12186; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v12187; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v32188; GFX9-FLUSH-NEXT: v_mov_b32_e32 v5, 1.02189; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v22190; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v4, v42191; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v2, v5 op_sel_hi:[1,0,0]2192; GFX9-FLUSH-NEXT: v_mad_mix_f32 v7, -|v0|, v4, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]2193; GFX9-FLUSH-NEXT: v_mad_f32 v6, v6, v2, v22194; GFX9-FLUSH-NEXT: v_mad_f32 v7, v7, v4, v42195; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v6, v5 op_sel_hi:[1,0,0]2196; GFX9-FLUSH-NEXT: v_mad_mix_f32 v0, -|v0|, v7, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]2197; GFX9-FLUSH-NEXT: v_mul_f32_e32 v2, v8, v22198; GFX9-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v42199; GFX9-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v22200; GFX9-FLUSH-NEXT: v_and_b32_e32 v0, 0xff800000, v02201; GFX9-FLUSH-NEXT: v_add_f32_e32 v2, v2, v62202; GFX9-FLUSH-NEXT: v_add_f32_e32 v0, v0, v72203; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v22204; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v02205; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, 1.02206; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v0, v3, 1.02207; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v1, v02208; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31]2209;2210; GFX10-IEEE-LABEL: v_rcp_v2f16_fabs:2211; GFX10-IEEE: ; %bb.0:2212; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2213; GFX10-IEEE-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02214; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v02215; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v02216; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v12217; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v22218; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v32219; GFX10-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v42220; GFX10-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v52221; GFX10-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v62222; GFX10-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v72223; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v42224; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v7, v52225; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v6, v42226; GFX10-IEEE-NEXT: v_add_f32_e32 v7, v7, v52227; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v62228; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v72229; GFX10-IEEE-NEXT: v_add_f32_e32 v2, 1.0, v22230; GFX10-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v32231; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v42232; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v52233; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v22234; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v32235; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v62236; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v72237; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v22238; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v32239; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v0, 1.02240; GFX10-IEEE-NEXT: v_div_fixup_f16 v1, v3, v1, 1.02241; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v0, v12242; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]2243;2244; GFX10-FLUSH-LABEL: v_rcp_v2f16_fabs:2245; GFX10-FLUSH: ; %bb.0:2246; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2247; GFX10-FLUSH-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02248; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v02249; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v02250; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v12251; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v4, v22252; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v32253; GFX10-FLUSH-NEXT: v_mad_f32 v6, -v2, v4, 1.02254; GFX10-FLUSH-NEXT: v_mad_f32 v7, -v3, v5, 1.02255; GFX10-FLUSH-NEXT: v_mad_f32 v6, v6, v4, v42256; GFX10-FLUSH-NEXT: v_mad_f32 v7, v7, v5, v52257; GFX10-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, 1.02258; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, 1.02259; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v42260; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v52261; GFX10-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v22262; GFX10-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v32263; GFX10-FLUSH-NEXT: v_add_f32_e32 v2, v2, v62264; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v72265; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v22266; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v32267; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v0, 1.02268; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v1, 1.02269; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v12270; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]2271;2272; GFX11-LABEL: v_rcp_v2f16_fabs:2273; GFX11: ; %bb.0:2274; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2275; GFX11-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v02276; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v12277; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v22278; GFX11-NEXT: v_rcp_f32_e32 v4, v42279; GFX11-NEXT: v_mov_b32_e32 v5, 1.02280; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2281; GFX11-NEXT: v_fma_mix_f32 v7, -|v0|, v4, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]2282; GFX11-NEXT: v_fma_f32 v7, v7, v4, v42283; GFX11-NEXT: v_fma_mix_f32 v0, -|v0|, v7, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]2284; GFX11-NEXT: v_mul_f32_e32 v0, v0, v42285; GFX11-NEXT: v_and_b32_e32 v0, 0xff800000, v02286; GFX11-NEXT: v_add_f32_e32 v0, v0, v72287; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v12288; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v02289; GFX11-NEXT: v_rcp_f32_e32 v3, v32290; GFX11-NEXT: v_div_fixup_f16 v0, v0, v2, 1.02291; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2292; GFX11-NEXT: v_fma_mix_f32 v6, -v1, v3, v5 op_sel_hi:[1,0,0]2293; GFX11-NEXT: v_fma_f32 v6, v6, v3, v32294; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v5 op_sel_hi:[1,0,0]2295; GFX11-NEXT: v_mul_f32_e32 v3, v8, v32296; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v32297; GFX11-NEXT: v_add_f32_e32 v3, v3, v62298; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v32299; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, 1.02300; GFX11-NEXT: v_pack_b32_f16 v0, v1, v02301; GFX11-NEXT: s_setpc_b64 s[30:31]2302 %x.fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)2303 %fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x.fabs2304 ret <2 x half> %fdiv2305}2306 2307define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) {2308; GFX6-IEEE-LABEL: v_neg_rcp_v2f16_fabs:2309; GFX6-IEEE: ; %bb.0:2310; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2311; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v12312; GFX6-IEEE-NEXT: v_and_b32_e32 v0, 0xffff, v02313; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v1, v02314; GFX6-IEEE-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02315; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v02316; GFX6-IEEE-NEXT: v_lshrrev_b32_e32 v0, 16, v02317; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -1.02318; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v22319; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, -1.0, v1, -1.02320; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.02321; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v32322; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v32323; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v42324; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v52325; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v42326; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v02327; GFX6-IEEE-NEXT: v_div_fmas_f32 v0, v2, v3, v52328; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v0, v1, -1.02329; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v02330; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v4, v4, -1.02331; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v12332; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, -1.0, v4, -1.02333; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v2, 1.02334; GFX6-IEEE-NEXT: v_fma_f32 v2, v5, v2, v22335; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v3, v22336; GFX6-IEEE-NEXT: v_fma_f32 v6, -v1, v5, v32337; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v2, v52338; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v5, v32339; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v52340; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v1, v4, -1.02341; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v12342; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]2343;2344; GFX6-FLUSH-LABEL: v_neg_rcp_v2f16_fabs:2345; GFX6-FLUSH: ; %bb.0:2346; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2347; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v12348; GFX6-FLUSH-NEXT: v_and_b32_e32 v0, 0xffff, v02349; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v1, v02350; GFX6-FLUSH-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02351; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v02352; GFX6-FLUSH-NEXT: v_lshrrev_b32_e32 v0, 16, v02353; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -1.02354; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v22355; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, -1.0, v1, -1.02356; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32357; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.02358; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v32359; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v32360; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v42361; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v52362; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v42363; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02364; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v52365; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v02366; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, -1.02367; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 02368; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v02369; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v3, v3, -1.02370; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v12371; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, -1.0, v3, -1.02372; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32373; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v2, 1.02374; GFX6-FLUSH-NEXT: v_fma_f32 v2, v5, v2, v22375; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v22376; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v1, v5, v42377; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v2, v52378; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v5, v42379; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02380; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v52381; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v1, v3, -1.02382; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v12383; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]2384;2385; GFX8-IEEE-LABEL: v_neg_rcp_v2f16_fabs:2386; GFX8-IEEE: ; %bb.0:2387; GFX8-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2388; GFX8-IEEE-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02389; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v02390; GFX8-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v02391; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v22392; GFX8-IEEE-NEXT: v_rcp_f32_e32 v4, v12393; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v32394; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v1, v42395; GFX8-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v62396; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v42397; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v3, v52398; GFX8-IEEE-NEXT: v_sub_f32_e32 v6, v6, v42399; GFX8-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v72400; GFX8-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v62401; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v52402; GFX8-IEEE-NEXT: v_add_f32_e32 v1, -1.0, v12403; GFX8-IEEE-NEXT: v_mul_f32_e32 v1, v1, v42404; GFX8-IEEE-NEXT: v_sub_f32_e32 v4, v7, v52405; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v42406; GFX8-IEEE-NEXT: v_add_f32_e32 v3, -1.0, v32407; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v52408; GFX8-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v12409; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v32410; GFX8-IEEE-NEXT: v_add_f32_e32 v1, v1, v62411; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v42412; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v12413; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v32414; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, -1.02415; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, -1.02416; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v12417; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v12418; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]2419;2420; GFX8-FLUSH-LABEL: v_neg_rcp_v2f16_fabs:2421; GFX8-FLUSH: ; %bb.0:2422; GFX8-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2423; GFX8-FLUSH-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02424; GFX8-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v02425; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v02426; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v22427; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v4, v12428; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v32429; GFX8-FLUSH-NEXT: v_mad_f32 v6, v1, v4, -1.02430; GFX8-FLUSH-NEXT: v_mad_f32 v7, v3, v5, -1.02431; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, -v42432; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, -v52433; GFX8-FLUSH-NEXT: v_mad_f32 v1, -v1, v6, -1.02434; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, -1.02435; GFX8-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v42436; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v52437; GFX8-FLUSH-NEXT: v_and_b32_e32 v1, 0xff800000, v12438; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v32439; GFX8-FLUSH-NEXT: v_add_f32_e32 v1, v1, v62440; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v72441; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v12442; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v32443; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, -1.02444; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, -1.02445; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v12446; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v12447; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]2448;2449; GFX9-IEEE-LABEL: v_neg_rcp_v2f16_fabs:2450; GFX9-IEEE: ; %bb.0:2451; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2452; GFX9-IEEE-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02453; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v02454; GFX9-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v02455; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v22456; GFX9-IEEE-NEXT: v_rcp_f32_e32 v4, v12457; GFX9-IEEE-NEXT: v_rcp_f32_e32 v5, v32458; GFX9-IEEE-NEXT: v_mul_f32_e32 v6, v1, v42459; GFX9-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v62460; GFX9-IEEE-NEXT: v_mul_f32_e32 v6, v6, v42461; GFX9-IEEE-NEXT: v_mul_f32_e32 v7, v3, v52462; GFX9-IEEE-NEXT: v_sub_f32_e32 v6, v6, v42463; GFX9-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v72464; GFX9-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v62465; GFX9-IEEE-NEXT: v_mul_f32_e32 v7, v7, v52466; GFX9-IEEE-NEXT: v_add_f32_e32 v1, -1.0, v12467; GFX9-IEEE-NEXT: v_mul_f32_e32 v1, v1, v42468; GFX9-IEEE-NEXT: v_sub_f32_e32 v4, v7, v52469; GFX9-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v42470; GFX9-IEEE-NEXT: v_add_f32_e32 v3, -1.0, v32471; GFX9-IEEE-NEXT: v_mul_f32_e32 v3, v3, v52472; GFX9-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v12473; GFX9-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v32474; GFX9-IEEE-NEXT: v_add_f32_e32 v1, v1, v62475; GFX9-IEEE-NEXT: v_add_f32_e32 v3, v3, v42476; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v12477; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v32478; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, -1.02479; GFX9-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, -1.02480; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v0, v12481; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31]2482;2483; GFX9-FLUSH-LABEL: v_neg_rcp_v2f16_fabs:2484; GFX9-FLUSH: ; %bb.0:2485; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2486; GFX9-FLUSH-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v02487; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v12488; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v12489; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v32490; GFX9-FLUSH-NEXT: v_mov_b32_e32 v5, -1.02491; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v22492; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v4, v42493; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, v1, v2, v5 op_sel_hi:[1,0,0]2494; GFX9-FLUSH-NEXT: v_mad_mix_f32 v7, |v0|, v4, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]2495; GFX9-FLUSH-NEXT: v_mad_f32 v6, v6, v2, -v22496; GFX9-FLUSH-NEXT: v_mad_f32 v7, v7, v4, -v42497; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v6, v5 op_sel_hi:[1,0,0]2498; GFX9-FLUSH-NEXT: v_mad_mix_f32 v0, -|v0|, v7, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]2499; GFX9-FLUSH-NEXT: v_mul_f32_e32 v2, v8, v22500; GFX9-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v42501; GFX9-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v22502; GFX9-FLUSH-NEXT: v_and_b32_e32 v0, 0xff800000, v02503; GFX9-FLUSH-NEXT: v_add_f32_e32 v2, v2, v62504; GFX9-FLUSH-NEXT: v_add_f32_e32 v0, v0, v72505; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v22506; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v02507; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, -1.02508; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v0, v3, -1.02509; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v1, v02510; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31]2511;2512; GFX10-IEEE-LABEL: v_neg_rcp_v2f16_fabs:2513; GFX10-IEEE: ; %bb.0:2514; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2515; GFX10-IEEE-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02516; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v02517; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v02518; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v12519; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v22520; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v32521; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v2, v42522; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v3, v52523; GFX10-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v62524; GFX10-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v72525; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v42526; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v7, v52527; GFX10-IEEE-NEXT: v_sub_f32_e32 v6, v6, v42528; GFX10-IEEE-NEXT: v_sub_f32_e32 v7, v7, v52529; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v62530; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v72531; GFX10-IEEE-NEXT: v_add_f32_e32 v2, -1.0, v22532; GFX10-IEEE-NEXT: v_add_f32_e32 v3, -1.0, v32533; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v42534; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v52535; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v22536; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v32537; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v62538; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v72539; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v22540; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v32541; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v0, -1.02542; GFX10-IEEE-NEXT: v_div_fixup_f16 v1, v3, v1, -1.02543; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v0, v12544; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]2545;2546; GFX10-FLUSH-LABEL: v_neg_rcp_v2f16_fabs:2547; GFX10-FLUSH: ; %bb.0:2548; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2549; GFX10-FLUSH-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v02550; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v02551; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v02552; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v12553; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v4, v22554; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v32555; GFX10-FLUSH-NEXT: v_mad_f32 v6, v2, v4, -1.02556; GFX10-FLUSH-NEXT: v_mad_f32 v7, v3, v5, -1.02557; GFX10-FLUSH-NEXT: v_mad_f32 v6, v6, v4, -v42558; GFX10-FLUSH-NEXT: v_mad_f32 v7, v7, v5, -v52559; GFX10-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, -1.02560; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, -1.02561; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v42562; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v52563; GFX10-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v22564; GFX10-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v32565; GFX10-FLUSH-NEXT: v_add_f32_e32 v2, v2, v62566; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v72567; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v22568; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v32569; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v0, -1.02570; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v1, -1.02571; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v12572; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]2573;2574; GFX11-LABEL: v_neg_rcp_v2f16_fabs:2575; GFX11: ; %bb.0:2576; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2577; GFX11-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v02578; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v12579; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v22580; GFX11-NEXT: v_rcp_f32_e32 v4, v42581; GFX11-NEXT: v_mov_b32_e32 v5, -1.02582; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2583; GFX11-NEXT: v_fma_mix_f32 v7, |v0|, v4, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]2584; GFX11-NEXT: v_fma_f32 v7, v7, v4, -v42585; GFX11-NEXT: v_fma_mix_f32 v0, -|v0|, v7, v5 op_sel:[1,0,0] op_sel_hi:[1,0,0]2586; GFX11-NEXT: v_mul_f32_e32 v0, v0, v42587; GFX11-NEXT: v_and_b32_e32 v0, 0xff800000, v02588; GFX11-NEXT: v_add_f32_e32 v0, v0, v72589; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v12590; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v02591; GFX11-NEXT: v_rcp_f32_e32 v3, v32592; GFX11-NEXT: v_div_fixup_f16 v0, v0, v2, -1.02593; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2594; GFX11-NEXT: v_fma_mix_f32 v6, v1, v3, v5 op_sel_hi:[1,0,0]2595; GFX11-NEXT: v_fma_f32 v6, v6, v3, -v32596; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v5 op_sel_hi:[1,0,0]2597; GFX11-NEXT: v_mul_f32_e32 v3, v8, v32598; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v32599; GFX11-NEXT: v_add_f32_e32 v3, v3, v62600; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v32601; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, -1.02602; GFX11-NEXT: v_pack_b32_f16 v0, v1, v02603; GFX11-NEXT: s_setpc_b64 s[30:31]2604 %x.fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)2605 %fdiv = fdiv <2 x half> <half -1.0, half -1.0>, %x.fabs2606 ret <2 x half> %fdiv2607}2608 2609define <2 x half> @v_rcp_v2f16_arcp(<2 x half> %x) {2610; GFX6-IEEE-LABEL: v_rcp_v2f16_arcp:2611; GFX6-IEEE: ; %bb.0:2612; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2613; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v02614; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v12615; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.02616; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v22617; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.02618; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.02619; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v32620; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v32621; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v42622; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v52623; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v42624; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v52625; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.02626; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.02627; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v22628; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.02629; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v02630; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.02631; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v32632; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v32633; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v42634; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v52635; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v42636; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v52637; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, 1.02638; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v12639; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]2640;2641; GFX6-FLUSH-LABEL: v_rcp_v2f16_arcp:2642; GFX6-FLUSH: ; %bb.0:2643; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2644; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v02645; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.02646; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v22647; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.02648; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32649; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.02650; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v32651; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v32652; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v42653; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v52654; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v42655; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02656; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v12657; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v52658; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.02659; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 02660; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v02661; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.02662; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v22663; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.02664; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32665; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.02666; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v32667; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v32668; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v42669; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v52670; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v42671; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02672; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v52673; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.02674; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v12675; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]2676;2677; GFX8-LABEL: v_rcp_v2f16_arcp:2678; GFX8: ; %bb.0:2679; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2680; GFX8-NEXT: v_rcp_f16_e32 v1, v02681; GFX8-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_12682; GFX8-NEXT: v_or_b32_e32 v0, v1, v02683; GFX8-NEXT: s_setpc_b64 s[30:31]2684;2685; GFX9-LABEL: v_rcp_v2f16_arcp:2686; GFX9: ; %bb.0:2687; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2688; GFX9-NEXT: v_rcp_f16_e32 v1, v02689; GFX9-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12690; GFX9-NEXT: v_pack_b32_f16 v0, v1, v02691; GFX9-NEXT: s_setpc_b64 s[30:31]2692;2693; GFX10-LABEL: v_rcp_v2f16_arcp:2694; GFX10: ; %bb.0:2695; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2696; GFX10-NEXT: v_rcp_f16_e32 v1, v02697; GFX10-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12698; GFX10-NEXT: v_pack_b32_f16 v0, v1, v02699; GFX10-NEXT: s_setpc_b64 s[30:31]2700;2701; GFX11-LABEL: v_rcp_v2f16_arcp:2702; GFX11: ; %bb.0:2703; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2704; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v02705; GFX11-NEXT: v_rcp_f16_e32 v0, v02706; GFX11-NEXT: v_rcp_f16_e32 v1, v12707; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2708; GFX11-NEXT: v_pack_b32_f16 v0, v0, v12709; GFX11-NEXT: s_setpc_b64 s[30:31]2710 %fdiv = fdiv arcp <2 x half> <half 1.0, half 1.0>, %x2711 ret <2 x half> %fdiv2712}2713 2714define <2 x half> @v_rcp_v2f16_arcp_afn(<2 x half> %x) {2715; GFX6-LABEL: v_rcp_v2f16_arcp_afn:2716; GFX6: ; %bb.0:2717; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2718; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v02719; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v12720; GFX6-NEXT: v_rcp_f32_e32 v0, v02721; GFX6-NEXT: v_rcp_f32_e32 v1, v12722; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v02723; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v12724; GFX6-NEXT: s_setpc_b64 s[30:31]2725;2726; GFX8-LABEL: v_rcp_v2f16_arcp_afn:2727; GFX8: ; %bb.0:2728; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2729; GFX8-NEXT: v_rcp_f16_e32 v1, v02730; GFX8-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_12731; GFX8-NEXT: v_or_b32_e32 v0, v1, v02732; GFX8-NEXT: s_setpc_b64 s[30:31]2733;2734; GFX9-LABEL: v_rcp_v2f16_arcp_afn:2735; GFX9: ; %bb.0:2736; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2737; GFX9-NEXT: v_rcp_f16_e32 v1, v02738; GFX9-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12739; GFX9-NEXT: v_pack_b32_f16 v0, v1, v02740; GFX9-NEXT: s_setpc_b64 s[30:31]2741;2742; GFX10-LABEL: v_rcp_v2f16_arcp_afn:2743; GFX10: ; %bb.0:2744; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2745; GFX10-NEXT: v_rcp_f16_e32 v1, v02746; GFX10-NEXT: v_rcp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_12747; GFX10-NEXT: v_pack_b32_f16 v0, v1, v02748; GFX10-NEXT: s_setpc_b64 s[30:31]2749;2750; GFX11-LABEL: v_rcp_v2f16_arcp_afn:2751; GFX11: ; %bb.0:2752; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2753; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v02754; GFX11-NEXT: v_rcp_f16_e32 v0, v02755; GFX11-NEXT: v_rcp_f16_e32 v1, v12756; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2757; GFX11-NEXT: v_pack_b32_f16 v0, v0, v12758; GFX11-NEXT: s_setpc_b64 s[30:31]2759 %fdiv = fdiv arcp afn <2 x half> <half 1.0, half 1.0>, %x2760 ret <2 x half> %fdiv2761}2762 2763define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) {2764; GFX6-IEEE-LABEL: v_rcp_v2f16_ulp25:2765; GFX6-IEEE: ; %bb.0:2766; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2767; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v02768; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v12769; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.02770; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v22771; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.02772; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.02773; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v32774; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v32775; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v42776; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v52777; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v42778; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v52779; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.02780; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.02781; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v22782; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.02783; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v02784; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.02785; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v32786; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v32787; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v42788; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v52789; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v42790; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v52791; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, 1.02792; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v12793; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]2794;2795; GFX6-FLUSH-LABEL: v_rcp_v2f16_ulp25:2796; GFX6-FLUSH: ; %bb.0:2797; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2798; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v02799; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.02800; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v22801; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.02802; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32803; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.02804; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v32805; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v32806; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v42807; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v52808; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v42809; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02810; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v12811; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v52812; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.02813; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 02814; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v02815; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.02816; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v22817; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.02818; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32819; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.02820; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v32821; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v32822; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v42823; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v52824; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v42825; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02826; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v52827; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.02828; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v12829; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]2830;2831; GFX8-IEEE-LABEL: v_rcp_v2f16_ulp25:2832; GFX8-IEEE: ; %bb.0:2833; GFX8-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2834; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v02835; GFX8-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v02836; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v22837; GFX8-IEEE-NEXT: v_rcp_f32_e32 v4, v12838; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v32839; GFX8-IEEE-NEXT: v_mul_f32_e64 v6, -v1, v42840; GFX8-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v62841; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v42842; GFX8-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v52843; GFX8-IEEE-NEXT: v_add_f32_e32 v6, v6, v42844; GFX8-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v72845; GFX8-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v62846; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v52847; GFX8-IEEE-NEXT: v_add_f32_e32 v1, 1.0, v12848; GFX8-IEEE-NEXT: v_mul_f32_e32 v1, v1, v42849; GFX8-IEEE-NEXT: v_add_f32_e32 v4, v7, v52850; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v42851; GFX8-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v32852; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v52853; GFX8-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v12854; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v32855; GFX8-IEEE-NEXT: v_add_f32_e32 v1, v1, v62856; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v42857; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v12858; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v32859; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, 1.02860; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, 1.02861; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v12862; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v12863; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]2864;2865; GFX8-FLUSH-LABEL: v_rcp_v2f16_ulp25:2866; GFX8-FLUSH: ; %bb.0:2867; GFX8-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2868; GFX8-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v02869; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v02870; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v22871; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v4, v12872; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v32873; GFX8-FLUSH-NEXT: v_mad_f32 v6, -v1, v4, 1.02874; GFX8-FLUSH-NEXT: v_mad_f32 v7, -v3, v5, 1.02875; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, v42876; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, v52877; GFX8-FLUSH-NEXT: v_mad_f32 v1, -v1, v6, 1.02878; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, 1.02879; GFX8-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v42880; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v52881; GFX8-FLUSH-NEXT: v_and_b32_e32 v1, 0xff800000, v12882; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v32883; GFX8-FLUSH-NEXT: v_add_f32_e32 v1, v1, v62884; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v72885; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v12886; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v32887; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, 1.02888; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, 1.02889; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v12890; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v12891; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]2892;2893; GFX9-IEEE-LABEL: v_rcp_v2f16_ulp25:2894; GFX9-IEEE: ; %bb.0:2895; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2896; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v02897; GFX9-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v02898; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v22899; GFX9-IEEE-NEXT: v_rcp_f32_e32 v4, v12900; GFX9-IEEE-NEXT: v_rcp_f32_e32 v5, v32901; GFX9-IEEE-NEXT: v_mul_f32_e64 v6, -v1, v42902; GFX9-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v62903; GFX9-IEEE-NEXT: v_mul_f32_e32 v6, v6, v42904; GFX9-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v52905; GFX9-IEEE-NEXT: v_add_f32_e32 v6, v6, v42906; GFX9-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v72907; GFX9-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v62908; GFX9-IEEE-NEXT: v_mul_f32_e32 v7, v7, v52909; GFX9-IEEE-NEXT: v_add_f32_e32 v1, 1.0, v12910; GFX9-IEEE-NEXT: v_mul_f32_e32 v1, v1, v42911; GFX9-IEEE-NEXT: v_add_f32_e32 v4, v7, v52912; GFX9-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v42913; GFX9-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v32914; GFX9-IEEE-NEXT: v_mul_f32_e32 v3, v3, v52915; GFX9-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v12916; GFX9-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v32917; GFX9-IEEE-NEXT: v_add_f32_e32 v1, v1, v62918; GFX9-IEEE-NEXT: v_add_f32_e32 v3, v3, v42919; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v12920; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v32921; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, 1.02922; GFX9-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, 1.02923; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v0, v12924; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31]2925;2926; GFX9-FLUSH-LABEL: v_rcp_v2f16_ulp25:2927; GFX9-FLUSH: ; %bb.0:2928; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2929; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v02930; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v02931; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v22932; GFX9-FLUSH-NEXT: v_mov_b32_e32 v4, 1.02933; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v1, v12934; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v3, v32935; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, -v0, v1, v4 op_sel_hi:[1,0,0]2936; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v0, v3, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]2937; GFX9-FLUSH-NEXT: v_mad_f32 v5, v5, v1, v12938; GFX9-FLUSH-NEXT: v_mad_f32 v6, v6, v3, v32939; GFX9-FLUSH-NEXT: v_mad_mix_f32 v7, -v0, v5, v4 op_sel_hi:[1,0,0]2940; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v0, v6, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]2941; GFX9-FLUSH-NEXT: v_mul_f32_e32 v1, v7, v12942; GFX9-FLUSH-NEXT: v_mul_f32_e32 v3, v4, v32943; GFX9-FLUSH-NEXT: v_and_b32_e32 v1, 0xff800000, v12944; GFX9-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v32945; GFX9-FLUSH-NEXT: v_add_f32_e32 v1, v1, v52946; GFX9-FLUSH-NEXT: v_add_f32_e32 v3, v3, v62947; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v12948; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v32949; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, 1.02950; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, 1.02951; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v12952; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31]2953;2954; GFX10-IEEE-LABEL: v_rcp_v2f16_ulp25:2955; GFX10-IEEE: ; %bb.0:2956; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2957; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v02958; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v02959; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v12960; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v22961; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v32962; GFX10-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v42963; GFX10-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v52964; GFX10-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v62965; GFX10-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v72966; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v42967; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v7, v52968; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v6, v42969; GFX10-IEEE-NEXT: v_add_f32_e32 v7, v7, v52970; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v62971; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v72972; GFX10-IEEE-NEXT: v_add_f32_e32 v2, 1.0, v22973; GFX10-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v32974; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v42975; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v52976; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v22977; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v32978; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v62979; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v72980; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v22981; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v32982; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v0, 1.02983; GFX10-IEEE-NEXT: v_div_fixup_f16 v1, v3, v1, 1.02984; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v0, v12985; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]2986;2987; GFX10-FLUSH-LABEL: v_rcp_v2f16_ulp25:2988; GFX10-FLUSH: ; %bb.0:2989; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2990; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v1, 16, v02991; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v02992; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v12993; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v4, v22994; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v32995; GFX10-FLUSH-NEXT: v_mad_f32 v6, -v2, v4, 1.02996; GFX10-FLUSH-NEXT: v_mad_f32 v7, -v3, v5, 1.02997; GFX10-FLUSH-NEXT: v_mad_f32 v6, v6, v4, v42998; GFX10-FLUSH-NEXT: v_mad_f32 v7, v7, v5, v52999; GFX10-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, 1.03000; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, 1.03001; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v43002; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v53003; GFX10-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v23004; GFX10-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v33005; GFX10-FLUSH-NEXT: v_add_f32_e32 v2, v2, v63006; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v73007; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v23008; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v33009; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v0, 1.03010; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v1, 1.03011; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v13012; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]3013;3014; GFX11-LABEL: v_rcp_v2f16_ulp25:3015; GFX11: ; %bb.0:3016; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3017; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v03018; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v03019; GFX11-NEXT: v_mov_b32_e32 v4, 1.03020; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v13021; GFX11-NEXT: v_rcp_f32_e32 v2, v23022; GFX11-NEXT: v_rcp_f32_e32 v3, v33023; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3024; GFX11-NEXT: v_fma_mix_f32 v5, -v0, v2, v4 op_sel_hi:[1,0,0]3025; GFX11-NEXT: v_fma_mix_f32 v6, -v0, v3, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]3026; GFX11-NEXT: v_fma_f32 v5, v5, v2, v23027; GFX11-NEXT: v_fma_f32 v6, v6, v3, v33028; GFX11-NEXT: v_fma_mix_f32 v7, -v0, v5, v4 op_sel_hi:[1,0,0]3029; GFX11-NEXT: v_fma_mix_f32 v4, -v0, v6, v4 op_sel:[1,0,0] op_sel_hi:[1,0,0]3030; GFX11-NEXT: v_dual_mul_f32 v2, v7, v2 :: v_dual_mul_f32 v3, v4, v33031; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v23032; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_and_b32 v3, 0xff800000, v33033; GFX11-NEXT: v_add_f32_e32 v3, v3, v63034; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v23035; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v33036; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, 1.03037; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, 1.03038; GFX11-NEXT: v_pack_b32_f16 v0, v0, v13039; GFX11-NEXT: s_setpc_b64 s[30:31]3040 %fdiv = fdiv <2 x half> <half 1.0, half 1.0>, %x3041 ret <2 x half> %fdiv3042}3043 3044define <2 x half> @v_fdiv_v2f16_afn_ulp25(<2 x half> %a, <2 x half> %b) {3045; GFX6-LABEL: v_fdiv_v2f16_afn_ulp25:3046; GFX6: ; %bb.0:3047; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3048; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v23049; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v33050; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v03051; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v13052; GFX6-NEXT: v_rcp_f32_e32 v2, v23053; GFX6-NEXT: v_rcp_f32_e32 v3, v33054; GFX6-NEXT: v_mul_f32_e32 v0, v0, v23055; GFX6-NEXT: v_mul_f32_e32 v1, v1, v33056; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v03057; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v13058; GFX6-NEXT: s_setpc_b64 s[30:31]3059;3060; GFX8-LABEL: v_fdiv_v2f16_afn_ulp25:3061; GFX8: ; %bb.0:3062; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3063; GFX8-NEXT: v_rcp_f16_e32 v2, v13064; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_13065; GFX8-NEXT: v_mul_f16_e32 v2, v0, v23066; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3067; GFX8-NEXT: v_or_b32_e32 v0, v2, v03068; GFX8-NEXT: s_setpc_b64 s[30:31]3069;3070; GFX9-LABEL: v_fdiv_v2f16_afn_ulp25:3071; GFX9: ; %bb.0:3072; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3073; GFX9-NEXT: v_rcp_f16_e32 v2, v13074; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_13075; GFX9-NEXT: v_mul_f16_e32 v2, v0, v23076; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3077; GFX9-NEXT: v_pack_b32_f16 v0, v2, v03078; GFX9-NEXT: s_setpc_b64 s[30:31]3079;3080; GFX10-LABEL: v_fdiv_v2f16_afn_ulp25:3081; GFX10: ; %bb.0:3082; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3083; GFX10-NEXT: v_rcp_f16_e32 v2, v13084; GFX10-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_13085; GFX10-NEXT: v_mul_f16_e32 v2, v0, v23086; GFX10-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3087; GFX10-NEXT: v_pack_b32_f16 v0, v2, v03088; GFX10-NEXT: s_setpc_b64 s[30:31]3089;3090; GFX11-LABEL: v_fdiv_v2f16_afn_ulp25:3091; GFX11: ; %bb.0:3092; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3093; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v13094; GFX11-NEXT: v_rcp_f16_e32 v1, v13095; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v03096; GFX11-NEXT: v_rcp_f16_e32 v2, v23097; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3098; GFX11-NEXT: v_mul_f16_e32 v0, v0, v13099; GFX11-NEXT: v_mul_f16_e32 v1, v3, v23100; GFX11-NEXT: v_pack_b32_f16 v0, v0, v13101; GFX11-NEXT: s_setpc_b64 s[30:31]3102 %fdiv = fdiv afn <2 x half> %a, %b3103 ret <2 x half> %fdiv3104}3105 3106define <2 x half> @v_fdiv_v2f16_arcp_ulp25(<2 x half> %a, <2 x half> %b) {3107; GFX6-IEEE-LABEL: v_fdiv_v2f16_arcp_ulp25:3108; GFX6-IEEE: ; %bb.0:3109; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3110; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v03111; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v23112; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v13113; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v33114; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v03115; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v43116; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v03117; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.03118; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v53119; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v53120; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v63121; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v73122; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v63123; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v73124; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v03125; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v13126; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v23127; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v13128; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v03129; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.03130; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v4, v43131; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v43132; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v6, v53133; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v63134; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v53135; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v63136; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v13137; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v13138; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]3139;3140; GFX6-FLUSH-LABEL: v_fdiv_v2f16_arcp_ulp25:3141; GFX6-FLUSH: ; %bb.0:3142; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3143; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v03144; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v23145; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v03146; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v43147; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v03148; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33149; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.03150; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v53151; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v53152; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v63153; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v73154; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v63155; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 03156; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v13157; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v33158; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v73159; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v03160; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 03161; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v03162; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v3, v3, v13163; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v23164; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v1, v3, v13165; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33166; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v4, 1.03167; GFX6-FLUSH-NEXT: v_fma_f32 v4, v6, v4, v43168; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v43169; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v2, v6, v53170; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v63171; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v6, v53172; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 03173; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v63174; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v13175; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v13176; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]3177;3178; GFX8-LABEL: v_fdiv_v2f16_arcp_ulp25:3179; GFX8: ; %bb.0:3180; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3181; GFX8-NEXT: v_rcp_f16_e32 v2, v13182; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_13183; GFX8-NEXT: v_mul_f16_e32 v2, v0, v23184; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3185; GFX8-NEXT: v_or_b32_e32 v0, v2, v03186; GFX8-NEXT: s_setpc_b64 s[30:31]3187;3188; GFX9-LABEL: v_fdiv_v2f16_arcp_ulp25:3189; GFX9: ; %bb.0:3190; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3191; GFX9-NEXT: v_rcp_f16_e32 v2, v13192; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_13193; GFX9-NEXT: v_mul_f16_e32 v2, v0, v23194; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3195; GFX9-NEXT: v_pack_b32_f16 v0, v2, v03196; GFX9-NEXT: s_setpc_b64 s[30:31]3197;3198; GFX10-LABEL: v_fdiv_v2f16_arcp_ulp25:3199; GFX10: ; %bb.0:3200; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3201; GFX10-NEXT: v_rcp_f16_e32 v2, v13202; GFX10-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_13203; GFX10-NEXT: v_mul_f16_e32 v2, v0, v23204; GFX10-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3205; GFX10-NEXT: v_pack_b32_f16 v0, v2, v03206; GFX10-NEXT: s_setpc_b64 s[30:31]3207;3208; GFX11-LABEL: v_fdiv_v2f16_arcp_ulp25:3209; GFX11: ; %bb.0:3210; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3211; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v13212; GFX11-NEXT: v_rcp_f16_e32 v1, v13213; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v03214; GFX11-NEXT: v_rcp_f16_e32 v2, v23215; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3216; GFX11-NEXT: v_mul_f16_e32 v0, v0, v13217; GFX11-NEXT: v_mul_f16_e32 v1, v3, v23218; GFX11-NEXT: v_pack_b32_f16 v0, v0, v13219; GFX11-NEXT: s_setpc_b64 s[30:31]3220 %fdiv = fdiv arcp <2 x half> %a, %b3221 ret <2 x half> %fdiv3222}3223 3224define <2 x half> @v_fdiv_v2f16_arcp_afn_ulp25(<2 x half> %a, <2 x half> %b) {3225; GFX6-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:3226; GFX6: ; %bb.0:3227; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3228; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v23229; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v33230; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v03231; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v13232; GFX6-NEXT: v_rcp_f32_e32 v2, v23233; GFX6-NEXT: v_rcp_f32_e32 v3, v33234; GFX6-NEXT: v_mul_f32_e32 v0, v0, v23235; GFX6-NEXT: v_mul_f32_e32 v1, v1, v33236; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v03237; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v13238; GFX6-NEXT: s_setpc_b64 s[30:31]3239;3240; GFX8-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:3241; GFX8: ; %bb.0:3242; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3243; GFX8-NEXT: v_rcp_f16_e32 v2, v13244; GFX8-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_13245; GFX8-NEXT: v_mul_f16_e32 v2, v0, v23246; GFX8-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3247; GFX8-NEXT: v_or_b32_e32 v0, v2, v03248; GFX8-NEXT: s_setpc_b64 s[30:31]3249;3250; GFX9-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:3251; GFX9: ; %bb.0:3252; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3253; GFX9-NEXT: v_rcp_f16_e32 v2, v13254; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_13255; GFX9-NEXT: v_mul_f16_e32 v2, v0, v23256; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3257; GFX9-NEXT: v_pack_b32_f16 v0, v2, v03258; GFX9-NEXT: s_setpc_b64 s[30:31]3259;3260; GFX10-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:3261; GFX10: ; %bb.0:3262; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3263; GFX10-NEXT: v_rcp_f16_e32 v2, v13264; GFX10-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_13265; GFX10-NEXT: v_mul_f16_e32 v2, v0, v23266; GFX10-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3267; GFX10-NEXT: v_pack_b32_f16 v0, v2, v03268; GFX10-NEXT: s_setpc_b64 s[30:31]3269;3270; GFX11-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:3271; GFX11: ; %bb.0:3272; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3273; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v13274; GFX11-NEXT: v_rcp_f16_e32 v1, v13275; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v03276; GFX11-NEXT: v_rcp_f16_e32 v2, v23277; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3278; GFX11-NEXT: v_mul_f16_e32 v0, v0, v13279; GFX11-NEXT: v_mul_f16_e32 v1, v3, v23280; GFX11-NEXT: v_pack_b32_f16 v0, v0, v13281; GFX11-NEXT: s_setpc_b64 s[30:31]3282 %fdiv = fdiv afn arcp <2 x half> %a, %b3283 ret <2 x half> %fdiv3284}3285 3286define amdgpu_ps i16 @s_fdiv_f16(i16 inreg %a.arg, i16 inreg %b.arg) {3287; GFX6-IEEE-LABEL: s_fdiv_f16:3288; GFX6-IEEE: ; %bb.0:3289; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s03290; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, s13291; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[0:1], v1, v1, v03292; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v23293; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v03294; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.03295; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v33296; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v33297; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v43298; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v53299; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v43300; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v53301; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v03302; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v03303; GFX6-IEEE-NEXT: v_readfirstlane_b32 s0, v03304; GFX6-IEEE-NEXT: ; return to shader part epilog3305;3306; GFX6-FLUSH-LABEL: s_fdiv_f16:3307; GFX6-FLUSH: ; %bb.0:3308; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s03309; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s13310; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[0:1], v1, v1, v03311; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v23312; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v03313; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33314; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.03315; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v33316; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v33317; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v43318; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v53319; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v43320; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 03321; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v53322; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v03323; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 03324; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v03325; GFX6-FLUSH-NEXT: v_readfirstlane_b32 s0, v03326; GFX6-FLUSH-NEXT: ; return to shader part epilog3327;3328; GFX8-IEEE-LABEL: s_fdiv_f16:3329; GFX8-IEEE: ; %bb.0:3330; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s13331; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v1, s03332; GFX8-IEEE-NEXT: v_rcp_f32_e32 v2, v03333; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v1, v23334; GFX8-IEEE-NEXT: v_mul_f32_e64 v4, -v0, v33335; GFX8-IEEE-NEXT: v_add_f32_e32 v4, v4, v13336; GFX8-IEEE-NEXT: v_mul_f32_e32 v4, v4, v23337; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v4, v33338; GFX8-IEEE-NEXT: v_mul_f32_e64 v0, -v0, v33339; GFX8-IEEE-NEXT: v_add_f32_e32 v0, v0, v13340; GFX8-IEEE-NEXT: v_mul_f32_e32 v0, v0, v23341; GFX8-IEEE-NEXT: v_and_b32_e32 v0, 0xff800000, v03342; GFX8-IEEE-NEXT: v_add_f32_e32 v0, v0, v33343; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v03344; GFX8-IEEE-NEXT: v_mov_b32_e32 v1, s13345; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v0, v1, s03346; GFX8-IEEE-NEXT: v_readfirstlane_b32 s0, v03347; GFX8-IEEE-NEXT: ; return to shader part epilog3348;3349; GFX8-FLUSH-LABEL: s_fdiv_f16:3350; GFX8-FLUSH: ; %bb.0:3351; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s13352; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s03353; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v2, v03354; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v1, v23355; GFX8-FLUSH-NEXT: v_mad_f32 v4, -v0, v3, v13356; GFX8-FLUSH-NEXT: v_mac_f32_e32 v3, v4, v23357; GFX8-FLUSH-NEXT: v_mad_f32 v0, -v0, v3, v13358; GFX8-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v23359; GFX8-FLUSH-NEXT: v_and_b32_e32 v0, 0xff800000, v03360; GFX8-FLUSH-NEXT: v_add_f32_e32 v0, v0, v33361; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v03362; GFX8-FLUSH-NEXT: v_mov_b32_e32 v1, s13363; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v0, v1, s03364; GFX8-FLUSH-NEXT: v_readfirstlane_b32 s0, v03365; GFX8-FLUSH-NEXT: ; return to shader part epilog3366;3367; GFX9-IEEE-LABEL: s_fdiv_f16:3368; GFX9-IEEE: ; %bb.0:3369; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s13370; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v1, s03371; GFX9-IEEE-NEXT: v_rcp_f32_e32 v2, v03372; GFX9-IEEE-NEXT: v_mul_f32_e32 v3, v1, v23373; GFX9-IEEE-NEXT: v_mul_f32_e64 v4, -v0, v33374; GFX9-IEEE-NEXT: v_add_f32_e32 v4, v4, v13375; GFX9-IEEE-NEXT: v_mul_f32_e32 v4, v4, v23376; GFX9-IEEE-NEXT: v_add_f32_e32 v3, v4, v33377; GFX9-IEEE-NEXT: v_mul_f32_e64 v0, -v0, v33378; GFX9-IEEE-NEXT: v_add_f32_e32 v0, v0, v13379; GFX9-IEEE-NEXT: v_mul_f32_e32 v0, v0, v23380; GFX9-IEEE-NEXT: v_and_b32_e32 v0, 0xff800000, v03381; GFX9-IEEE-NEXT: v_add_f32_e32 v0, v0, v33382; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v03383; GFX9-IEEE-NEXT: v_mov_b32_e32 v1, s13384; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v0, v1, s03385; GFX9-IEEE-NEXT: v_readfirstlane_b32 s0, v03386; GFX9-IEEE-NEXT: ; return to shader part epilog3387;3388; GFX9-FLUSH-LABEL: s_fdiv_f16:3389; GFX9-FLUSH: ; %bb.0:3390; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s13391; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s03392; GFX9-FLUSH-NEXT: v_mov_b32_e32 v2, s13393; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v0, v03394; GFX9-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v03395; GFX9-FLUSH-NEXT: v_mad_mix_f32 v3, -v2, v1, s0 op_sel_hi:[1,0,1]3396; GFX9-FLUSH-NEXT: v_mac_f32_e32 v1, v3, v03397; GFX9-FLUSH-NEXT: v_mad_mix_f32 v3, -v2, v1, s0 op_sel_hi:[1,0,1]3398; GFX9-FLUSH-NEXT: v_mul_f32_e32 v0, v3, v03399; GFX9-FLUSH-NEXT: v_and_b32_e32 v0, 0xff800000, v03400; GFX9-FLUSH-NEXT: v_add_f32_e32 v0, v0, v13401; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v03402; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v0, v2, s03403; GFX9-FLUSH-NEXT: v_readfirstlane_b32 s0, v03404; GFX9-FLUSH-NEXT: ; return to shader part epilog3405;3406; GFX10-IEEE-LABEL: s_fdiv_f16:3407; GFX10-IEEE: ; %bb.0:3408; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s13409; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, s03410; GFX10-IEEE-NEXT: v_rcp_f32_e32 v1, v03411; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v2, v13412; GFX10-IEEE-NEXT: v_mul_f32_e64 v4, -v0, v33413; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v23414; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v4, v13415; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v4, v33416; GFX10-IEEE-NEXT: v_mul_f32_e64 v0, -v0, v33417; GFX10-IEEE-NEXT: v_add_f32_e32 v0, v0, v23418; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v0, v13419; GFX10-IEEE-NEXT: v_and_b32_e32 v0, 0xff800000, v03420; GFX10-IEEE-NEXT: v_add_f32_e32 v0, v0, v33421; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v03422; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v0, s1, s03423; GFX10-IEEE-NEXT: v_readfirstlane_b32 s0, v03424; GFX10-IEEE-NEXT: ; return to shader part epilog3425;3426; GFX10-FLUSH-LABEL: s_fdiv_f16:3427; GFX10-FLUSH: ; %bb.0:3428; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s13429; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, s03430; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v1, v03431; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v2, v13432; GFX10-FLUSH-NEXT: v_mad_f32 v4, -v0, v3, v23433; GFX10-FLUSH-NEXT: v_mac_f32_e32 v3, v4, v13434; GFX10-FLUSH-NEXT: v_mad_f32 v0, -v0, v3, v23435; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v13436; GFX10-FLUSH-NEXT: v_and_b32_e32 v0, 0xff800000, v03437; GFX10-FLUSH-NEXT: v_add_f32_e32 v0, v0, v33438; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v03439; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v0, s1, s03440; GFX10-FLUSH-NEXT: v_readfirstlane_b32 s0, v03441; GFX10-FLUSH-NEXT: ; return to shader part epilog3442;3443; GFX11-LABEL: s_fdiv_f16:3444; GFX11: ; %bb.0:3445; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s13446; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s03447; GFX11-NEXT: v_rcp_f32_e32 v0, v03448; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3449; GFX11-NEXT: v_mul_f32_e32 v1, v1, v03450; GFX11-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]3451; GFX11-NEXT: v_fmac_f32_e32 v1, v2, v03452; GFX11-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1]3453; GFX11-NEXT: v_mul_f32_e32 v0, v2, v03454; GFX11-NEXT: v_and_b32_e32 v0, 0xff800000, v03455; GFX11-NEXT: v_add_f32_e32 v0, v0, v13456; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v03457; GFX11-NEXT: v_div_fixup_f16 v0, v0, s1, s03458; GFX11-NEXT: v_readfirstlane_b32 s0, v03459; GFX11-NEXT: ; return to shader part epilog3460 %a = bitcast i16 %a.arg to half3461 %b = bitcast i16 %b.arg to half3462 %fdiv = fdiv half %a, %b3463 %result = bitcast half %fdiv to i163464 ret i16 %result3465}3466 3467define amdgpu_ps i16 @s_fdiv_f16_arcp(i16 inreg %a.arg, i16 inreg %b.arg) {3468; GFX6-IEEE-LABEL: s_fdiv_f16_arcp:3469; GFX6-IEEE: ; %bb.0:3470; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s03471; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, s13472; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[0:1], v1, v1, v03473; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v23474; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v03475; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.03476; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v33477; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v33478; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v43479; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v53480; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v43481; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v53482; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v03483; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v03484; GFX6-IEEE-NEXT: v_readfirstlane_b32 s0, v03485; GFX6-IEEE-NEXT: ; return to shader part epilog3486;3487; GFX6-FLUSH-LABEL: s_fdiv_f16_arcp:3488; GFX6-FLUSH: ; %bb.0:3489; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s03490; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s13491; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[0:1], v1, v1, v03492; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v23493; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v03494; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33495; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.03496; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v33497; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v33498; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v43499; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v53500; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v43501; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 03502; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v53503; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v03504; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 03505; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v03506; GFX6-FLUSH-NEXT: v_readfirstlane_b32 s0, v03507; GFX6-FLUSH-NEXT: ; return to shader part epilog3508;3509; GFX89-LABEL: s_fdiv_f16_arcp:3510; GFX89: ; %bb.0:3511; GFX89-NEXT: v_rcp_f16_e32 v0, s13512; GFX89-NEXT: v_mul_f16_e32 v0, s0, v03513; GFX89-NEXT: v_readfirstlane_b32 s0, v03514; GFX89-NEXT: ; return to shader part epilog3515;3516; GFX10-LABEL: s_fdiv_f16_arcp:3517; GFX10: ; %bb.0:3518; GFX10-NEXT: v_rcp_f16_e32 v0, s13519; GFX10-NEXT: v_mul_f16_e32 v0, s0, v03520; GFX10-NEXT: v_readfirstlane_b32 s0, v03521; GFX10-NEXT: ; return to shader part epilog3522;3523; GFX11-LABEL: s_fdiv_f16_arcp:3524; GFX11: ; %bb.0:3525; GFX11-NEXT: v_rcp_f16_e32 v0, s13526; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3527; GFX11-NEXT: v_mul_f16_e32 v0, s0, v03528; GFX11-NEXT: v_readfirstlane_b32 s0, v03529; GFX11-NEXT: ; return to shader part epilog3530 %a = bitcast i16 %a.arg to half3531 %b = bitcast i16 %b.arg to half3532 %fdiv = fdiv arcp half %a, %b3533 %result = bitcast half %fdiv to i163534 ret i16 %result3535}3536 3537define amdgpu_ps i16 @s_fdiv_f16_afn(i16 inreg %a.arg, i16 inreg %b.arg) {3538; GFX6-LABEL: s_fdiv_f16_afn:3539; GFX6: ; %bb.0:3540; GFX6-NEXT: v_cvt_f32_f16_e32 v0, s13541; GFX6-NEXT: v_cvt_f32_f16_e32 v1, s03542; GFX6-NEXT: v_rcp_f32_e32 v0, v03543; GFX6-NEXT: v_mul_f32_e32 v0, v1, v03544; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v03545; GFX6-NEXT: v_readfirstlane_b32 s0, v03546; GFX6-NEXT: ; return to shader part epilog3547;3548; GFX89-LABEL: s_fdiv_f16_afn:3549; GFX89: ; %bb.0:3550; GFX89-NEXT: v_rcp_f16_e32 v0, s13551; GFX89-NEXT: v_mul_f16_e32 v0, s0, v03552; GFX89-NEXT: v_readfirstlane_b32 s0, v03553; GFX89-NEXT: ; return to shader part epilog3554;3555; GFX10-LABEL: s_fdiv_f16_afn:3556; GFX10: ; %bb.0:3557; GFX10-NEXT: v_rcp_f16_e32 v0, s13558; GFX10-NEXT: v_mul_f16_e32 v0, s0, v03559; GFX10-NEXT: v_readfirstlane_b32 s0, v03560; GFX10-NEXT: ; return to shader part epilog3561;3562; GFX11-LABEL: s_fdiv_f16_afn:3563; GFX11: ; %bb.0:3564; GFX11-NEXT: v_rcp_f16_e32 v0, s13565; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3566; GFX11-NEXT: v_mul_f16_e32 v0, s0, v03567; GFX11-NEXT: v_readfirstlane_b32 s0, v03568; GFX11-NEXT: ; return to shader part epilog3569 %a = bitcast i16 %a.arg to half3570 %b = bitcast i16 %b.arg to half3571 %fdiv = fdiv afn half %a, %b3572 %result = bitcast half %fdiv to i163573 ret i16 %result3574}3575 3576define amdgpu_ps i32 @s_fdiv_v2f16(i32 inreg %a.arg, i32 inreg %b.arg) {3577; GFX6-IEEE-LABEL: s_fdiv_v2f16:3578; GFX6-IEEE: ; %bb.0:3579; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s03580; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, s13581; GFX6-IEEE-NEXT: s_lshr_b32 s0, s0, 163582; GFX6-IEEE-NEXT: s_lshr_b32 s1, s1, 163583; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v03584; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v23585; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v03586; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.03587; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v33588; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v33589; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v43590; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v53591; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v43592; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v4, s03593; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v6, s13594; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v53595; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v03596; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v03597; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[0:1], v6, v6, v43598; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v33599; GFX6-IEEE-NEXT: v_div_scale_f32 v1, vcc, v4, v6, v43600; GFX6-IEEE-NEXT: v_fma_f32 v2, -v3, v5, 1.03601; GFX6-IEEE-NEXT: v_fma_f32 v2, v2, v5, v53602; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v1, v23603; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v5, v13604; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v2, v53605; GFX6-IEEE-NEXT: v_fma_f32 v1, -v3, v5, v13606; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v53607; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v1, v6, v43608; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v13609; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v13610; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v0, v13611; GFX6-IEEE-NEXT: v_readfirstlane_b32 s0, v03612; GFX6-IEEE-NEXT: ; return to shader part epilog3613;3614; GFX6-FLUSH-LABEL: s_fdiv_v2f16:3615; GFX6-FLUSH: ; %bb.0:3616; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s03617; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s13618; GFX6-FLUSH-NEXT: s_lshr_b32 s0, s0, 163619; GFX6-FLUSH-NEXT: s_lshr_b32 s1, s1, 163620; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v03621; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v23622; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v03623; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33624; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.03625; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v33626; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v33627; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v43628; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v53629; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v43630; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 03631; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v53632; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, s03633; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s13634; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v03635; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 03636; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v03637; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[0:1], v4, v4, v33638; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v13639; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v3, v4, v33640; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33641; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v1, v2, 1.03642; GFX6-FLUSH-NEXT: v_fma_f32 v2, v6, v2, v23643; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v5, v23644; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v1, v6, v53645; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v2, v63646; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v6, v53647; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 03648; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v63649; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v1, v4, v33650; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v13651; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v13652; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v0, v13653; GFX6-FLUSH-NEXT: v_readfirstlane_b32 s0, v03654; GFX6-FLUSH-NEXT: ; return to shader part epilog3655;3656; GFX8-IEEE-LABEL: s_fdiv_v2f16:3657; GFX8-IEEE: ; %bb.0:3658; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s13659; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v1, s03660; GFX8-IEEE-NEXT: s_lshr_b32 s3, s1, 163661; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v4, s33662; GFX8-IEEE-NEXT: v_rcp_f32_e32 v2, v03663; GFX8-IEEE-NEXT: s_lshr_b32 s2, s0, 163664; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v3, s23665; GFX8-IEEE-NEXT: v_mul_f32_e32 v5, v1, v23666; GFX8-IEEE-NEXT: v_mul_f32_e64 v6, -v0, v53667; GFX8-IEEE-NEXT: v_add_f32_e32 v6, v6, v13668; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v23669; GFX8-IEEE-NEXT: v_add_f32_e32 v5, v6, v53670; GFX8-IEEE-NEXT: v_mul_f32_e64 v0, -v0, v53671; GFX8-IEEE-NEXT: v_add_f32_e32 v0, v0, v13672; GFX8-IEEE-NEXT: v_rcp_f32_e32 v1, v43673; GFX8-IEEE-NEXT: v_mul_f32_e32 v0, v0, v23674; GFX8-IEEE-NEXT: v_and_b32_e32 v0, 0xff800000, v03675; GFX8-IEEE-NEXT: v_add_f32_e32 v0, v0, v53676; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v3, v13677; GFX8-IEEE-NEXT: v_mul_f32_e64 v5, -v4, v23678; GFX8-IEEE-NEXT: v_add_f32_e32 v5, v5, v33679; GFX8-IEEE-NEXT: v_mul_f32_e32 v5, v5, v13680; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v5, v23681; GFX8-IEEE-NEXT: v_mul_f32_e64 v4, -v4, v23682; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v4, v33683; GFX8-IEEE-NEXT: v_mul_f32_e32 v1, v3, v13684; GFX8-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v13685; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v03686; GFX8-IEEE-NEXT: v_add_f32_e32 v1, v1, v23687; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v13688; GFX8-IEEE-NEXT: v_mov_b32_e32 v2, s13689; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v0, v2, s03690; GFX8-IEEE-NEXT: v_mov_b32_e32 v2, s33691; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v1, v2, s23692; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v13693; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v13694; GFX8-IEEE-NEXT: v_readfirstlane_b32 s0, v03695; GFX8-IEEE-NEXT: ; return to shader part epilog3696;3697; GFX8-FLUSH-LABEL: s_fdiv_v2f16:3698; GFX8-FLUSH: ; %bb.0:3699; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s13700; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s03701; GFX8-FLUSH-NEXT: s_lshr_b32 s3, s1, 163702; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s33703; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v2, v03704; GFX8-FLUSH-NEXT: s_lshr_b32 s2, s0, 163705; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, s23706; GFX8-FLUSH-NEXT: v_mul_f32_e32 v5, v1, v23707; GFX8-FLUSH-NEXT: v_mad_f32 v6, -v0, v5, v13708; GFX8-FLUSH-NEXT: v_mac_f32_e32 v5, v6, v23709; GFX8-FLUSH-NEXT: v_mad_f32 v0, -v0, v5, v13710; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v1, v43711; GFX8-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v23712; GFX8-FLUSH-NEXT: v_and_b32_e32 v0, 0xff800000, v03713; GFX8-FLUSH-NEXT: v_add_f32_e32 v0, v0, v53714; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v13715; GFX8-FLUSH-NEXT: v_mad_f32 v5, -v4, v2, v33716; GFX8-FLUSH-NEXT: v_mac_f32_e32 v2, v5, v13717; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v4, v2, v33718; GFX8-FLUSH-NEXT: v_mul_f32_e32 v1, v3, v13719; GFX8-FLUSH-NEXT: v_and_b32_e32 v1, 0xff800000, v13720; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v03721; GFX8-FLUSH-NEXT: v_add_f32_e32 v1, v1, v23722; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v13723; GFX8-FLUSH-NEXT: v_mov_b32_e32 v2, s13724; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v0, v2, s03725; GFX8-FLUSH-NEXT: v_mov_b32_e32 v2, s33726; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v1, v2, s23727; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v13728; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v13729; GFX8-FLUSH-NEXT: v_readfirstlane_b32 s0, v03730; GFX8-FLUSH-NEXT: ; return to shader part epilog3731;3732; GFX9-IEEE-LABEL: s_fdiv_v2f16:3733; GFX9-IEEE: ; %bb.0:3734; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s13735; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v1, s03736; GFX9-IEEE-NEXT: s_lshr_b32 s3, s1, 163737; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v4, s33738; GFX9-IEEE-NEXT: v_rcp_f32_e32 v2, v03739; GFX9-IEEE-NEXT: s_lshr_b32 s2, s0, 163740; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v3, s23741; GFX9-IEEE-NEXT: v_mul_f32_e32 v5, v1, v23742; GFX9-IEEE-NEXT: v_mul_f32_e64 v6, -v0, v53743; GFX9-IEEE-NEXT: v_add_f32_e32 v6, v6, v13744; GFX9-IEEE-NEXT: v_mul_f32_e32 v6, v6, v23745; GFX9-IEEE-NEXT: v_add_f32_e32 v5, v6, v53746; GFX9-IEEE-NEXT: v_mul_f32_e64 v0, -v0, v53747; GFX9-IEEE-NEXT: v_add_f32_e32 v0, v0, v13748; GFX9-IEEE-NEXT: v_rcp_f32_e32 v1, v43749; GFX9-IEEE-NEXT: v_mul_f32_e32 v0, v0, v23750; GFX9-IEEE-NEXT: v_and_b32_e32 v0, 0xff800000, v03751; GFX9-IEEE-NEXT: v_add_f32_e32 v0, v0, v53752; GFX9-IEEE-NEXT: v_mul_f32_e32 v2, v3, v13753; GFX9-IEEE-NEXT: v_mul_f32_e64 v5, -v4, v23754; GFX9-IEEE-NEXT: v_add_f32_e32 v5, v5, v33755; GFX9-IEEE-NEXT: v_mul_f32_e32 v5, v5, v13756; GFX9-IEEE-NEXT: v_add_f32_e32 v2, v5, v23757; GFX9-IEEE-NEXT: v_mul_f32_e64 v4, -v4, v23758; GFX9-IEEE-NEXT: v_add_f32_e32 v3, v4, v33759; GFX9-IEEE-NEXT: v_mul_f32_e32 v1, v3, v13760; GFX9-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v13761; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v03762; GFX9-IEEE-NEXT: v_add_f32_e32 v1, v1, v23763; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v13764; GFX9-IEEE-NEXT: v_mov_b32_e32 v2, s13765; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v0, v2, s03766; GFX9-IEEE-NEXT: v_mov_b32_e32 v2, s33767; GFX9-IEEE-NEXT: v_div_fixup_f16 v1, v1, v2, s23768; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v0, v13769; GFX9-IEEE-NEXT: v_readfirstlane_b32 s0, v03770; GFX9-IEEE-NEXT: ; return to shader part epilog3771;3772; GFX9-FLUSH-LABEL: s_fdiv_v2f16:3773; GFX9-FLUSH: ; %bb.0:3774; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s13775; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s03776; GFX9-FLUSH-NEXT: s_lshr_b32 s3, s1, 163777; GFX9-FLUSH-NEXT: v_mov_b32_e32 v2, s13778; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v0, v03779; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, s33780; GFX9-FLUSH-NEXT: s_lshr_b32 s2, s0, 163781; GFX9-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v03782; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v2, v1, s0 op_sel_hi:[1,0,1]3783; GFX9-FLUSH-NEXT: v_mac_f32_e32 v1, v4, v03784; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v2, v1, s0 op_sel_hi:[1,0,1]3785; GFX9-FLUSH-NEXT: v_mul_f32_e32 v0, v4, v03786; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s23787; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v3, v33788; GFX9-FLUSH-NEXT: v_and_b32_e32 v0, 0xff800000, v03789; GFX9-FLUSH-NEXT: v_add_f32_e32 v0, v0, v13790; GFX9-FLUSH-NEXT: v_mov_b32_e32 v1, s33791; GFX9-FLUSH-NEXT: v_mul_f32_e32 v4, v4, v33792; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, -v1, v4, s2 op_sel_hi:[1,0,1]3793; GFX9-FLUSH-NEXT: v_mac_f32_e32 v4, v5, v33794; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, -v1, v4, s2 op_sel_hi:[1,0,1]3795; GFX9-FLUSH-NEXT: v_mul_f32_e32 v3, v5, v33796; GFX9-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v33797; GFX9-FLUSH-NEXT: v_add_f32_e32 v3, v3, v43798; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v03799; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v33800; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v0, v2, s03801; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v1, s23802; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v13803; GFX9-FLUSH-NEXT: v_readfirstlane_b32 s0, v03804; GFX9-FLUSH-NEXT: ; return to shader part epilog3805;3806; GFX10-IEEE-LABEL: s_fdiv_v2f16:3807; GFX10-IEEE: ; %bb.0:3808; GFX10-IEEE-NEXT: s_lshr_b32 s2, s1, 163809; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s13810; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v1, s23811; GFX10-IEEE-NEXT: s_lshr_b32 s3, s0, 163812; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, s03813; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v5, s33814; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v03815; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v13816; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v4, v23817; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v5, v33818; GFX10-IEEE-NEXT: v_mul_f32_e64 v8, -v0, v63819; GFX10-IEEE-NEXT: v_mul_f32_e64 v9, -v1, v73820; GFX10-IEEE-NEXT: v_add_f32_e32 v8, v8, v43821; GFX10-IEEE-NEXT: v_add_f32_e32 v9, v9, v53822; GFX10-IEEE-NEXT: v_mul_f32_e32 v8, v8, v23823; GFX10-IEEE-NEXT: v_mul_f32_e32 v9, v9, v33824; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v8, v63825; GFX10-IEEE-NEXT: v_add_f32_e32 v7, v9, v73826; GFX10-IEEE-NEXT: v_mul_f32_e64 v0, -v0, v63827; GFX10-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v73828; GFX10-IEEE-NEXT: v_add_f32_e32 v0, v0, v43829; GFX10-IEEE-NEXT: v_add_f32_e32 v1, v1, v53830; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v0, v23831; GFX10-IEEE-NEXT: v_mul_f32_e32 v1, v1, v33832; GFX10-IEEE-NEXT: v_and_b32_e32 v0, 0xff800000, v03833; GFX10-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v13834; GFX10-IEEE-NEXT: v_add_f32_e32 v0, v0, v63835; GFX10-IEEE-NEXT: v_add_f32_e32 v1, v1, v73836; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v03837; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v13838; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v0, s1, s03839; GFX10-IEEE-NEXT: v_div_fixup_f16 v1, v1, s2, s33840; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v0, v13841; GFX10-IEEE-NEXT: v_readfirstlane_b32 s0, v03842; GFX10-IEEE-NEXT: ; return to shader part epilog3843;3844; GFX10-FLUSH-LABEL: s_fdiv_v2f16:3845; GFX10-FLUSH: ; %bb.0:3846; GFX10-FLUSH-NEXT: s_lshr_b32 s2, s1, 163847; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s13848; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s23849; GFX10-FLUSH-NEXT: s_lshr_b32 s3, s0, 163850; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s03851; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v5, s33852; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v03853; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v13854; GFX10-FLUSH-NEXT: v_mul_f32_e32 v6, v4, v23855; GFX10-FLUSH-NEXT: v_mul_f32_e32 v7, v5, v33856; GFX10-FLUSH-NEXT: v_mad_f32 v8, -v0, v6, v43857; GFX10-FLUSH-NEXT: v_mad_f32 v9, -v1, v7, v53858; GFX10-FLUSH-NEXT: v_mac_f32_e32 v6, v8, v23859; GFX10-FLUSH-NEXT: v_mac_f32_e32 v7, v9, v33860; GFX10-FLUSH-NEXT: v_mad_f32 v0, -v0, v6, v43861; GFX10-FLUSH-NEXT: v_mad_f32 v1, -v1, v7, v53862; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v23863; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v33864; GFX10-FLUSH-NEXT: v_and_b32_e32 v0, 0xff800000, v03865; GFX10-FLUSH-NEXT: v_and_b32_e32 v1, 0xff800000, v13866; GFX10-FLUSH-NEXT: v_add_f32_e32 v0, v0, v63867; GFX10-FLUSH-NEXT: v_add_f32_e32 v1, v1, v73868; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v03869; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v13870; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v0, s1, s03871; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v1, s2, s33872; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v13873; GFX10-FLUSH-NEXT: v_readfirstlane_b32 s0, v03874; GFX10-FLUSH-NEXT: ; return to shader part epilog3875;3876; GFX11-LABEL: s_fdiv_v2f16:3877; GFX11: ; %bb.0:3878; GFX11-NEXT: s_lshr_b32 s2, s1, 163879; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s13880; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s23881; GFX11-NEXT: s_lshr_b32 s3, s0, 163882; GFX11-NEXT: v_cvt_f32_f16_e32 v2, s03883; GFX11-NEXT: v_cvt_f32_f16_e32 v3, s33884; GFX11-NEXT: v_rcp_f32_e32 v0, v03885; GFX11-NEXT: v_rcp_f32_e32 v1, v13886; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3887; GFX11-NEXT: v_dual_mul_f32 v2, v2, v0 :: v_dual_mul_f32 v3, v3, v13888; GFX11-NEXT: v_fma_mix_f32 v4, -s1, v2, s0 op_sel_hi:[1,0,1]3889; GFX11-NEXT: v_fma_mix_f32 v5, -s2, v3, s3 op_sel_hi:[1,0,1]3890; GFX11-NEXT: v_dual_fmac_f32 v2, v4, v0 :: v_dual_fmac_f32 v3, v5, v13891; GFX11-NEXT: v_fma_mix_f32 v4, -s1, v2, s0 op_sel_hi:[1,0,1]3892; GFX11-NEXT: v_fma_mix_f32 v5, -s2, v3, s3 op_sel_hi:[1,0,1]3893; GFX11-NEXT: v_dual_mul_f32 v0, v4, v0 :: v_dual_mul_f32 v1, v5, v13894; GFX11-NEXT: v_and_b32_e32 v1, 0xff800000, v13895; GFX11-NEXT: v_dual_add_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xff800000, v03896; GFX11-NEXT: v_add_f32_e32 v0, v0, v23897; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v13898; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v03899; GFX11-NEXT: v_div_fixup_f16 v1, v1, s2, s33900; GFX11-NEXT: v_div_fixup_f16 v0, v0, s1, s03901; GFX11-NEXT: v_pack_b32_f16 v0, v0, v13902; GFX11-NEXT: v_readfirstlane_b32 s0, v03903; GFX11-NEXT: ; return to shader part epilog3904 %a = bitcast i32 %a.arg to <2 x half>3905 %b = bitcast i32 %b.arg to <2 x half>3906 %fdiv = fdiv <2 x half> %a, %b3907 %result = bitcast <2 x half> %fdiv to i323908 ret i32 %result3909}3910 3911define amdgpu_ps i16 @s_rcp_f16(i16 inreg %a.arg) {3912; GFX6-IEEE-LABEL: s_rcp_f16:3913; GFX6-IEEE: ; %bb.0:3914; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s03915; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[0:1], v0, v0, 1.03916; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v13917; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.03918; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.03919; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v23920; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v23921; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v33922; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v43923; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v33924; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v43925; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.03926; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v03927; GFX6-IEEE-NEXT: v_readfirstlane_b32 s0, v03928; GFX6-IEEE-NEXT: ; return to shader part epilog3929;3930; GFX6-FLUSH-LABEL: s_rcp_f16:3931; GFX6-FLUSH: ; %bb.0:3932; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s03933; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[0:1], v0, v0, 1.03934; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v13935; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.03936; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33937; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.03938; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v23939; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v23940; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v33941; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v43942; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v33943; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 03944; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v43945; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.03946; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 03947; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v03948; GFX6-FLUSH-NEXT: v_readfirstlane_b32 s0, v03949; GFX6-FLUSH-NEXT: ; return to shader part epilog3950;3951; GFX89-LABEL: s_rcp_f16:3952; GFX89: ; %bb.0:3953; GFX89-NEXT: v_rcp_f16_e32 v0, s03954; GFX89-NEXT: v_readfirstlane_b32 s0, v03955; GFX89-NEXT: ; return to shader part epilog3956;3957; GFX10-LABEL: s_rcp_f16:3958; GFX10: ; %bb.0:3959; GFX10-NEXT: v_rcp_f16_e32 v0, s03960; GFX10-NEXT: v_readfirstlane_b32 s0, v03961; GFX10-NEXT: ; return to shader part epilog3962;3963; GFX11-LABEL: s_rcp_f16:3964; GFX11: ; %bb.0:3965; GFX11-NEXT: v_rcp_f16_e32 v0, s03966; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3967; GFX11-NEXT: v_readfirstlane_b32 s0, v03968; GFX11-NEXT: ; return to shader part epilog3969 %a = bitcast i16 %a.arg to half3970 %fdiv = fdiv half 1.0, %a3971 %result = bitcast half %fdiv to i163972 ret i16 %result3973}3974 3975define amdgpu_ps i16 @s_neg_rcp_f16(i16 inreg %a.arg) {3976; GFX6-IEEE-LABEL: s_neg_rcp_f16:3977; GFX6-IEEE: ; %bb.0:3978; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s03979; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[0:1], v0, v0, -1.03980; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v13981; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.03982; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.03983; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v23984; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v23985; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v33986; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v43987; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v33988; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v43989; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, -1.03990; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v03991; GFX6-IEEE-NEXT: v_readfirstlane_b32 s0, v03992; GFX6-IEEE-NEXT: ; return to shader part epilog3993;3994; GFX6-FLUSH-LABEL: s_neg_rcp_f16:3995; GFX6-FLUSH: ; %bb.0:3996; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s03997; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[0:1], v0, v0, -1.03998; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v13999; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.04000; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34001; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.04002; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v24003; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v24004; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v34005; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v44006; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v34007; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 04008; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v44009; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, -1.04010; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 04011; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04012; GFX6-FLUSH-NEXT: v_readfirstlane_b32 s0, v04013; GFX6-FLUSH-NEXT: ; return to shader part epilog4014;4015; GFX89-LABEL: s_neg_rcp_f16:4016; GFX89: ; %bb.0:4017; GFX89-NEXT: v_rcp_f16_e64 v0, -s04018; GFX89-NEXT: v_readfirstlane_b32 s0, v04019; GFX89-NEXT: ; return to shader part epilog4020;4021; GFX10-LABEL: s_neg_rcp_f16:4022; GFX10: ; %bb.0:4023; GFX10-NEXT: v_rcp_f16_e64 v0, -s04024; GFX10-NEXT: v_readfirstlane_b32 s0, v04025; GFX10-NEXT: ; return to shader part epilog4026;4027; GFX11-LABEL: s_neg_rcp_f16:4028; GFX11: ; %bb.0:4029; GFX11-NEXT: v_rcp_f16_e64 v0, -s04030; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4031; GFX11-NEXT: v_readfirstlane_b32 s0, v04032; GFX11-NEXT: ; return to shader part epilog4033 %a = bitcast i16 %a.arg to half4034 %fdiv = fdiv half -1.0, %a4035 %result = bitcast half %fdiv to i164036 ret i16 %result4037}4038 4039define amdgpu_ps i16 @s_rsq_f16(i16 inreg %a.arg) {4040; GFX6-IEEE-LABEL: s_rsq_f16:4041; GFX6-IEEE: ; %bb.0:4042; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s04043; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v04044; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04045; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04046; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[0:1], v0, v0, 1.04047; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v14048; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.04049; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.04050; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v24051; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v24052; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v34053; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v44054; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v34055; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v44056; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.04057; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04058; GFX6-IEEE-NEXT: v_readfirstlane_b32 s0, v04059; GFX6-IEEE-NEXT: ; return to shader part epilog4060;4061; GFX6-FLUSH-LABEL: s_rsq_f16:4062; GFX6-FLUSH: ; %bb.0:4063; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s04064; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v04065; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 04066; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04067; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04068; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[0:1], v0, v0, 1.04069; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v14070; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.04071; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34072; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.04073; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v24074; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v24075; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v34076; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v44077; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v34078; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 04079; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v44080; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.04081; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04082; GFX6-FLUSH-NEXT: v_readfirstlane_b32 s0, v04083; GFX6-FLUSH-NEXT: ; return to shader part epilog4084;4085; GFX89-LABEL: s_rsq_f16:4086; GFX89: ; %bb.0:4087; GFX89-NEXT: v_rsq_f16_e32 v0, s04088; GFX89-NEXT: v_readfirstlane_b32 s0, v04089; GFX89-NEXT: ; return to shader part epilog4090;4091; GFX10-LABEL: s_rsq_f16:4092; GFX10: ; %bb.0:4093; GFX10-NEXT: v_rsq_f16_e32 v0, s04094; GFX10-NEXT: v_readfirstlane_b32 s0, v04095; GFX10-NEXT: ; return to shader part epilog4096;4097; GFX11-LABEL: s_rsq_f16:4098; GFX11: ; %bb.0:4099; GFX11-NEXT: v_rsq_f16_e32 v0, s04100; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4101; GFX11-NEXT: v_readfirstlane_b32 s0, v04102; GFX11-NEXT: ; return to shader part epilog4103 %a = bitcast i16 %a.arg to half4104 %sqrt = call contract half @llvm.sqrt.f16(half %a)4105 %fdiv = fdiv contract half 1.0, %sqrt4106 %result = bitcast half %fdiv to i164107 ret i16 %result4108}4109 4110define amdgpu_ps i32 @s_rsq_v2f16(i32 inreg %a.arg) {4111; GFX6-IEEE-LABEL: s_rsq_v2f16:4112; GFX6-IEEE: ; %bb.0:4113; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s04114; GFX6-IEEE-NEXT: s_lshr_b32 s0, s0, 164115; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, s04116; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v04117; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v1, v14118; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04119; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v14120; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04121; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v14122; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[0:1], v0, v0, -1.04123; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v24124; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.04125; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[0:1], v1, v1, -1.04126; GFX6-IEEE-NEXT: v_fma_f32 v8, -v2, v4, 1.04127; GFX6-IEEE-NEXT: v_fma_f32 v4, v8, v4, v44128; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v54129; GFX6-IEEE-NEXT: v_mul_f32_e32 v9, v3, v44130; GFX6-IEEE-NEXT: v_fma_f32 v10, -v2, v9, v34131; GFX6-IEEE-NEXT: v_fma_f32 v9, v10, v4, v94132; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v9, v34133; GFX6-IEEE-NEXT: v_fma_f32 v8, -v5, v6, 1.04134; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v94135; GFX6-IEEE-NEXT: v_div_scale_f32 v7, s[0:1], -1.0, v1, -1.04136; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, -1.04137; GFX6-IEEE-NEXT: v_fma_f32 v2, v8, v6, v64138; GFX6-IEEE-NEXT: v_mul_f32_e32 v3, v7, v24139; GFX6-IEEE-NEXT: v_fma_f32 v4, -v5, v3, v74140; GFX6-IEEE-NEXT: v_fma_f32 v3, v4, v2, v34141; GFX6-IEEE-NEXT: v_fma_f32 v4, -v5, v3, v74142; GFX6-IEEE-NEXT: s_mov_b64 vcc, s[0:1]4143; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v4, v2, v34144; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, -1.04145; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v14146; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04147; GFX6-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v14148; GFX6-IEEE-NEXT: v_or_b32_e32 v0, v0, v14149; GFX6-IEEE-NEXT: v_readfirstlane_b32 s0, v04150; GFX6-IEEE-NEXT: ; return to shader part epilog4151;4152; GFX6-FLUSH-LABEL: s_rsq_v2f16:4153; GFX6-FLUSH: ; %bb.0:4154; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s04155; GFX6-FLUSH-NEXT: s_lshr_b32 s0, s0, 164156; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s04157; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v04158; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v1, v14159; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 04160; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04161; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v14162; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04163; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[0:1], v0, v0, -1.04164; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v24165; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, -1.0, v0, -1.04166; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34167; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.04168; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v34169; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v34170; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v44171; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v54172; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v44173; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 04174; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v14175; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v54176; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, -1.04177; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04178; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[0:1], v1, v1, -1.04179; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v24180; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, -1.0, v1, -1.04181; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34182; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.04183; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v34184; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v34185; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v44186; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v54187; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v44188; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 04189; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v54190; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, -1.04191; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v14192; GFX6-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v14193; GFX6-FLUSH-NEXT: v_or_b32_e32 v0, v0, v14194; GFX6-FLUSH-NEXT: v_readfirstlane_b32 s0, v04195; GFX6-FLUSH-NEXT: ; return to shader part epilog4196;4197; GFX8-IEEE-LABEL: s_rsq_v2f16:4198; GFX8-IEEE: ; %bb.0:4199; GFX8-IEEE-NEXT: v_sqrt_f16_e32 v0, s04200; GFX8-IEEE-NEXT: s_lshr_b32 s0, s0, 164201; GFX8-IEEE-NEXT: v_sqrt_f16_e32 v1, s04202; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v04203; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v14204; GFX8-IEEE-NEXT: v_rcp_f32_e32 v4, v24205; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v34206; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v2, v44207; GFX8-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v64208; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v3, v54209; GFX8-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v74210; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v54211; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v44212; GFX8-IEEE-NEXT: v_sub_f32_e32 v7, v7, v54213; GFX8-IEEE-NEXT: v_sub_f32_e32 v6, v6, v44214; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v74215; GFX8-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v64216; GFX8-IEEE-NEXT: v_add_f32_e32 v3, -1.0, v34217; GFX8-IEEE-NEXT: v_add_f32_e32 v2, -1.0, v24218; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v54219; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v2, v44220; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v34221; GFX8-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v24222; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v74223; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v64224; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v34225; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v24226; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v1, -1.04227; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v2, v0, -1.04228; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v14229; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v14230; GFX8-IEEE-NEXT: v_readfirstlane_b32 s0, v04231; GFX8-IEEE-NEXT: ; return to shader part epilog4232;4233; GFX8-FLUSH-LABEL: s_rsq_v2f16:4234; GFX8-FLUSH: ; %bb.0:4235; GFX8-FLUSH-NEXT: v_sqrt_f16_e32 v0, s04236; GFX8-FLUSH-NEXT: s_lshr_b32 s0, s0, 164237; GFX8-FLUSH-NEXT: v_sqrt_f16_e32 v1, s04238; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v04239; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v14240; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v4, v24241; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v34242; GFX8-FLUSH-NEXT: v_mad_f32 v6, v2, v4, -1.04243; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, -v44244; GFX8-FLUSH-NEXT: v_mad_f32 v7, v3, v5, -1.04245; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, -v54246; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, -1.04247; GFX8-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, -1.04248; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v54249; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v44250; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v34251; GFX8-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v24252; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v74253; GFX8-FLUSH-NEXT: v_add_f32_e32 v2, v2, v64254; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v34255; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v24256; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v1, -1.04257; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v0, -1.04258; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v14259; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v14260; GFX8-FLUSH-NEXT: v_readfirstlane_b32 s0, v04261; GFX8-FLUSH-NEXT: ; return to shader part epilog4262;4263; GFX9-IEEE-LABEL: s_rsq_v2f16:4264; GFX9-IEEE: ; %bb.0:4265; GFX9-IEEE-NEXT: v_sqrt_f16_e32 v0, s04266; GFX9-IEEE-NEXT: s_lshr_b32 s0, s0, 164267; GFX9-IEEE-NEXT: v_sqrt_f16_e32 v1, s04268; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v04269; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v14270; GFX9-IEEE-NEXT: v_rcp_f32_e32 v4, v24271; GFX9-IEEE-NEXT: v_rcp_f32_e32 v5, v34272; GFX9-IEEE-NEXT: v_fma_f32 v6, v2, v4, -1.04273; GFX9-IEEE-NEXT: v_fma_f32 v6, v6, v4, -v44274; GFX9-IEEE-NEXT: v_fma_f32 v7, v3, v5, -1.04275; GFX9-IEEE-NEXT: v_fma_f32 v7, v7, v5, -v54276; GFX9-IEEE-NEXT: v_fma_f32 v2, -v2, v6, -1.04277; GFX9-IEEE-NEXT: v_fma_f32 v3, -v3, v7, -1.04278; GFX9-IEEE-NEXT: v_mul_f32_e32 v2, v2, v44279; GFX9-IEEE-NEXT: v_mul_f32_e32 v3, v3, v54280; GFX9-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v24281; GFX9-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v34282; GFX9-IEEE-NEXT: v_add_f32_e32 v2, v2, v64283; GFX9-IEEE-NEXT: v_add_f32_e32 v3, v3, v74284; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v24285; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v34286; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v2, v0, -1.04287; GFX9-IEEE-NEXT: v_div_fixup_f16 v1, v3, v1, -1.04288; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v0, v14289; GFX9-IEEE-NEXT: v_readfirstlane_b32 s0, v04290; GFX9-IEEE-NEXT: ; return to shader part epilog4291;4292; GFX9-FLUSH-LABEL: s_rsq_v2f16:4293; GFX9-FLUSH: ; %bb.0:4294; GFX9-FLUSH-NEXT: v_sqrt_f16_e32 v0, s04295; GFX9-FLUSH-NEXT: s_lshr_b32 s0, s0, 164296; GFX9-FLUSH-NEXT: v_sqrt_f16_e32 v1, s04297; GFX9-FLUSH-NEXT: v_mov_b32_e32 v4, -1.04298; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v04299; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v14300; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v24301; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v3, v34302; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, v0, v2, v4 op_sel_hi:[1,0,0]4303; GFX9-FLUSH-NEXT: v_mad_f32 v5, v5, v2, -v24304; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, v1, v3, v4 op_sel_hi:[1,0,0]4305; GFX9-FLUSH-NEXT: v_mad_f32 v6, v6, v3, -v34306; GFX9-FLUSH-NEXT: v_mad_mix_f32 v7, -v0, v5, v4 op_sel_hi:[1,0,0]4307; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v1, v6, v4 op_sel_hi:[1,0,0]4308; GFX9-FLUSH-NEXT: v_mul_f32_e32 v2, v7, v24309; GFX9-FLUSH-NEXT: v_mul_f32_e32 v3, v4, v34310; GFX9-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v24311; GFX9-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v34312; GFX9-FLUSH-NEXT: v_add_f32_e32 v2, v2, v54313; GFX9-FLUSH-NEXT: v_add_f32_e32 v3, v3, v64314; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v24315; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v34316; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v0, -1.04317; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v1, -1.04318; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v14319; GFX9-FLUSH-NEXT: v_readfirstlane_b32 s0, v04320; GFX9-FLUSH-NEXT: ; return to shader part epilog4321;4322; GFX10-IEEE-LABEL: s_rsq_v2f16:4323; GFX10-IEEE: ; %bb.0:4324; GFX10-IEEE-NEXT: s_lshr_b32 s1, s0, 164325; GFX10-IEEE-NEXT: v_sqrt_f16_e32 v0, s04326; GFX10-IEEE-NEXT: v_sqrt_f16_e32 v1, s14327; GFX10-IEEE-NEXT: v_mov_b32_e32 v4, -1.04328; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v04329; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v14330; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v24331; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v34332; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, v0, v2, v4 op_sel_hi:[1,0,0]4333; GFX10-IEEE-NEXT: v_fma_mix_f32 v6, v1, v3, v4 op_sel_hi:[1,0,0]4334; GFX10-IEEE-NEXT: v_fma_f32 v5, v5, v2, -v24335; GFX10-IEEE-NEXT: v_fma_f32 v6, v6, v3, -v34336; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v0, v5, v4 op_sel_hi:[1,0,0]4337; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, -v1, v6, v4 op_sel_hi:[1,0,0]4338; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v7, v24339; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v4, v34340; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v24341; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v34342; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v54343; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v64344; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v24345; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v34346; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v0, -1.04347; GFX10-IEEE-NEXT: v_div_fixup_f16 v1, v3, v1, -1.04348; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v0, v14349; GFX10-IEEE-NEXT: v_readfirstlane_b32 s0, v04350; GFX10-IEEE-NEXT: ; return to shader part epilog4351;4352; GFX10-FLUSH-LABEL: s_rsq_v2f16:4353; GFX10-FLUSH: ; %bb.0:4354; GFX10-FLUSH-NEXT: s_lshr_b32 s1, s0, 164355; GFX10-FLUSH-NEXT: v_sqrt_f16_e32 v0, s04356; GFX10-FLUSH-NEXT: v_sqrt_f16_e32 v1, s14357; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v04358; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v14359; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v4, v24360; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v34361; GFX10-FLUSH-NEXT: v_mad_f32 v6, v2, v4, -1.04362; GFX10-FLUSH-NEXT: v_mad_f32 v7, v3, v5, -1.04363; GFX10-FLUSH-NEXT: v_mad_f32 v6, v6, v4, -v44364; GFX10-FLUSH-NEXT: v_mad_f32 v7, v7, v5, -v54365; GFX10-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, -1.04366; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, -1.04367; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v44368; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v54369; GFX10-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v24370; GFX10-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v34371; GFX10-FLUSH-NEXT: v_add_f32_e32 v2, v2, v64372; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v74373; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v24374; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v34375; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v0, -1.04376; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v1, -1.04377; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v14378; GFX10-FLUSH-NEXT: v_readfirstlane_b32 s0, v04379; GFX10-FLUSH-NEXT: ; return to shader part epilog4380;4381; GFX11-LABEL: s_rsq_v2f16:4382; GFX11: ; %bb.0:4383; GFX11-NEXT: s_lshr_b32 s1, s0, 164384; GFX11-NEXT: v_sqrt_f16_e32 v0, s04385; GFX11-NEXT: v_sqrt_f16_e32 v1, s14386; GFX11-NEXT: v_mov_b32_e32 v4, -1.04387; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4388; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v04389; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v14390; GFX11-NEXT: v_rcp_f32_e32 v2, v24391; GFX11-NEXT: v_rcp_f32_e32 v3, v34392; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4393; GFX11-NEXT: v_fma_mix_f32 v5, v0, v2, v4 op_sel_hi:[1,0,0]4394; GFX11-NEXT: v_fma_mix_f32 v6, v1, v3, v4 op_sel_hi:[1,0,0]4395; GFX11-NEXT: v_fma_f32 v5, v5, v2, -v24396; GFX11-NEXT: v_fma_f32 v6, v6, v3, -v34397; GFX11-NEXT: v_fma_mix_f32 v7, -v0, v5, v4 op_sel_hi:[1,0,0]4398; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v6, v4 op_sel_hi:[1,0,0]4399; GFX11-NEXT: v_dual_mul_f32 v2, v7, v2 :: v_dual_mul_f32 v3, v4, v34400; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v24401; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_and_b32 v3, 0xff800000, v34402; GFX11-NEXT: v_add_f32_e32 v3, v3, v64403; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v24404; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v34405; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, -1.04406; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, -1.04407; GFX11-NEXT: v_pack_b32_f16 v0, v0, v14408; GFX11-NEXT: v_readfirstlane_b32 s0, v04409; GFX11-NEXT: ; return to shader part epilog4410 %a = bitcast i32 %a.arg to <2 x half>4411 %sqrt = call contract <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)4412 %fdiv = fdiv contract <2 x half> <half -1.0, half -1.0>, %sqrt4413 %result = bitcast <2 x half> %fdiv to i324414 ret i32 %result4415}4416 4417define half @v_rsq_f16(half %a) {4418; GFX6-IEEE-LABEL: v_rsq_f16:4419; GFX6-IEEE: ; %bb.0:4420; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4421; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04422; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v04423; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04424; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04425; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.04426; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v14427; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.04428; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.04429; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v24430; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v24431; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v34432; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v44433; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v34434; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v44435; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.04436; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04437; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]4438;4439; GFX6-FLUSH-LABEL: v_rsq_f16:4440; GFX6-FLUSH: ; %bb.0:4441; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4442; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04443; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v04444; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 04445; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04446; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04447; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.04448; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v14449; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.04450; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34451; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.04452; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v24453; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v24454; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v34455; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v44456; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v34457; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 04458; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v44459; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.04460; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04461; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]4462;4463; GFX89-LABEL: v_rsq_f16:4464; GFX89: ; %bb.0:4465; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4466; GFX89-NEXT: v_rsq_f16_e32 v0, v04467; GFX89-NEXT: s_setpc_b64 s[30:31]4468;4469; GFX10PLUS-LABEL: v_rsq_f16:4470; GFX10PLUS: ; %bb.0:4471; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4472; GFX10PLUS-NEXT: v_rsq_f16_e32 v0, v04473; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]4474 %sqrt = call contract half @llvm.sqrt.f16(half %a)4475 %fdiv = fdiv contract half 1.0, %sqrt4476 ret half %fdiv4477}4478 4479define half @v_neg_rsq_f16(half %a) {4480; GFX6-IEEE-LABEL: v_neg_rsq_f16:4481; GFX6-IEEE: ; %bb.0:4482; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4483; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04484; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v04485; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04486; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04487; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.04488; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v14489; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.04490; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.04491; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v24492; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v24493; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v34494; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v44495; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v34496; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v44497; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, -1.04498; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04499; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]4500;4501; GFX6-FLUSH-LABEL: v_neg_rsq_f16:4502; GFX6-FLUSH: ; %bb.0:4503; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4504; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04505; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v04506; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 04507; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04508; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04509; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.04510; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v14511; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.04512; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34513; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.04514; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v24515; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v24516; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v34517; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v44518; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v34519; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 04520; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v44521; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, -1.04522; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04523; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]4524;4525; GFX89-LABEL: v_neg_rsq_f16:4526; GFX89: ; %bb.0:4527; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4528; GFX89-NEXT: v_sqrt_f16_e32 v0, v04529; GFX89-NEXT: v_rcp_f16_e64 v0, -v04530; GFX89-NEXT: s_setpc_b64 s[30:31]4531;4532; GFX10-LABEL: v_neg_rsq_f16:4533; GFX10: ; %bb.0:4534; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4535; GFX10-NEXT: v_sqrt_f16_e32 v0, v04536; GFX10-NEXT: v_rcp_f16_e64 v0, -v04537; GFX10-NEXT: s_setpc_b64 s[30:31]4538;4539; GFX11-LABEL: v_neg_rsq_f16:4540; GFX11: ; %bb.0:4541; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4542; GFX11-NEXT: v_sqrt_f16_e32 v0, v04543; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4544; GFX11-NEXT: v_rcp_f16_e64 v0, -v04545; GFX11-NEXT: s_setpc_b64 s[30:31]4546 %sqrt = call contract half @llvm.sqrt.f16(half %a)4547 %fdiv = fdiv contract half -1.0, %sqrt4548 ret half %fdiv4549}4550 4551define { half, half } @v_rsq_f16_multi_use(half %a) {4552; GFX6-IEEE-LABEL: v_rsq_f16_multi_use:4553; GFX6-IEEE: ; %bb.0:4554; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4555; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04556; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v04557; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04558; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v04559; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.04560; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v24561; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.04562; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.04563; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v34564; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v34565; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v44566; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v54567; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v44568; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v54569; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, 1.04570; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v14571; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]4572;4573; GFX6-FLUSH-LABEL: v_rsq_f16_multi_use:4574; GFX6-FLUSH: ; %bb.0:4575; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4576; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04577; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v04578; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 04579; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04580; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v04581; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.04582; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v24583; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.04584; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34585; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.04586; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v34587; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v34588; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v44589; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v54590; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v44591; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 04592; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v54593; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.04594; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v14595; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]4596;4597; GFX89-LABEL: v_rsq_f16_multi_use:4598; GFX89: ; %bb.0:4599; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4600; GFX89-NEXT: v_sqrt_f16_e32 v2, v04601; GFX89-NEXT: v_rsq_f16_e32 v1, v04602; GFX89-NEXT: v_mov_b32_e32 v0, v24603; GFX89-NEXT: s_setpc_b64 s[30:31]4604;4605; GFX10-LABEL: v_rsq_f16_multi_use:4606; GFX10: ; %bb.0:4607; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4608; GFX10-NEXT: v_sqrt_f16_e32 v2, v04609; GFX10-NEXT: v_rsq_f16_e32 v1, v04610; GFX10-NEXT: v_mov_b32_e32 v0, v24611; GFX10-NEXT: s_setpc_b64 s[30:31]4612;4613; GFX11-LABEL: v_rsq_f16_multi_use:4614; GFX11: ; %bb.0:4615; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4616; GFX11-NEXT: v_sqrt_f16_e32 v2, v04617; GFX11-NEXT: v_rsq_f16_e32 v1, v04618; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4619; GFX11-NEXT: v_mov_b32_e32 v0, v24620; GFX11-NEXT: s_setpc_b64 s[30:31]4621 %sqrt = call contract half @llvm.sqrt.f16(half %a)4622 %insert.0 = insertvalue { half, half } poison, half %sqrt, 04623 %fdiv = fdiv contract half 1.0, %sqrt4624 %insert.1 = insertvalue { half, half } %insert.0, half %fdiv, 14625 ret { half, half } %insert.14626}4627 4628define half @v_rsq_f16_missing_contract0(half %a) {4629; GFX6-IEEE-LABEL: v_rsq_f16_missing_contract0:4630; GFX6-IEEE: ; %bb.0:4631; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4632; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04633; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v04634; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04635; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04636; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.04637; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v14638; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.04639; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.04640; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v24641; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v24642; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v34643; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v44644; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v34645; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v44646; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.04647; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04648; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]4649;4650; GFX6-FLUSH-LABEL: v_rsq_f16_missing_contract0:4651; GFX6-FLUSH: ; %bb.0:4652; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4653; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04654; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v04655; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 04656; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04657; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04658; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.04659; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v14660; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.04661; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34662; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.04663; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v24664; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v24665; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v34666; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v44667; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v34668; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 04669; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v44670; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.04671; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04672; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]4673;4674; GFX89-LABEL: v_rsq_f16_missing_contract0:4675; GFX89: ; %bb.0:4676; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4677; GFX89-NEXT: v_sqrt_f16_e32 v0, v04678; GFX89-NEXT: v_rcp_f16_e32 v0, v04679; GFX89-NEXT: s_setpc_b64 s[30:31]4680;4681; GFX10-LABEL: v_rsq_f16_missing_contract0:4682; GFX10: ; %bb.0:4683; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4684; GFX10-NEXT: v_sqrt_f16_e32 v0, v04685; GFX10-NEXT: v_rcp_f16_e32 v0, v04686; GFX10-NEXT: s_setpc_b64 s[30:31]4687;4688; GFX11-LABEL: v_rsq_f16_missing_contract0:4689; GFX11: ; %bb.0:4690; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4691; GFX11-NEXT: v_sqrt_f16_e32 v0, v04692; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4693; GFX11-NEXT: v_rcp_f16_e32 v0, v04694; GFX11-NEXT: s_setpc_b64 s[30:31]4695 %sqrt = call half @llvm.sqrt.f16(half %a)4696 %fdiv = fdiv contract half 1.0, %sqrt4697 ret half %fdiv4698}4699 4700define half @v_rsq_f16_missing_contract1(half %a) {4701; GFX6-IEEE-LABEL: v_rsq_f16_missing_contract1:4702; GFX6-IEEE: ; %bb.0:4703; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4704; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04705; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v04706; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04707; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04708; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.04709; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v14710; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.04711; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.04712; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v24713; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v24714; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v34715; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v44716; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v34717; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v44718; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.04719; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04720; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]4721;4722; GFX6-FLUSH-LABEL: v_rsq_f16_missing_contract1:4723; GFX6-FLUSH: ; %bb.0:4724; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4725; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04726; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v04727; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 04728; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04729; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04730; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.04731; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v14732; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.04733; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34734; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.04735; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v24736; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v24737; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v34738; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v44739; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v34740; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 04741; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v44742; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.04743; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04744; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]4745;4746; GFX89-LABEL: v_rsq_f16_missing_contract1:4747; GFX89: ; %bb.0:4748; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4749; GFX89-NEXT: v_sqrt_f16_e32 v0, v04750; GFX89-NEXT: v_rcp_f16_e32 v0, v04751; GFX89-NEXT: s_setpc_b64 s[30:31]4752;4753; GFX10-LABEL: v_rsq_f16_missing_contract1:4754; GFX10: ; %bb.0:4755; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4756; GFX10-NEXT: v_sqrt_f16_e32 v0, v04757; GFX10-NEXT: v_rcp_f16_e32 v0, v04758; GFX10-NEXT: s_setpc_b64 s[30:31]4759;4760; GFX11-LABEL: v_rsq_f16_missing_contract1:4761; GFX11: ; %bb.0:4762; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4763; GFX11-NEXT: v_sqrt_f16_e32 v0, v04764; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4765; GFX11-NEXT: v_rcp_f16_e32 v0, v04766; GFX11-NEXT: s_setpc_b64 s[30:31]4767 %sqrt = call contract half @llvm.sqrt.f16(half %a)4768 %fdiv = fdiv half 1.0, %sqrt4769 ret half %fdiv4770}4771 4772define half @v_neg_rsq_f16_missing_contract0(half %a) {4773; GFX6-IEEE-LABEL: v_neg_rsq_f16_missing_contract0:4774; GFX6-IEEE: ; %bb.0:4775; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4776; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04777; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v04778; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04779; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04780; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.04781; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v14782; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.04783; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.04784; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v24785; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v24786; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v34787; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v44788; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v34789; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v44790; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, -1.04791; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04792; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]4793;4794; GFX6-FLUSH-LABEL: v_neg_rsq_f16_missing_contract0:4795; GFX6-FLUSH: ; %bb.0:4796; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4797; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04798; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v04799; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 04800; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04801; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04802; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.04803; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v14804; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.04805; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34806; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.04807; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v24808; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v24809; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v34810; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v44811; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v34812; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 04813; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v44814; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, -1.04815; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04816; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]4817;4818; GFX89-LABEL: v_neg_rsq_f16_missing_contract0:4819; GFX89: ; %bb.0:4820; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4821; GFX89-NEXT: v_sqrt_f16_e32 v0, v04822; GFX89-NEXT: v_rcp_f16_e64 v0, -v04823; GFX89-NEXT: s_setpc_b64 s[30:31]4824;4825; GFX10-LABEL: v_neg_rsq_f16_missing_contract0:4826; GFX10: ; %bb.0:4827; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4828; GFX10-NEXT: v_sqrt_f16_e32 v0, v04829; GFX10-NEXT: v_rcp_f16_e64 v0, -v04830; GFX10-NEXT: s_setpc_b64 s[30:31]4831;4832; GFX11-LABEL: v_neg_rsq_f16_missing_contract0:4833; GFX11: ; %bb.0:4834; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4835; GFX11-NEXT: v_sqrt_f16_e32 v0, v04836; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4837; GFX11-NEXT: v_rcp_f16_e64 v0, -v04838; GFX11-NEXT: s_setpc_b64 s[30:31]4839 %sqrt = call half @llvm.sqrt.f16(half %a)4840 %fdiv = fdiv contract half -1.0, %sqrt4841 ret half %fdiv4842}4843 4844define half @v_neg_rsq_f16_missing_contract1(half %a) {4845; GFX6-IEEE-LABEL: v_neg_rsq_f16_missing_contract1:4846; GFX6-IEEE: ; %bb.0:4847; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4848; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04849; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v04850; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04851; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04852; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.04853; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v14854; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.04855; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.04856; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v24857; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v24858; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v34859; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v44860; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v34861; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v44862; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, -1.04863; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04864; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]4865;4866; GFX6-FLUSH-LABEL: v_neg_rsq_f16_missing_contract1:4867; GFX6-FLUSH: ; %bb.0:4868; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4869; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04870; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v04871; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 04872; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04873; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04874; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.04875; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v14876; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.04877; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34878; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.04879; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v24880; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v24881; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v34882; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v44883; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v34884; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 04885; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v44886; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, -1.04887; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04888; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]4889;4890; GFX89-LABEL: v_neg_rsq_f16_missing_contract1:4891; GFX89: ; %bb.0:4892; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4893; GFX89-NEXT: v_sqrt_f16_e32 v0, v04894; GFX89-NEXT: v_rcp_f16_e64 v0, -v04895; GFX89-NEXT: s_setpc_b64 s[30:31]4896;4897; GFX10-LABEL: v_neg_rsq_f16_missing_contract1:4898; GFX10: ; %bb.0:4899; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4900; GFX10-NEXT: v_sqrt_f16_e32 v0, v04901; GFX10-NEXT: v_rcp_f16_e64 v0, -v04902; GFX10-NEXT: s_setpc_b64 s[30:31]4903;4904; GFX11-LABEL: v_neg_rsq_f16_missing_contract1:4905; GFX11: ; %bb.0:4906; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4907; GFX11-NEXT: v_sqrt_f16_e32 v0, v04908; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4909; GFX11-NEXT: v_rcp_f16_e64 v0, -v04910; GFX11-NEXT: s_setpc_b64 s[30:31]4911 %sqrt = call contract half @llvm.sqrt.f16(half %a)4912 %fdiv = fdiv half -1.0, %sqrt4913 ret half %fdiv4914}4915 4916define half @v_neg_rsq_f16_fabs(half %a) {4917; GFX6-IEEE-LABEL: v_neg_rsq_f16_fabs:4918; GFX6-IEEE: ; %bb.0:4919; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4920; GFX6-IEEE-NEXT: v_cvt_f32_f16_e64 v0, |v0|4921; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v04922; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04923; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04924; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.04925; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v14926; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.04927; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.04928; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v24929; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v24930; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v34931; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v44932; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v34933; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v44934; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, -1.04935; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04936; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]4937;4938; GFX6-FLUSH-LABEL: v_neg_rsq_f16_fabs:4939; GFX6-FLUSH: ; %bb.0:4940; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4941; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e64 v0, |v0|4942; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v04943; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 04944; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04945; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v04946; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.04947; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v14948; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.04949; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34950; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.04951; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v24952; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v24953; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v34954; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v44955; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v34956; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 04957; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v44958; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, -1.04959; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v04960; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]4961;4962; GFX89-LABEL: v_neg_rsq_f16_fabs:4963; GFX89: ; %bb.0:4964; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4965; GFX89-NEXT: v_sqrt_f16_e64 v0, |v0|4966; GFX89-NEXT: v_rcp_f16_e64 v0, -v04967; GFX89-NEXT: s_setpc_b64 s[30:31]4968;4969; GFX10-LABEL: v_neg_rsq_f16_fabs:4970; GFX10: ; %bb.0:4971; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4972; GFX10-NEXT: v_sqrt_f16_e64 v0, |v0|4973; GFX10-NEXT: v_rcp_f16_e64 v0, -v04974; GFX10-NEXT: s_setpc_b64 s[30:31]4975;4976; GFX11-LABEL: v_neg_rsq_f16_fabs:4977; GFX11: ; %bb.0:4978; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4979; GFX11-NEXT: v_sqrt_f16_e64 v0, |v0|4980; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4981; GFX11-NEXT: v_rcp_f16_e64 v0, -v04982; GFX11-NEXT: s_setpc_b64 s[30:31]4983 %a.fabs = call half @llvm.fabs.f16(half %a)4984 %sqrt = call contract half @llvm.sqrt.f16(half %a.fabs)4985 %fdiv = fdiv contract half -1.0, %sqrt4986 ret half %fdiv4987}4988 4989define half @v_rsq_f16_arcp(half %a) {4990; GFX6-IEEE-LABEL: v_rsq_f16_arcp:4991; GFX6-IEEE: ; %bb.0:4992; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4993; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04994; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v04995; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v04996; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v04997; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.04998; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v14999; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.05000; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.05001; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v25002; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v25003; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v35004; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v45005; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v35006; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v45007; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.05008; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v05009; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]5010;5011; GFX6-FLUSH-LABEL: v_rsq_f16_arcp:5012; GFX6-FLUSH: ; %bb.0:5013; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5014; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v05015; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v05016; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 05017; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v05018; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v05019; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.05020; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v15021; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.05022; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 35023; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.05024; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v25025; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v25026; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v35027; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v45028; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v35029; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 05030; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v45031; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.05032; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v05033; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]5034;5035; GFX89-LABEL: v_rsq_f16_arcp:5036; GFX89: ; %bb.0:5037; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5038; GFX89-NEXT: v_rsq_f16_e32 v0, v05039; GFX89-NEXT: s_setpc_b64 s[30:31]5040;5041; GFX10PLUS-LABEL: v_rsq_f16_arcp:5042; GFX10PLUS: ; %bb.0:5043; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5044; GFX10PLUS-NEXT: v_rsq_f16_e32 v0, v05045; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]5046 %sqrt = call contract half @llvm.sqrt.f16(half %a)5047 %fdiv = fdiv contract arcp half 1.0, %sqrt5048 ret half %fdiv5049}5050 5051define half @v_neg_rsq_f16_arcp(half %a) {5052; GFX6-IEEE-LABEL: v_neg_rsq_f16_arcp:5053; GFX6-IEEE: ; %bb.0:5054; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5055; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v05056; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v05057; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v05058; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v05059; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.05060; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v15061; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.05062; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.05063; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v25064; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v25065; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v35066; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v45067; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v35068; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v45069; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, -1.05070; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v05071; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]5072;5073; GFX6-FLUSH-LABEL: v_neg_rsq_f16_arcp:5074; GFX6-FLUSH: ; %bb.0:5075; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5076; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v05077; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v05078; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 05079; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v05080; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v05081; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.05082; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v15083; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.05084; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 35085; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.05086; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v25087; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v25088; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v35089; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v45090; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v35091; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 05092; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v45093; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, -1.05094; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v05095; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]5096;5097; GFX89-LABEL: v_neg_rsq_f16_arcp:5098; GFX89: ; %bb.0:5099; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5100; GFX89-NEXT: v_sqrt_f16_e32 v0, v05101; GFX89-NEXT: v_rcp_f16_e64 v0, -v05102; GFX89-NEXT: s_setpc_b64 s[30:31]5103;5104; GFX10-LABEL: v_neg_rsq_f16_arcp:5105; GFX10: ; %bb.0:5106; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5107; GFX10-NEXT: v_sqrt_f16_e32 v0, v05108; GFX10-NEXT: v_rcp_f16_e64 v0, -v05109; GFX10-NEXT: s_setpc_b64 s[30:31]5110;5111; GFX11-LABEL: v_neg_rsq_f16_arcp:5112; GFX11: ; %bb.0:5113; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5114; GFX11-NEXT: v_sqrt_f16_e32 v0, v05115; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)5116; GFX11-NEXT: v_rcp_f16_e64 v0, -v05117; GFX11-NEXT: s_setpc_b64 s[30:31]5118 %sqrt = call contract half @llvm.sqrt.f16(half %a)5119 %fdiv = fdiv contract arcp half -1.0, %sqrt5120 ret half %fdiv5121}5122 5123define half @v_rsq_f16_afn(half %a) {5124; GFX6-LABEL: v_rsq_f16_afn:5125; GFX6: ; %bb.0:5126; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5127; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v05128; GFX6-NEXT: v_sqrt_f32_e32 v0, v05129; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v05130; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v05131; GFX6-NEXT: v_rcp_f32_e32 v0, v05132; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v05133; GFX6-NEXT: s_setpc_b64 s[30:31]5134;5135; GFX89-LABEL: v_rsq_f16_afn:5136; GFX89: ; %bb.0:5137; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5138; GFX89-NEXT: v_rsq_f16_e32 v0, v05139; GFX89-NEXT: s_setpc_b64 s[30:31]5140;5141; GFX10PLUS-LABEL: v_rsq_f16_afn:5142; GFX10PLUS: ; %bb.0:5143; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5144; GFX10PLUS-NEXT: v_rsq_f16_e32 v0, v05145; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]5146 %sqrt = call contract half @llvm.sqrt.f16(half %a)5147 %fdiv = fdiv afn contract half 1.0, %sqrt5148 ret half %fdiv5149}5150 5151define half @v_rsq_f16_afn_nocontract(half %a) {5152; GFX6-LABEL: v_rsq_f16_afn_nocontract:5153; GFX6: ; %bb.0:5154; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5155; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v05156; GFX6-NEXT: v_sqrt_f32_e32 v0, v05157; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v05158; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v05159; GFX6-NEXT: v_rcp_f32_e32 v0, v05160; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v05161; GFX6-NEXT: s_setpc_b64 s[30:31]5162;5163; GFX89-LABEL: v_rsq_f16_afn_nocontract:5164; GFX89: ; %bb.0:5165; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5166; GFX89-NEXT: v_sqrt_f16_e32 v0, v05167; GFX89-NEXT: v_rcp_f16_e32 v0, v05168; GFX89-NEXT: s_setpc_b64 s[30:31]5169;5170; GFX10-LABEL: v_rsq_f16_afn_nocontract:5171; GFX10: ; %bb.0:5172; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5173; GFX10-NEXT: v_sqrt_f16_e32 v0, v05174; GFX10-NEXT: v_rcp_f16_e32 v0, v05175; GFX10-NEXT: s_setpc_b64 s[30:31]5176;5177; GFX11-LABEL: v_rsq_f16_afn_nocontract:5178; GFX11: ; %bb.0:5179; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5180; GFX11-NEXT: v_sqrt_f16_e32 v0, v05181; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)5182; GFX11-NEXT: v_rcp_f16_e32 v0, v05183; GFX11-NEXT: s_setpc_b64 s[30:31]5184 %sqrt = call half @llvm.sqrt.f16(half %a)5185 %fdiv = fdiv afn half 1.0, %sqrt5186 ret half %fdiv5187}5188 5189define <2 x half> @v_rsq_v2f16(<2 x half> %a) {5190; GFX6-IEEE-LABEL: v_rsq_v2f16:5191; GFX6-IEEE: ; %bb.0:5192; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5193; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v05194; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v15195; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v05196; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v1, v15197; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v05198; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v15199; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v05200; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v15201; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.05202; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v25203; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.05204; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v1, v1, 1.05205; GFX6-IEEE-NEXT: v_fma_f32 v8, -v2, v5, 1.05206; GFX6-IEEE-NEXT: v_fma_f32 v5, v8, v5, v55207; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v45208; GFX6-IEEE-NEXT: v_mul_f32_e32 v8, v3, v55209; GFX6-IEEE-NEXT: v_fma_f32 v10, -v2, v8, v35210; GFX6-IEEE-NEXT: v_fma_f32 v8, v10, v5, v85211; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v8, v35212; GFX6-IEEE-NEXT: v_fma_f32 v9, -v4, v6, 1.05213; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v5, v85214; GFX6-IEEE-NEXT: v_div_scale_f32 v7, s[4:5], 1.0, v1, 1.05215; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.05216; GFX6-IEEE-NEXT: v_fma_f32 v2, v9, v6, v65217; GFX6-IEEE-NEXT: v_mul_f32_e32 v3, v7, v25218; GFX6-IEEE-NEXT: v_fma_f32 v5, -v4, v3, v75219; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v2, v35220; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v3, v75221; GFX6-IEEE-NEXT: s_mov_b64 vcc, s[4:5]5222; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v4, v2, v35223; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, 1.05224; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v05225; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v15226; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]5227;5228; GFX6-FLUSH-LABEL: v_rsq_v2f16:5229; GFX6-FLUSH: ; %bb.0:5230; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5231; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v05232; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v15233; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v05234; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v1, v15235; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 05236; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v05237; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v15238; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v05239; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.05240; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v25241; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.05242; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 35243; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.05244; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v35245; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v35246; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v45247; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v55248; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v45249; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 05250; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v15251; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v55252; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.05253; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v05254; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.05255; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v25256; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.05257; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 35258; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.05259; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v35260; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v35261; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v45262; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v55263; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v45264; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 05265; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v55266; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.05267; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v15268; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]5269;5270; GFX8-IEEE-LABEL: v_rsq_v2f16:5271; GFX8-IEEE: ; %bb.0:5272; GFX8-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5273; GFX8-IEEE-NEXT: v_sqrt_f16_e32 v1, v05274; GFX8-IEEE-NEXT: v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15275; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v15276; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v05277; GFX8-IEEE-NEXT: v_rcp_f32_e32 v4, v25278; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v35279; GFX8-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v45280; GFX8-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v55281; GFX8-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v75282; GFX8-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v65283; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v55284; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v45285; GFX8-IEEE-NEXT: v_add_f32_e32 v7, v7, v55286; GFX8-IEEE-NEXT: v_add_f32_e32 v6, v6, v45287; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v75288; GFX8-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v65289; GFX8-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v35290; GFX8-IEEE-NEXT: v_add_f32_e32 v2, 1.0, v25291; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v55292; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v2, v45293; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v35294; GFX8-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v25295; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v75296; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v65297; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v35298; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v25299; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v3, v0, 1.05300; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v2, v1, 1.05301; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v05302; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v1, v05303; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]5304;5305; GFX8-FLUSH-LABEL: v_rsq_v2f16:5306; GFX8-FLUSH: ; %bb.0:5307; GFX8-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5308; GFX8-FLUSH-NEXT: v_sqrt_f16_e32 v1, v05309; GFX8-FLUSH-NEXT: v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15310; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v15311; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v05312; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v4, v25313; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v35314; GFX8-FLUSH-NEXT: v_mad_f32 v6, -v2, v4, 1.05315; GFX8-FLUSH-NEXT: v_mad_f32 v7, -v3, v5, 1.05316; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, v55317; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, v45318; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, 1.05319; GFX8-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, 1.05320; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v55321; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v45322; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v35323; GFX8-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v25324; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v75325; GFX8-FLUSH-NEXT: v_add_f32_e32 v2, v2, v65326; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v35327; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v25328; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v0, 1.05329; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, 1.05330; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v05331; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v1, v05332; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]5333;5334; GFX9-IEEE-LABEL: v_rsq_v2f16:5335; GFX9-IEEE: ; %bb.0:5336; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5337; GFX9-IEEE-NEXT: v_sqrt_f16_e32 v1, v05338; GFX9-IEEE-NEXT: v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15339; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v15340; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v05341; GFX9-IEEE-NEXT: v_rcp_f32_e32 v4, v25342; GFX9-IEEE-NEXT: v_rcp_f32_e32 v5, v35343; GFX9-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.05344; GFX9-IEEE-NEXT: v_fma_f32 v7, -v3, v5, 1.05345; GFX9-IEEE-NEXT: v_fma_f32 v6, v6, v4, v45346; GFX9-IEEE-NEXT: v_fma_f32 v7, v7, v5, v55347; GFX9-IEEE-NEXT: v_fma_f32 v2, -v2, v6, 1.05348; GFX9-IEEE-NEXT: v_fma_f32 v3, -v3, v7, 1.05349; GFX9-IEEE-NEXT: v_mul_f32_e32 v2, v2, v45350; GFX9-IEEE-NEXT: v_mul_f32_e32 v3, v3, v55351; GFX9-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v25352; GFX9-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v35353; GFX9-IEEE-NEXT: v_add_f32_e32 v2, v2, v65354; GFX9-IEEE-NEXT: v_add_f32_e32 v3, v3, v75355; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v25356; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v35357; GFX9-IEEE-NEXT: v_div_fixup_f16 v1, v2, v1, 1.05358; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v3, v0, 1.05359; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v1, v05360; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31]5361;5362; GFX9-FLUSH-LABEL: v_rsq_v2f16:5363; GFX9-FLUSH: ; %bb.0:5364; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5365; GFX9-FLUSH-NEXT: v_sqrt_f16_e32 v1, v05366; GFX9-FLUSH-NEXT: v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15367; GFX9-FLUSH-NEXT: v_mov_b32_e32 v4, 1.05368; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v15369; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v05370; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v25371; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v3, v35372; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, -v1, v2, v4 op_sel_hi:[1,0,0]5373; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v0, v3, v4 op_sel_hi:[1,0,0]5374; GFX9-FLUSH-NEXT: v_mad_f32 v5, v5, v2, v25375; GFX9-FLUSH-NEXT: v_mad_f32 v6, v6, v3, v35376; GFX9-FLUSH-NEXT: v_mad_mix_f32 v7, -v1, v5, v4 op_sel_hi:[1,0,0]5377; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v0, v6, v4 op_sel_hi:[1,0,0]5378; GFX9-FLUSH-NEXT: v_mul_f32_e32 v2, v7, v25379; GFX9-FLUSH-NEXT: v_mul_f32_e32 v3, v4, v35380; GFX9-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v25381; GFX9-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v35382; GFX9-FLUSH-NEXT: v_add_f32_e32 v2, v2, v55383; GFX9-FLUSH-NEXT: v_add_f32_e32 v3, v3, v65384; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v25385; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v35386; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, 1.05387; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v0, 1.05388; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v1, v05389; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31]5390;5391; GFX10-IEEE-LABEL: v_rsq_v2f16:5392; GFX10-IEEE: ; %bb.0:5393; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5394; GFX10-IEEE-NEXT: v_sqrt_f16_e32 v1, v05395; GFX10-IEEE-NEXT: v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15396; GFX10-IEEE-NEXT: v_mov_b32_e32 v4, 1.05397; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v15398; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v05399; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v25400; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v35401; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, -v1, v2, v4 op_sel_hi:[1,0,0]5402; GFX10-IEEE-NEXT: v_fma_mix_f32 v6, -v0, v3, v4 op_sel_hi:[1,0,0]5403; GFX10-IEEE-NEXT: v_fma_f32 v5, v5, v2, v25404; GFX10-IEEE-NEXT: v_fma_f32 v6, v6, v3, v35405; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v1, v5, v4 op_sel_hi:[1,0,0]5406; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, -v0, v6, v4 op_sel_hi:[1,0,0]5407; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v7, v25408; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v4, v35409; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v25410; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v35411; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v55412; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v65413; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v25414; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v35415; GFX10-IEEE-NEXT: v_div_fixup_f16 v1, v2, v1, 1.05416; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v3, v0, 1.05417; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v1, v05418; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]5419;5420; GFX10-FLUSH-LABEL: v_rsq_v2f16:5421; GFX10-FLUSH: ; %bb.0:5422; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5423; GFX10-FLUSH-NEXT: v_sqrt_f16_e32 v1, v05424; GFX10-FLUSH-NEXT: v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15425; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v15426; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v05427; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v4, v25428; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v35429; GFX10-FLUSH-NEXT: v_mad_f32 v6, -v2, v4, 1.05430; GFX10-FLUSH-NEXT: v_mad_f32 v7, -v3, v5, 1.05431; GFX10-FLUSH-NEXT: v_mad_f32 v6, v6, v4, v45432; GFX10-FLUSH-NEXT: v_mad_f32 v7, v7, v5, v55433; GFX10-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, 1.05434; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, 1.05435; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v45436; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v55437; GFX10-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v25438; GFX10-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v35439; GFX10-FLUSH-NEXT: v_add_f32_e32 v2, v2, v65440; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v75441; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v25442; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v35443; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, 1.05444; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v0, 1.05445; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v1, v05446; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]5447;5448; GFX11-LABEL: v_rsq_v2f16:5449; GFX11: ; %bb.0:5450; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5451; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v05452; GFX11-NEXT: v_sqrt_f16_e32 v0, v05453; GFX11-NEXT: v_mov_b32_e32 v4, 1.05454; GFX11-NEXT: v_sqrt_f16_e32 v1, v15455; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)5456; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v05457; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v15458; GFX11-NEXT: v_rcp_f32_e32 v2, v25459; GFX11-NEXT: v_rcp_f32_e32 v3, v35460; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)5461; GFX11-NEXT: v_fma_mix_f32 v5, -v0, v2, v4 op_sel_hi:[1,0,0]5462; GFX11-NEXT: v_fma_mix_f32 v6, -v1, v3, v4 op_sel_hi:[1,0,0]5463; GFX11-NEXT: v_fma_f32 v5, v5, v2, v25464; GFX11-NEXT: v_fma_f32 v6, v6, v3, v35465; GFX11-NEXT: v_fma_mix_f32 v7, -v0, v5, v4 op_sel_hi:[1,0,0]5466; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v6, v4 op_sel_hi:[1,0,0]5467; GFX11-NEXT: v_dual_mul_f32 v2, v7, v2 :: v_dual_mul_f32 v3, v4, v35468; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v25469; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_and_b32 v3, 0xff800000, v35470; GFX11-NEXT: v_add_f32_e32 v3, v3, v65471; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v25472; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v35473; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, 1.05474; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, 1.05475; GFX11-NEXT: v_pack_b32_f16 v0, v0, v15476; GFX11-NEXT: s_setpc_b64 s[30:31]5477 %sqrt = call contract <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)5478 %fdiv = fdiv contract <2 x half> <half 1.0, half 1.0>, %sqrt5479 ret <2 x half> %fdiv5480}5481 5482define <2 x half> @v_neg_rsq_v2f16(<2 x half> %a) {5483; GFX6-IEEE-LABEL: v_neg_rsq_v2f16:5484; GFX6-IEEE: ; %bb.0:5485; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5486; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v05487; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v15488; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v0, v05489; GFX6-IEEE-NEXT: v_sqrt_f32_e32 v1, v15490; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v05491; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v15492; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v0, v05493; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, v15494; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, -1.05495; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v25496; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.05497; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v1, v1, -1.05498; GFX6-IEEE-NEXT: v_fma_f32 v8, -v2, v5, 1.05499; GFX6-IEEE-NEXT: v_fma_f32 v5, v8, v5, v55500; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v45501; GFX6-IEEE-NEXT: v_mul_f32_e32 v8, v3, v55502; GFX6-IEEE-NEXT: v_fma_f32 v10, -v2, v8, v35503; GFX6-IEEE-NEXT: v_fma_f32 v8, v10, v5, v85504; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v8, v35505; GFX6-IEEE-NEXT: v_fma_f32 v9, -v4, v6, 1.05506; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v5, v85507; GFX6-IEEE-NEXT: v_div_scale_f32 v7, s[4:5], -1.0, v1, -1.05508; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, -1.05509; GFX6-IEEE-NEXT: v_fma_f32 v2, v9, v6, v65510; GFX6-IEEE-NEXT: v_mul_f32_e32 v3, v7, v25511; GFX6-IEEE-NEXT: v_fma_f32 v5, -v4, v3, v75512; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v2, v35513; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v3, v75514; GFX6-IEEE-NEXT: s_mov_b64 vcc, s[4:5]5515; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v4, v2, v35516; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, -1.05517; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v05518; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v15519; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]5520;5521; GFX6-FLUSH-LABEL: v_neg_rsq_v2f16:5522; GFX6-FLUSH: ; %bb.0:5523; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5524; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v05525; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v15526; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v0, v05527; GFX6-FLUSH-NEXT: v_sqrt_f32_e32 v1, v15528; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 05529; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v05530; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v15531; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, v05532; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, -1.05533; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v25534; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, -1.0, v0, -1.05535; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 35536; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.05537; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v35538; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v35539; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v45540; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v55541; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v45542; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 05543; GFX6-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, v15544; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v55545; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, -1.05546; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v05547; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -1.05548; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v25549; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, -1.0, v1, -1.05550; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 35551; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.05552; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v35553; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v35554; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v45555; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v55556; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v45557; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 05558; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v55559; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, -1.05560; GFX6-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v15561; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]5562;5563; GFX8-IEEE-LABEL: v_neg_rsq_v2f16:5564; GFX8-IEEE: ; %bb.0:5565; GFX8-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5566; GFX8-IEEE-NEXT: v_sqrt_f16_e32 v1, v05567; GFX8-IEEE-NEXT: v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15568; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v15569; GFX8-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v05570; GFX8-IEEE-NEXT: v_rcp_f32_e32 v4, v25571; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v35572; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v2, v45573; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v3, v55574; GFX8-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v75575; GFX8-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v65576; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v55577; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v45578; GFX8-IEEE-NEXT: v_sub_f32_e32 v7, v7, v55579; GFX8-IEEE-NEXT: v_sub_f32_e32 v6, v6, v45580; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v75581; GFX8-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v65582; GFX8-IEEE-NEXT: v_add_f32_e32 v3, -1.0, v35583; GFX8-IEEE-NEXT: v_add_f32_e32 v2, -1.0, v25584; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v55585; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v2, v45586; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v35587; GFX8-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v25588; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v75589; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v65590; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v35591; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v25592; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v3, v0, -1.05593; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v2, v1, -1.05594; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v05595; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v1, v05596; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]5597;5598; GFX8-FLUSH-LABEL: v_neg_rsq_v2f16:5599; GFX8-FLUSH: ; %bb.0:5600; GFX8-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5601; GFX8-FLUSH-NEXT: v_sqrt_f16_e32 v1, v05602; GFX8-FLUSH-NEXT: v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15603; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v15604; GFX8-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v05605; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v4, v25606; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v35607; GFX8-FLUSH-NEXT: v_mad_f32 v6, v2, v4, -1.05608; GFX8-FLUSH-NEXT: v_mad_f32 v7, v3, v5, -1.05609; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, -v55610; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, -v45611; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, -1.05612; GFX8-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, -1.05613; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v55614; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v45615; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v35616; GFX8-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v25617; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v75618; GFX8-FLUSH-NEXT: v_add_f32_e32 v2, v2, v65619; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v35620; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v25621; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v0, -1.05622; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, -1.05623; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v05624; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v1, v05625; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]5626;5627; GFX9-IEEE-LABEL: v_neg_rsq_v2f16:5628; GFX9-IEEE: ; %bb.0:5629; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5630; GFX9-IEEE-NEXT: v_sqrt_f16_e32 v1, v05631; GFX9-IEEE-NEXT: v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15632; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v15633; GFX9-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v05634; GFX9-IEEE-NEXT: v_rcp_f32_e32 v4, v25635; GFX9-IEEE-NEXT: v_rcp_f32_e32 v5, v35636; GFX9-IEEE-NEXT: v_fma_f32 v6, v2, v4, -1.05637; GFX9-IEEE-NEXT: v_fma_f32 v7, v3, v5, -1.05638; GFX9-IEEE-NEXT: v_fma_f32 v6, v6, v4, -v45639; GFX9-IEEE-NEXT: v_fma_f32 v7, v7, v5, -v55640; GFX9-IEEE-NEXT: v_fma_f32 v2, -v2, v6, -1.05641; GFX9-IEEE-NEXT: v_fma_f32 v3, -v3, v7, -1.05642; GFX9-IEEE-NEXT: v_mul_f32_e32 v2, v2, v45643; GFX9-IEEE-NEXT: v_mul_f32_e32 v3, v3, v55644; GFX9-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v25645; GFX9-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v35646; GFX9-IEEE-NEXT: v_add_f32_e32 v2, v2, v65647; GFX9-IEEE-NEXT: v_add_f32_e32 v3, v3, v75648; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v25649; GFX9-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v35650; GFX9-IEEE-NEXT: v_div_fixup_f16 v1, v2, v1, -1.05651; GFX9-IEEE-NEXT: v_div_fixup_f16 v0, v3, v0, -1.05652; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v1, v05653; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31]5654;5655; GFX9-FLUSH-LABEL: v_neg_rsq_v2f16:5656; GFX9-FLUSH: ; %bb.0:5657; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5658; GFX9-FLUSH-NEXT: v_sqrt_f16_e32 v1, v05659; GFX9-FLUSH-NEXT: v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15660; GFX9-FLUSH-NEXT: v_mov_b32_e32 v4, -1.05661; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v15662; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v05663; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v25664; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v3, v35665; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, v1, v2, v4 op_sel_hi:[1,0,0]5666; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, v0, v3, v4 op_sel_hi:[1,0,0]5667; GFX9-FLUSH-NEXT: v_mad_f32 v5, v5, v2, -v25668; GFX9-FLUSH-NEXT: v_mad_f32 v6, v6, v3, -v35669; GFX9-FLUSH-NEXT: v_mad_mix_f32 v7, -v1, v5, v4 op_sel_hi:[1,0,0]5670; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v0, v6, v4 op_sel_hi:[1,0,0]5671; GFX9-FLUSH-NEXT: v_mul_f32_e32 v2, v7, v25672; GFX9-FLUSH-NEXT: v_mul_f32_e32 v3, v4, v35673; GFX9-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v25674; GFX9-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v35675; GFX9-FLUSH-NEXT: v_add_f32_e32 v2, v2, v55676; GFX9-FLUSH-NEXT: v_add_f32_e32 v3, v3, v65677; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v25678; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v35679; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, -1.05680; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v0, -1.05681; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v1, v05682; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31]5683;5684; GFX10-IEEE-LABEL: v_neg_rsq_v2f16:5685; GFX10-IEEE: ; %bb.0:5686; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5687; GFX10-IEEE-NEXT: v_sqrt_f16_e32 v1, v05688; GFX10-IEEE-NEXT: v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15689; GFX10-IEEE-NEXT: v_mov_b32_e32 v4, -1.05690; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v15691; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v05692; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v25693; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v35694; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, v1, v2, v4 op_sel_hi:[1,0,0]5695; GFX10-IEEE-NEXT: v_fma_mix_f32 v6, v0, v3, v4 op_sel_hi:[1,0,0]5696; GFX10-IEEE-NEXT: v_fma_f32 v5, v5, v2, -v25697; GFX10-IEEE-NEXT: v_fma_f32 v6, v6, v3, -v35698; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v1, v5, v4 op_sel_hi:[1,0,0]5699; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, -v0, v6, v4 op_sel_hi:[1,0,0]5700; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v7, v25701; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v4, v35702; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v25703; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v35704; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v55705; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v65706; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v25707; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v35708; GFX10-IEEE-NEXT: v_div_fixup_f16 v1, v2, v1, -1.05709; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v3, v0, -1.05710; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v1, v05711; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]5712;5713; GFX10-FLUSH-LABEL: v_neg_rsq_v2f16:5714; GFX10-FLUSH: ; %bb.0:5715; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5716; GFX10-FLUSH-NEXT: v_sqrt_f16_e32 v1, v05717; GFX10-FLUSH-NEXT: v_sqrt_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_15718; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v15719; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v05720; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v4, v25721; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v35722; GFX10-FLUSH-NEXT: v_mad_f32 v6, v2, v4, -1.05723; GFX10-FLUSH-NEXT: v_mad_f32 v7, v3, v5, -1.05724; GFX10-FLUSH-NEXT: v_mad_f32 v6, v6, v4, -v45725; GFX10-FLUSH-NEXT: v_mad_f32 v7, v7, v5, -v55726; GFX10-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, -1.05727; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, -1.05728; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v45729; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v55730; GFX10-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v25731; GFX10-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v35732; GFX10-FLUSH-NEXT: v_add_f32_e32 v2, v2, v65733; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v75734; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v25735; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v35736; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, -1.05737; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v0, -1.05738; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v1, v05739; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]5740;5741; GFX11-LABEL: v_neg_rsq_v2f16:5742; GFX11: ; %bb.0:5743; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5744; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v05745; GFX11-NEXT: v_sqrt_f16_e32 v0, v05746; GFX11-NEXT: v_mov_b32_e32 v4, -1.05747; GFX11-NEXT: v_sqrt_f16_e32 v1, v15748; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)5749; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v05750; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v15751; GFX11-NEXT: v_rcp_f32_e32 v2, v25752; GFX11-NEXT: v_rcp_f32_e32 v3, v35753; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)5754; GFX11-NEXT: v_fma_mix_f32 v5, v0, v2, v4 op_sel_hi:[1,0,0]5755; GFX11-NEXT: v_fma_mix_f32 v6, v1, v3, v4 op_sel_hi:[1,0,0]5756; GFX11-NEXT: v_fma_f32 v5, v5, v2, -v25757; GFX11-NEXT: v_fma_f32 v6, v6, v3, -v35758; GFX11-NEXT: v_fma_mix_f32 v7, -v0, v5, v4 op_sel_hi:[1,0,0]5759; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v6, v4 op_sel_hi:[1,0,0]5760; GFX11-NEXT: v_dual_mul_f32 v2, v7, v2 :: v_dual_mul_f32 v3, v4, v35761; GFX11-NEXT: v_and_b32_e32 v2, 0xff800000, v25762; GFX11-NEXT: v_dual_add_f32 v2, v2, v5 :: v_dual_and_b32 v3, 0xff800000, v35763; GFX11-NEXT: v_add_f32_e32 v3, v3, v65764; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v25765; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v35766; GFX11-NEXT: v_div_fixup_f16 v0, v2, v0, -1.05767; GFX11-NEXT: v_div_fixup_f16 v1, v3, v1, -1.05768; GFX11-NEXT: v_pack_b32_f16 v0, v0, v15769; GFX11-NEXT: s_setpc_b64 s[30:31]5770 %sqrt = call contract <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)5771 %fdiv = fdiv contract <2 x half> <half -1.0, half -1.0>, %sqrt5772 ret <2 x half> %fdiv5773}5774 5775declare half @llvm.fabs.f16(half)5776declare half @llvm.sqrt.f16(half)5777declare <2 x half> @llvm.fabs.v2f16(<2 x half>)5778declare <2 x half> @llvm.sqrt.v2f16(<2 x half>)5779 5780;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:5781; GFX11-FLUSH: {{.*}}5782; GFX11-IEEE: {{.*}}5783