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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-FASTFMA %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-FASTFMA %s4 5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=pitcairn -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-SLOWFMA %s6; RUN: llc -global-isel -mtriple=amdgcn -mcpu=pitcairn -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-SLOWFMA %s7 8; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s9; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s10 11; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s12; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s13 14; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GFX10,GFX10-IEEE %s15; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX10,GFX10-FLUSH %s16 17; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GFX11,GFX11-IEEE %s18; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX11,GFX11-FLUSH %s19 20define float @v_fdiv_f32(float %a, float %b) {21; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32:22; GFX6-IEEE-FASTFMA: ; %bb.0:23; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)24; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v025; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v226; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v027; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.028; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v329; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v330; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v431; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v532; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v433; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v534; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v035; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]36;37; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32:38; GFX6-FLUSH-FASTFMA: ; %bb.0:39; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)40; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v041; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v242; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v043; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 344; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.045; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v346; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v347; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v448; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v549; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v450; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 051; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v552; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v053; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]54;55; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32:56; GFX6-IEEE-SLOWFMA: ; %bb.0:57; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)58; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v059; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v060; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v261; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.062; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v463; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v464; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v365; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v566; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v367; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v568; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v069; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]70;71; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32:72; GFX6-FLUSH-SLOWFMA: ; %bb.0:73; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)74; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v075; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v076; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v277; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 378; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.079; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v480; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v481; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v382; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v583; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v384; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 085; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v586; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v087; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]88;89; GFX89-IEEE-LABEL: v_fdiv_f32:90; GFX89-IEEE: ; %bb.0:91; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)92; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v093; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v094; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v295; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.096; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v497; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v498; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v399; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5100; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v3101; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5102; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0103; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]104;105; GFX89-FLUSH-LABEL: v_fdiv_f32:106; GFX89-FLUSH: ; %bb.0:107; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)108; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0109; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0110; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2111; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3112; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0113; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4114; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4115; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v3116; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5117; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v3118; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0119; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5120; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0121; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]122;123; GFX10-IEEE-LABEL: v_fdiv_f32:124; GFX10-IEEE: ; %bb.0:125; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)126; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0127; GFX10-IEEE-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0128; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2129; GFX10-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0130; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3131; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v5, v3132; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, v5133; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v3134; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v4, v5135; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4136; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0137; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]138;139; GFX10-FLUSH-LABEL: v_fdiv_f32:140; GFX10-FLUSH: ; %bb.0:141; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)142; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0143; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0144; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2145; GFX10-FLUSH-NEXT: s_denorm_mode 3146; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0147; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3148; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3149; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4150; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3151; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4152; GFX10-FLUSH-NEXT: s_denorm_mode 0153; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5154; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0155; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]156;157; GFX11-IEEE-LABEL: v_fdiv_f32:158; GFX11-IEEE: ; %bb.0:159; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)160; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v1, v1, v0161; GFX11-IEEE-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0162; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)163; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v2164; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)165; GFX11-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0166; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3167; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)168; GFX11-IEEE-NEXT: v_mul_f32_e32 v4, v5, v3169; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v4, v5170; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)171; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v3172; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v4, v5173; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)174; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4175; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0176; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]177;178; GFX11-FLUSH-LABEL: v_fdiv_f32:179; GFX11-FLUSH: ; %bb.0:180; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)181; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v1, v1, v0182; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0183; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)184; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2185; GFX11-FLUSH-NEXT: s_denorm_mode 3186; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)187; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0188; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3189; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)190; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3191; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4192; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)193; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3194; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4195; GFX11-FLUSH-NEXT: s_denorm_mode 0196; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)197; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5198; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0199; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]200 %fdiv = fdiv float %a, %b201 ret float %fdiv202}203 204 205define float @v_fdiv_f32_dynamic_denorm(float %a, float %b) #0 {206; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_dynamic_denorm:207; GFX6-IEEE-FASTFMA: ; %bb.0:208; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)209; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0210; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2211; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0212; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)213; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3214; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0215; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3216; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3217; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4218; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5219; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4220; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4221; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5222; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0223; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]224;225; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32_dynamic_denorm:226; GFX6-FLUSH-FASTFMA: ; %bb.0:227; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)228; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0229; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2230; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0231; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)232; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3233; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0234; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3235; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3236; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4237; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5238; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4239; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4240; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5241; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0242; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]243;244; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_dynamic_denorm:245; GFX6-IEEE-SLOWFMA: ; %bb.0:246; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)247; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0248; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0249; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)250; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2251; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3252; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0253; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4254; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4255; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3256; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5257; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3258; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4259; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5260; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0261; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]262;263; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32_dynamic_denorm:264; GFX6-FLUSH-SLOWFMA: ; %bb.0:265; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)266; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0267; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0268; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)269; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2270; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3271; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0272; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4273; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4274; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3275; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5276; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3277; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4278; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5279; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0280; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]281;282; GFX89-IEEE-LABEL: v_fdiv_f32_dynamic_denorm:283; GFX89-IEEE: ; %bb.0:284; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)285; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0286; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0287; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)288; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v2289; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3290; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.0291; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4292; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4293; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v3294; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5295; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v3296; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4297; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5298; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0299; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]300;301; GFX89-FLUSH-LABEL: v_fdiv_f32_dynamic_denorm:302; GFX89-FLUSH: ; %bb.0:303; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)304; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0305; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0306; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)307; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2308; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3309; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0310; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4311; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4312; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v3313; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5314; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v3315; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4316; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5317; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0318; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]319;320; GFX10-IEEE-LABEL: v_fdiv_f32_dynamic_denorm:321; GFX10-IEEE: ; %bb.0:322; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)323; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0324; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0325; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)326; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2327; GFX10-IEEE-NEXT: s_denorm_mode 15328; GFX10-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0329; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3330; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3331; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4332; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3333; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4334; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4335; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5336; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0337; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]338;339; GFX10-FLUSH-LABEL: v_fdiv_f32_dynamic_denorm:340; GFX10-FLUSH: ; %bb.0:341; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)342; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0343; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0344; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)345; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2346; GFX10-FLUSH-NEXT: s_denorm_mode 3347; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0348; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3349; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3350; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4351; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3352; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4353; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s4354; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5355; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0356; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]357;358; GFX11-IEEE-LABEL: v_fdiv_f32_dynamic_denorm:359; GFX11-IEEE: ; %bb.0:360; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)361; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v1, v1, v0362; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0363; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)364; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v2365; GFX11-IEEE-NEXT: s_denorm_mode 15366; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)367; GFX11-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0368; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)369; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v3370; GFX11-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3371; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)372; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4373; GFX11-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v3374; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)375; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4376; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0377; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5378; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)379; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0380; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]381;382; GFX11-FLUSH-LABEL: v_fdiv_f32_dynamic_denorm:383; GFX11-FLUSH: ; %bb.0:384; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)385; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v1, v1, v0386; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0387; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)388; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v2389; GFX11-FLUSH-NEXT: s_denorm_mode 3390; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)391; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0392; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)393; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v3394; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3395; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)396; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4397; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v3398; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)399; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4400; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0401; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5402; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1)403; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0404; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]405 %fdiv = fdiv float %a, %b406 ret float %fdiv407}408 409define float @v_fdiv_f32_afn(float %a, float %b) {410; GCN-LABEL: v_fdiv_f32_afn:411; GCN: ; %bb.0:412; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)413; GCN-NEXT: v_rcp_f32_e32 v1, v1414; GCN-NEXT: v_mul_f32_e32 v0, v0, v1415; GCN-NEXT: s_setpc_b64 s[30:31]416;417; GFX10-LABEL: v_fdiv_f32_afn:418; GFX10: ; %bb.0:419; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)420; GFX10-NEXT: v_rcp_f32_e32 v1, v1421; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1422; GFX10-NEXT: s_setpc_b64 s[30:31]423;424; GFX11-LABEL: v_fdiv_f32_afn:425; GFX11: ; %bb.0:426; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)427; GFX11-NEXT: v_rcp_f32_e32 v1, v1428; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)429; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1430; GFX11-NEXT: s_setpc_b64 s[30:31]431 %fdiv = fdiv afn float %a, %b432 ret float %fdiv433}434 435define float @v_fdiv_f32_ulp25(float %a, float %b) {436; GFX6-IEEE-LABEL: v_fdiv_f32_ulp25:437; GFX6-IEEE: ; %bb.0:438; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)439; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000440; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1441; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3442; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc443; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2444; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v0445; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3446; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1447; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc448; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0449; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2450; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1451; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v0452; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]453;454; GCN-FLUSH-LABEL: v_fdiv_f32_ulp25:455; GCN-FLUSH: ; %bb.0:456; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)457; GCN-FLUSH-NEXT: v_mov_b32_e32 v2, 0x6f800000458; GCN-FLUSH-NEXT: v_mov_b32_e32 v3, 0x2f800000459; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, v2460; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc461; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v2462; GCN-FLUSH-NEXT: v_rcp_f32_e32 v1, v1463; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v1464; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v2, v0465; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]466;467; GFX10-IEEE-LABEL: v_fdiv_f32_ulp25:468; GFX10-IEEE: ; %bb.0:469; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)470; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1471; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1472; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v0473; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0474; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v2475; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v0, v0, v1476; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2477; GFX10-IEEE-NEXT: v_ldexp_f32 v0, v2, v0478; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]479;480; GFX10-FLUSH-LABEL: v_fdiv_f32_ulp25:481; GFX10-FLUSH: ; %bb.0:482; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)483; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|484; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4485; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v2486; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v1, v1487; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v1488; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v2, v0489; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]490;491; GFX11-IEEE-LABEL: v_fdiv_f32_ulp25:492; GFX11-IEEE: ; %bb.0:493; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)494; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1495; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1496; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v0497; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0498; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)499; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v2500; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v0, v0, v1501; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)502; GFX11-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2503; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)504; GFX11-IEEE-NEXT: v_ldexp_f32 v0, v2, v0505; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]506;507; GFX11-FLUSH-LABEL: v_fdiv_f32_ulp25:508; GFX11-FLUSH: ; %bb.0:509; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)510; GFX11-FLUSH-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|511; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)512; GFX11-FLUSH-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0513; GFX11-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v2514; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)515; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v1, v1516; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)517; GFX11-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v1518; GFX11-FLUSH-NEXT: v_mul_f32_e32 v0, v2, v0519; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]520 %fdiv = fdiv float %a, %b, !fpmath !0521 ret float %fdiv522}523 524define float @v_fdiv_f32_dynamic_25ulp(float %x, float %y) #0 {525; GFX6-LABEL: v_fdiv_f32_dynamic_25ulp:526; GFX6: ; %bb.0:527; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)528; GFX6-NEXT: s_mov_b32 s4, 0x7f800000529; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v1530; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4531; GFX6-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc532; GFX6-NEXT: v_rcp_f32_e32 v2, v2533; GFX6-NEXT: v_frexp_mant_f32_e32 v3, v0534; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4535; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v1536; GFX6-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc537; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v0538; GFX6-NEXT: v_mul_f32_e32 v2, v3, v2539; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1540; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v0541; GFX6-NEXT: s_setpc_b64 s[30:31]542;543; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp:544; GFX7: ; %bb.0:545; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)546; GFX7-NEXT: v_frexp_mant_f32_e32 v2, v1547; GFX7-NEXT: v_rcp_f32_e32 v2, v2548; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v1549; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v3, v0550; GFX7-NEXT: v_frexp_mant_f32_e32 v0, v0551; GFX7-NEXT: v_mul_f32_e32 v0, v0, v2552; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v3, v1553; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1554; GFX7-NEXT: s_setpc_b64 s[30:31]555;556; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp:557; GFX8: ; %bb.0:558; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)559; GFX8-NEXT: v_frexp_mant_f32_e32 v2, v1560; GFX8-NEXT: v_rcp_f32_e32 v2, v2561; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v1562; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v3, v0563; GFX8-NEXT: v_frexp_mant_f32_e32 v0, v0564; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2565; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v3, v1566; GFX8-NEXT: v_ldexp_f32 v0, v0, v1567; GFX8-NEXT: s_setpc_b64 s[30:31]568;569; GFX6-IEEE-LABEL: v_fdiv_f32_dynamic_25ulp:570; GFX6-IEEE: ; %bb.0:571; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)572; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f800000573; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v1574; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3575; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc576; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v2577; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v0578; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3579; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1580; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc581; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0582; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v2583; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v1584; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v0585; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]586;587; GFX6-FLUSH-LABEL: v_fdiv_f32_dynamic_25ulp:588; GFX6-FLUSH: ; %bb.0:589; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)590; GFX6-FLUSH-NEXT: v_mov_b32_e32 v3, 0x7f800000591; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v2, v1592; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3593; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc594; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v2595; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v4, v0596; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3597; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v1598; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc599; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v0600; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v2601; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v1602; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v2, v0603; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]604;605; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp:606; GFX10: ; %bb.0:607; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)608; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v1609; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v1610; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v0611; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0612; GFX10-NEXT: v_rcp_f32_e32 v2, v2613; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1614; GFX10-NEXT: v_mul_f32_e32 v2, v3, v2615; GFX10-NEXT: v_ldexp_f32 v0, v2, v0616; GFX10-NEXT: s_setpc_b64 s[30:31]617;618; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp:619; GFX11: ; %bb.0:620; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)621; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v1622; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v1623; GFX11-NEXT: v_frexp_mant_f32_e32 v3, v0624; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0625; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)626; GFX11-NEXT: v_rcp_f32_e32 v2, v2627; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v1628; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)629; GFX11-NEXT: v_mul_f32_e32 v2, v3, v2630; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)631; GFX11-NEXT: v_ldexp_f32 v0, v2, v0632; GFX11-NEXT: s_setpc_b64 s[30:31]633; EG-LABEL: v_fdiv_f32_dynamic_25ulp:634; EG: ; %bb.0:635; EG-NEXT: CF_END636; EG-NEXT: PAD637 %div = fdiv float %x, %y, !fpmath !0638 ret float %div639}640 641define float @v_rcp_f32(float %x) {642; GFX6-IEEE-FASTFMA-LABEL: v_rcp_f32:643; GFX6-IEEE-FASTFMA: ; %bb.0:644; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)645; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0646; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1647; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0648; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0649; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2650; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2651; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3652; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4653; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3654; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4655; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0656; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]657;658; GFX6-FLUSH-FASTFMA-LABEL: v_rcp_f32:659; GFX6-FLUSH-FASTFMA: ; %bb.0:660; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)661; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0662; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1663; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0664; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3665; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0666; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2667; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2668; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3669; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4670; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3671; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0672; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4673; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0674; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]675;676; GFX6-IEEE-SLOWFMA-LABEL: v_rcp_f32:677; GFX6-IEEE-SLOWFMA: ; %bb.0:678; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)679; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0680; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0681; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1682; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0683; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3684; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3685; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2686; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4687; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2688; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4689; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0690; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]691;692; GFX6-FLUSH-SLOWFMA-LABEL: v_rcp_f32:693; GFX6-FLUSH-SLOWFMA: ; %bb.0:694; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)695; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0696; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0697; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1698; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3699; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0700; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3701; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3702; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2703; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4704; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2705; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0706; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4707; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0708; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]709;710; GFX89-IEEE-LABEL: v_rcp_f32:711; GFX89-IEEE: ; %bb.0:712; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)713; GFX89-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0714; GFX89-IEEE-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0715; GFX89-IEEE-NEXT: v_rcp_f32_e32 v3, v1716; GFX89-IEEE-NEXT: v_fma_f32 v4, -v1, v3, 1.0717; GFX89-IEEE-NEXT: v_fma_f32 v3, v4, v3, v3718; GFX89-IEEE-NEXT: v_mul_f32_e32 v4, v2, v3719; GFX89-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v2720; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v3, v4721; GFX89-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v2722; GFX89-IEEE-NEXT: v_div_fmas_f32 v1, v1, v3, v4723; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0724; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]725;726; GFX89-FLUSH-LABEL: v_rcp_f32:727; GFX89-FLUSH: ; %bb.0:728; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)729; GFX89-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0730; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0731; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v3, v1732; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3733; GFX89-FLUSH-NEXT: v_fma_f32 v4, -v1, v3, 1.0734; GFX89-FLUSH-NEXT: v_fma_f32 v3, v4, v3, v3735; GFX89-FLUSH-NEXT: v_mul_f32_e32 v4, v2, v3736; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v2737; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v3, v4738; GFX89-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v2739; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0740; GFX89-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v3, v4741; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0742; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]743;744; GFX10-IEEE-LABEL: v_rcp_f32:745; GFX10-IEEE: ; %bb.0:746; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)747; GFX10-IEEE-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0748; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0749; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v1750; GFX10-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0751; GFX10-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2752; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2753; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4754; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v2755; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4756; GFX10-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v3757; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0758; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]759;760; GFX10-FLUSH-LABEL: v_rcp_f32:761; GFX10-FLUSH: ; %bb.0:762; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)763; GFX10-FLUSH-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0764; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0765; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v1766; GFX10-FLUSH-NEXT: s_denorm_mode 3767; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0768; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2769; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2770; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3771; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2772; GFX10-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3773; GFX10-FLUSH-NEXT: s_denorm_mode 0774; GFX10-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4775; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0776; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]777;778; GFX11-IEEE-LABEL: v_rcp_f32:779; GFX11-IEEE: ; %bb.0:780; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)781; GFX11-IEEE-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0782; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0783; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)784; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v1785; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)786; GFX11-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0787; GFX11-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2788; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)789; GFX11-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2790; GFX11-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4791; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)792; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v2793; GFX11-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4794; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)795; GFX11-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v3796; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0797; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]798;799; GFX11-FLUSH-LABEL: v_rcp_f32:800; GFX11-FLUSH: ; %bb.0:801; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)802; GFX11-FLUSH-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0803; GFX11-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0804; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)805; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v1806; GFX11-FLUSH-NEXT: s_denorm_mode 3807; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)808; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0809; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2810; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)811; GFX11-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2812; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3813; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)814; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2815; GFX11-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3816; GFX11-FLUSH-NEXT: s_denorm_mode 0817; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)818; GFX11-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4819; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0820; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]821 %fdiv = fdiv float 1.0, %x822 ret float %fdiv823}824 825define float @v_rcp_f32_arcp(float %x) {826; GFX6-IEEE-FASTFMA-LABEL: v_rcp_f32_arcp:827; GFX6-IEEE-FASTFMA: ; %bb.0:828; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)829; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0830; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1831; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0832; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0833; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2834; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2835; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3836; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4837; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3838; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4839; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0840; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]841;842; GFX6-FLUSH-FASTFMA-LABEL: v_rcp_f32_arcp:843; GFX6-FLUSH-FASTFMA: ; %bb.0:844; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)845; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0846; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1847; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0848; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3849; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0850; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2851; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2852; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3853; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4854; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3855; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0856; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4857; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0858; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]859;860; GFX6-IEEE-SLOWFMA-LABEL: v_rcp_f32_arcp:861; GFX6-IEEE-SLOWFMA: ; %bb.0:862; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)863; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0864; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0865; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1866; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0867; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3868; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3869; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2870; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4871; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2872; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4873; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0874; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]875;876; GFX6-FLUSH-SLOWFMA-LABEL: v_rcp_f32_arcp:877; GFX6-FLUSH-SLOWFMA: ; %bb.0:878; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)879; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0880; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0881; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1882; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3883; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0884; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3885; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3886; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2887; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4888; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2889; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0890; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4891; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0892; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]893;894; GFX89-IEEE-LABEL: v_rcp_f32_arcp:895; GFX89-IEEE: ; %bb.0:896; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)897; GFX89-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0898; GFX89-IEEE-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0899; GFX89-IEEE-NEXT: v_rcp_f32_e32 v3, v1900; GFX89-IEEE-NEXT: v_fma_f32 v4, -v1, v3, 1.0901; GFX89-IEEE-NEXT: v_fma_f32 v3, v4, v3, v3902; GFX89-IEEE-NEXT: v_mul_f32_e32 v4, v2, v3903; GFX89-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v2904; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v3, v4905; GFX89-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v2906; GFX89-IEEE-NEXT: v_div_fmas_f32 v1, v1, v3, v4907; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0908; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]909;910; GFX89-FLUSH-LABEL: v_rcp_f32_arcp:911; GFX89-FLUSH: ; %bb.0:912; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)913; GFX89-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0914; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0915; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v3, v1916; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3917; GFX89-FLUSH-NEXT: v_fma_f32 v4, -v1, v3, 1.0918; GFX89-FLUSH-NEXT: v_fma_f32 v3, v4, v3, v3919; GFX89-FLUSH-NEXT: v_mul_f32_e32 v4, v2, v3920; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v2921; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v3, v4922; GFX89-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v2923; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0924; GFX89-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v3, v4925; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0926; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]927;928; GFX10-IEEE-LABEL: v_rcp_f32_arcp:929; GFX10-IEEE: ; %bb.0:930; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)931; GFX10-IEEE-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0932; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0933; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v1934; GFX10-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0935; GFX10-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2936; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2937; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4938; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v2939; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4940; GFX10-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v3941; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0942; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]943;944; GFX10-FLUSH-LABEL: v_rcp_f32_arcp:945; GFX10-FLUSH: ; %bb.0:946; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)947; GFX10-FLUSH-NEXT: v_div_scale_f32 v1, s4, v0, v0, 1.0948; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0949; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v1950; GFX10-FLUSH-NEXT: s_denorm_mode 3951; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0952; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2953; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2954; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3955; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2956; GFX10-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3957; GFX10-FLUSH-NEXT: s_denorm_mode 0958; GFX10-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4959; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0960; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]961;962; GFX11-IEEE-LABEL: v_rcp_f32_arcp:963; GFX11-IEEE: ; %bb.0:964; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)965; GFX11-IEEE-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0966; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0967; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)968; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v1969; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)970; GFX11-IEEE-NEXT: v_fma_f32 v3, -v1, v2, 1.0971; GFX11-IEEE-NEXT: v_fmac_f32_e32 v2, v3, v2972; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)973; GFX11-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2974; GFX11-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4975; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)976; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v2977; GFX11-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4978; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)979; GFX11-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v3980; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0981; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]982;983; GFX11-FLUSH-LABEL: v_rcp_f32_arcp:984; GFX11-FLUSH: ; %bb.0:985; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)986; GFX11-FLUSH-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0987; GFX11-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0988; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)989; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v1990; GFX11-FLUSH-NEXT: s_denorm_mode 3991; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)992; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0993; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2994; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)995; GFX11-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2996; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3997; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)998; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2999; GFX11-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v31000; GFX11-FLUSH-NEXT: s_denorm_mode 01001; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1002; GFX11-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v41003; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.01004; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]1005 %fdiv = fdiv arcp float 1.0, %x1006 ret float %fdiv1007}1008 1009define float @v_rcp_f32_arcp_afn(float %x) {1010; GCN-LABEL: v_rcp_f32_arcp_afn:1011; GCN: ; %bb.0:1012; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1013; GCN-NEXT: v_rcp_f32_e32 v0, v01014; GCN-NEXT: s_setpc_b64 s[30:31]1015;1016; GFX10-LABEL: v_rcp_f32_arcp_afn:1017; GFX10: ; %bb.0:1018; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1019; GFX10-NEXT: v_rcp_f32_e32 v0, v01020; GFX10-NEXT: s_setpc_b64 s[30:31]1021;1022; GFX11-LABEL: v_rcp_f32_arcp_afn:1023; GFX11: ; %bb.0:1024; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1025; GFX11-NEXT: v_rcp_f32_e32 v0, v01026; GFX11-NEXT: s_setpc_b64 s[30:31]1027 %fdiv = fdiv arcp afn float 1.0, %x1028 ret float %fdiv1029}1030 1031define float @v_rcp_f32_ulp25(float %x) {1032; GFX6-IEEE-LABEL: v_rcp_f32_ulp25:1033; GFX6-IEEE: ; %bb.0:1034; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1035; GFX6-IEEE-NEXT: v_mov_b32_e32 v2, 0x7f8000001036; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v1, v01037; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v21038; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc1039; GFX6-IEEE-NEXT: v_rcp_f32_e32 v1, v11040; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01041; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01042; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v1, v01043; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]1044;1045; GCN-FLUSH-LABEL: v_rcp_f32_ulp25:1046; GCN-FLUSH: ; %bb.0:1047; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1048; GCN-FLUSH-NEXT: v_rcp_f32_e32 v0, v01049; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]1050;1051; GFX10-IEEE-LABEL: v_rcp_f32_ulp25:1052; GFX10-IEEE: ; %bb.0:1053; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1054; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v1, v01055; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01056; GFX10-IEEE-NEXT: v_rcp_f32_e32 v1, v11057; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v0, 0, v01058; GFX10-IEEE-NEXT: v_ldexp_f32 v0, v1, v01059; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]1060;1061; GFX10-FLUSH-LABEL: v_rcp_f32_ulp25:1062; GFX10-FLUSH: ; %bb.0:1063; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1064; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v0, v01065; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]1066;1067; GFX11-IEEE-LABEL: v_rcp_f32_ulp25:1068; GFX11-IEEE: ; %bb.0:1069; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1070; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v1, v01071; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01072; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1073; GFX11-IEEE-NEXT: v_rcp_f32_e32 v1, v11074; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v0, 0, v01075; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1076; GFX11-IEEE-NEXT: v_ldexp_f32 v0, v1, v01077; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]1078;1079; GFX11-FLUSH-LABEL: v_rcp_f32_ulp25:1080; GFX11-FLUSH: ; %bb.0:1081; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1082; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v0, v01083; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]1084 %fdiv = fdiv float 1.0, %x, !fpmath !01085 ret float %fdiv1086}1087 1088define float @v_fdiv_f32_afn_ulp25(float %a, float %b) {1089; GCN-LABEL: v_fdiv_f32_afn_ulp25:1090; GCN: ; %bb.0:1091; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1092; GCN-NEXT: v_rcp_f32_e32 v1, v11093; GCN-NEXT: v_mul_f32_e32 v0, v0, v11094; GCN-NEXT: s_setpc_b64 s[30:31]1095;1096; GFX10-LABEL: v_fdiv_f32_afn_ulp25:1097; GFX10: ; %bb.0:1098; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1099; GFX10-NEXT: v_rcp_f32_e32 v1, v11100; GFX10-NEXT: v_mul_f32_e32 v0, v0, v11101; GFX10-NEXT: s_setpc_b64 s[30:31]1102;1103; GFX11-LABEL: v_fdiv_f32_afn_ulp25:1104; GFX11: ; %bb.0:1105; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1106; GFX11-NEXT: v_rcp_f32_e32 v1, v11107; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1108; GFX11-NEXT: v_mul_f32_e32 v0, v0, v11109; GFX11-NEXT: s_setpc_b64 s[30:31]1110 %fdiv = fdiv afn float %a, %b, !fpmath !01111 ret float %fdiv1112}1113 1114define float @v_fdiv_f32_arcp_ulp25(float %a, float %b) {1115; GFX6-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:1116; GFX6-IEEE: ; %bb.0:1117; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1118; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f8000001119; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v11120; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v31121; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc1122; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v21123; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v11124; GFX6-IEEE-NEXT: v_sub_i32_e32 v1, vcc, 0, v11125; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v1, v2, v11126; GFX6-IEEE-NEXT: v_mul_f32_e32 v0, v0, v11127; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]1128;1129; GCN-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:1130; GCN-FLUSH: ; %bb.0:1131; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1132; GCN-FLUSH-NEXT: v_rcp_f32_e32 v1, v11133; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v11134; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]1135;1136; GFX10-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:1137; GFX10-IEEE: ; %bb.0:1138; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1139; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v11140; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v11141; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v21142; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v1, 0, v11143; GFX10-IEEE-NEXT: v_ldexp_f32 v1, v2, v11144; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v0, v11145; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]1146;1147; GFX10-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:1148; GFX10-FLUSH: ; %bb.0:1149; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1150; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v1, v11151; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v11152; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]1153;1154; GFX11-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:1155; GFX11-IEEE: ; %bb.0:1156; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1157; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v11158; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v11159; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1160; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v21161; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v1, 0, v11162; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1163; GFX11-IEEE-NEXT: v_ldexp_f32 v1, v2, v11164; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)1165; GFX11-IEEE-NEXT: v_mul_f32_e32 v0, v0, v11166; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]1167;1168; GFX11-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:1169; GFX11-FLUSH: ; %bb.0:1170; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1171; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v1, v11172; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1173; GFX11-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v11174; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]1175 %fdiv = fdiv arcp float %a, %b, !fpmath !01176 ret float %fdiv1177}1178 1179define <2 x float> @v_fdiv_v2f32(<2 x float> %a, <2 x float> %b) {1180; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_v2f32:1181; GFX6-IEEE-FASTFMA: ; %bb.0:1182; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1183; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v01184; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v5, v41185; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v01186; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, -v4, v5, 1.01187; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v7, v5, v51188; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v7, v6, v51189; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v8, -v4, v7, v61190; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, v8, v5, v71191; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v4, v7, v61192; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v4, v4, v5, v71193; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v11194; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v6, v51195; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v01196; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v11197; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v5, v6, 1.01198; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v4, v6, v61199; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v6, v2, v41200; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, -v5, v6, v21201; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v61202; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v5, v6, v21203; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v61204; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v3, v11205; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]1206;1207; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_v2f32:1208; GFX6-FLUSH-FASTFMA: ; %bb.0:1209; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1210; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v01211; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v5, v41212; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v01213; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31214; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v7, -v4, v5, 1.01215; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v7, v5, v51216; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v7, v6, v51217; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v8, -v4, v7, v61218; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v7, v8, v5, v71219; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, -v4, v7, v61220; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01221; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v4, v4, v5, v71222; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v11223; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v6, v51224; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v01225; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v11226; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31227; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, -v5, v6, 1.01228; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v4, v6, v61229; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v6, v2, v41230; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v7, -v5, v6, v21231; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v61232; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v5, v6, v21233; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01234; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v61235; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v3, v11236; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]1237;1238; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_v2f32:1239; GFX6-IEEE-SLOWFMA: ; %bb.0:1240; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1241; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v01242; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v11243; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v01244; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v7, s[4:5], v1, v3, v11245; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v8, v41246; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v9, v51247; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, -v4, v8, 1.01248; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, v10, v8, v81249; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, -v5, v9, 1.01250; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, v11, v9, v91251; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v10, v6, v81252; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v11, v7, v91253; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v12, -v4, v10, v61254; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v13, -v5, v11, v71255; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, v12, v8, v101256; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, v13, v9, v111257; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, -v4, v10, v61258; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v5, v11, v71259; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v4, v4, v8, v101260; GFX6-IEEE-SLOWFMA-NEXT: s_mov_b64 vcc, s[4:5]1261; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v5, v5, v9, v111262; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v01263; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v1, v5, v3, v11264; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]1265;1266; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_v2f32:1267; GFX6-FLUSH-SLOWFMA: ; %bb.0:1268; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1269; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v01270; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v5, vcc, v0, v2, v01271; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v6, v41272; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31273; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v7, -v4, v6, 1.01274; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, v7, v6, v61275; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v7, v5, v61276; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v8, -v4, v7, v51277; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v7, v8, v6, v71278; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, -v4, v7, v51279; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01280; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v11281; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v4, v4, v6, v71282; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v6, vcc, v1, v3, v11283; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v7, v51284; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v01285; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31286; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v5, v7, 1.01287; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, v2, v7, v71288; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v4, v6, v21289; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v7, -v5, v4, v61290; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v7, v2, v41291; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v5, v4, v61292; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01293; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v5, v2, v41294; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v1, v2, v3, v11295; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]1296;1297; GFX89-IEEE-LABEL: v_fdiv_v2f32:1298; GFX89-IEEE: ; %bb.0:1299; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1300; GFX89-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v01301; GFX89-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v11302; GFX89-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v01303; GFX89-IEEE-NEXT: v_div_scale_f32 v7, s[4:5], v1, v3, v11304; GFX89-IEEE-NEXT: v_rcp_f32_e32 v8, v41305; GFX89-IEEE-NEXT: v_rcp_f32_e32 v9, v51306; GFX89-IEEE-NEXT: v_fma_f32 v10, -v4, v8, 1.01307; GFX89-IEEE-NEXT: v_fma_f32 v8, v10, v8, v81308; GFX89-IEEE-NEXT: v_fma_f32 v11, -v5, v9, 1.01309; GFX89-IEEE-NEXT: v_fma_f32 v9, v11, v9, v91310; GFX89-IEEE-NEXT: v_mul_f32_e32 v10, v6, v81311; GFX89-IEEE-NEXT: v_mul_f32_e32 v11, v7, v91312; GFX89-IEEE-NEXT: v_fma_f32 v12, -v4, v10, v61313; GFX89-IEEE-NEXT: v_fma_f32 v13, -v5, v11, v71314; GFX89-IEEE-NEXT: v_fma_f32 v10, v12, v8, v101315; GFX89-IEEE-NEXT: v_fma_f32 v11, v13, v9, v111316; GFX89-IEEE-NEXT: v_fma_f32 v4, -v4, v10, v61317; GFX89-IEEE-NEXT: v_fma_f32 v5, -v5, v11, v71318; GFX89-IEEE-NEXT: v_div_fmas_f32 v4, v4, v8, v101319; GFX89-IEEE-NEXT: s_mov_b64 vcc, s[4:5]1320; GFX89-IEEE-NEXT: v_div_fmas_f32 v5, v5, v9, v111321; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v01322; GFX89-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v11323; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]1324;1325; GFX89-FLUSH-LABEL: v_fdiv_v2f32:1326; GFX89-FLUSH: ; %bb.0:1327; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1328; GFX89-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v01329; GFX89-FLUSH-NEXT: v_div_scale_f32 v5, vcc, v0, v2, v01330; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v6, v41331; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31332; GFX89-FLUSH-NEXT: v_fma_f32 v7, -v4, v6, 1.01333; GFX89-FLUSH-NEXT: v_fma_f32 v6, v7, v6, v61334; GFX89-FLUSH-NEXT: v_mul_f32_e32 v7, v5, v61335; GFX89-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v51336; GFX89-FLUSH-NEXT: v_fma_f32 v7, v8, v6, v71337; GFX89-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v51338; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01339; GFX89-FLUSH-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v11340; GFX89-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v6, v71341; GFX89-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v1, v3, v11342; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v7, v51343; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v01344; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31345; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v5, v7, 1.01346; GFX89-FLUSH-NEXT: v_fma_f32 v2, v2, v7, v71347; GFX89-FLUSH-NEXT: v_mul_f32_e32 v4, v6, v21348; GFX89-FLUSH-NEXT: v_fma_f32 v7, -v5, v4, v61349; GFX89-FLUSH-NEXT: v_fma_f32 v4, v7, v2, v41350; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v5, v4, v61351; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01352; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v5, v2, v41353; GFX89-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v11354; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]1355;1356; GFX10-IEEE-LABEL: v_fdiv_v2f32:1357; GFX10-IEEE: ; %bb.0:1358; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1359; GFX10-IEEE-NEXT: v_div_scale_f32 v4, s4, v2, v2, v01360; GFX10-IEEE-NEXT: v_div_scale_f32 v5, s4, v3, v3, v11361; GFX10-IEEE-NEXT: v_div_scale_f32 v10, vcc_lo, v0, v2, v01362; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v41363; GFX10-IEEE-NEXT: v_rcp_f32_e32 v7, v51364; GFX10-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.01365; GFX10-IEEE-NEXT: v_fma_f32 v9, -v5, v7, 1.01366; GFX10-IEEE-NEXT: v_fmac_f32_e32 v6, v8, v61367; GFX10-IEEE-NEXT: v_div_scale_f32 v8, s4, v1, v3, v11368; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v9, v71369; GFX10-IEEE-NEXT: v_mul_f32_e32 v9, v10, v61370; GFX10-IEEE-NEXT: v_mul_f32_e32 v11, v8, v71371; GFX10-IEEE-NEXT: v_fma_f32 v12, -v4, v9, v101372; GFX10-IEEE-NEXT: v_fma_f32 v13, -v5, v11, v81373; GFX10-IEEE-NEXT: v_fmac_f32_e32 v9, v12, v61374; GFX10-IEEE-NEXT: v_fmac_f32_e32 v11, v13, v71375; GFX10-IEEE-NEXT: v_fma_f32 v4, -v4, v9, v101376; GFX10-IEEE-NEXT: v_fma_f32 v5, -v5, v11, v81377; GFX10-IEEE-NEXT: v_div_fmas_f32 v4, v4, v6, v91378; GFX10-IEEE-NEXT: s_mov_b32 vcc_lo, s41379; GFX10-IEEE-NEXT: v_div_fmas_f32 v5, v5, v7, v111380; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v01381; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v11382; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]1383;1384; GFX10-FLUSH-LABEL: v_fdiv_v2f32:1385; GFX10-FLUSH: ; %bb.0:1386; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1387; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, s4, v2, v2, v01388; GFX10-FLUSH-NEXT: v_div_scale_f32 v6, vcc_lo, v0, v2, v01389; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v41390; GFX10-FLUSH-NEXT: s_denorm_mode 31391; GFX10-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.01392; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v7, v51393; GFX10-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v51394; GFX10-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v61395; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v7, v8, v51396; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v61397; GFX10-FLUSH-NEXT: s_denorm_mode 01398; GFX10-FLUSH-NEXT: v_div_scale_f32 v6, s4, v3, v3, v11399; GFX10-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v71400; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v61401; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v01402; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v1, v3, v11403; GFX10-FLUSH-NEXT: s_denorm_mode 31404; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v6, v5, 1.01405; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v4, v51406; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v2, v51407; GFX10-FLUSH-NEXT: v_fma_f32 v7, -v6, v4, v21408; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v7, v51409; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v6, v4, v21410; GFX10-FLUSH-NEXT: s_denorm_mode 01411; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v5, v41412; GFX10-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v11413; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]1414;1415; GFX11-IEEE-LABEL: v_fdiv_v2f32:1416; GFX11-IEEE: ; %bb.0:1417; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1418; GFX11-IEEE-NEXT: v_div_scale_f32 v4, null, v2, v2, v01419; GFX11-IEEE-NEXT: v_div_scale_f32 v5, null, v3, v3, v11420; GFX11-IEEE-NEXT: v_div_scale_f32 v10, vcc_lo, v0, v2, v01421; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1422; GFX11-IEEE-NEXT: v_rcp_f32_e32 v6, v41423; GFX11-IEEE-NEXT: v_rcp_f32_e32 v7, v51424; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1425; GFX11-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.01426; GFX11-IEEE-NEXT: v_fma_f32 v9, -v5, v7, 1.01427; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1428; GFX11-IEEE-NEXT: v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v71429; GFX11-IEEE-NEXT: v_div_scale_f32 v8, s0, v1, v3, v11430; GFX11-IEEE-NEXT: v_mul_f32_e32 v9, v10, v61431; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1432; GFX11-IEEE-NEXT: v_mul_f32_e32 v11, v8, v71433; GFX11-IEEE-NEXT: v_fma_f32 v12, -v4, v9, v101434; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1435; GFX11-IEEE-NEXT: v_fma_f32 v13, -v5, v11, v81436; GFX11-IEEE-NEXT: v_fmac_f32_e32 v9, v12, v61437; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1438; GFX11-IEEE-NEXT: v_fmac_f32_e32 v11, v13, v71439; GFX11-IEEE-NEXT: v_fma_f32 v4, -v4, v9, v101440; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1441; GFX11-IEEE-NEXT: v_fma_f32 v5, -v5, v11, v81442; GFX11-IEEE-NEXT: v_div_fmas_f32 v4, v4, v6, v91443; GFX11-IEEE-NEXT: s_mov_b32 vcc_lo, s01444; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1445; GFX11-IEEE-NEXT: v_div_fmas_f32 v5, v5, v7, v111446; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v01447; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2)1448; GFX11-IEEE-NEXT: v_div_fixup_f32 v1, v5, v3, v11449; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]1450;1451; GFX11-FLUSH-LABEL: v_fdiv_v2f32:1452; GFX11-FLUSH: ; %bb.0:1453; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1454; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, null, v2, v2, v01455; GFX11-FLUSH-NEXT: v_div_scale_f32 v6, vcc_lo, v0, v2, v01456; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)1457; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v5, v41458; GFX11-FLUSH-NEXT: s_denorm_mode 31459; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1460; GFX11-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.01461; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v7, v51462; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1463; GFX11-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v51464; GFX11-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v61465; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1466; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v7, v8, v51467; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v61468; GFX11-FLUSH-NEXT: s_denorm_mode 01469; GFX11-FLUSH-NEXT: v_div_scale_f32 v6, null, v3, v3, v11470; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1471; GFX11-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v71472; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v5, v61473; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)1474; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v01475; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v1, v3, v11476; GFX11-FLUSH-NEXT: s_denorm_mode 31477; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1478; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v6, v5, 1.01479; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v4, v51480; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1481; GFX11-FLUSH-NEXT: v_mul_f32_e32 v4, v2, v51482; GFX11-FLUSH-NEXT: v_fma_f32 v7, -v6, v4, v21483; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1484; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v7, v51485; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v6, v4, v21486; GFX11-FLUSH-NEXT: s_denorm_mode 01487; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1488; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v5, v41489; GFX11-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v11490; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]1491 %fdiv = fdiv <2 x float> %a, %b1492 ret <2 x float> %fdiv1493}1494 1495define <2 x float> @v_fdiv_v2f32_afn(<2 x float> %a, <2 x float> %b) {1496; GCN-LABEL: v_fdiv_v2f32_afn:1497; GCN: ; %bb.0:1498; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1499; GCN-NEXT: v_rcp_f32_e32 v2, v21500; GCN-NEXT: v_rcp_f32_e32 v3, v31501; GCN-NEXT: v_mul_f32_e32 v0, v0, v21502; GCN-NEXT: v_mul_f32_e32 v1, v1, v31503; GCN-NEXT: s_setpc_b64 s[30:31]1504;1505; GFX10-LABEL: v_fdiv_v2f32_afn:1506; GFX10: ; %bb.0:1507; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1508; GFX10-NEXT: v_rcp_f32_e32 v2, v21509; GFX10-NEXT: v_rcp_f32_e32 v3, v31510; GFX10-NEXT: v_mul_f32_e32 v0, v0, v21511; GFX10-NEXT: v_mul_f32_e32 v1, v1, v31512; GFX10-NEXT: s_setpc_b64 s[30:31]1513;1514; GFX11-LABEL: v_fdiv_v2f32_afn:1515; GFX11: ; %bb.0:1516; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1517; GFX11-NEXT: v_rcp_f32_e32 v2, v21518; GFX11-NEXT: v_rcp_f32_e32 v3, v31519; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1520; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v31521; GFX11-NEXT: s_setpc_b64 s[30:31]1522 %fdiv = fdiv afn <2 x float> %a, %b1523 ret <2 x float> %fdiv1524}1525 1526define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) {1527; GFX6-IEEE-LABEL: v_fdiv_v2f32_ulp25:1528; GFX6-IEEE: ; %bb.0:1529; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1530; GFX6-IEEE-NEXT: v_mov_b32_e32 v5, 0x7f8000001531; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v21532; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v51533; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc1534; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v6, v01535; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v51536; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v21537; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v6, v0, v6, vcc1538; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01539; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v41540; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v21541; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v31542; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v51543; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc1544; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v21545; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v6, v41546; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v4, v01547; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v11548; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v51549; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v31550; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v4, v1, v4, vcc1551; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v11552; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v4, v21553; GFX6-IEEE-NEXT: v_sub_i32_e32 v1, vcc, v1, v31554; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v1, v2, v11555; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]1556;1557; GCN-FLUSH-LABEL: v_fdiv_v2f32_ulp25:1558; GCN-FLUSH: ; %bb.0:1559; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1560; GCN-FLUSH-NEXT: v_mov_b32_e32 v4, 0x6f8000001561; GCN-FLUSH-NEXT: v_mov_b32_e32 v5, 0x2f8000001562; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, v41563; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v6, 1.0, v5, vcc1564; GCN-FLUSH-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, v41565; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v4, 1.0, v5, vcc1566; GCN-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v61567; GCN-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v41568; GCN-FLUSH-NEXT: v_rcp_f32_e32 v2, v21569; GCN-FLUSH-NEXT: v_rcp_f32_e32 v3, v31570; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v21571; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v31572; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v6, v01573; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v4, v11574; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]1575;1576; GFX10-IEEE-LABEL: v_fdiv_v2f32_ulp25:1577; GFX10-IEEE: ; %bb.0:1578; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1579; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v21580; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v5, v31581; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v21582; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v6, v01583; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v31584; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v41585; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v51586; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v7, v11587; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v0, v01588; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v1, v11589; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v2, v6, v21590; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v3, v7, v31591; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v0, v41592; GFX10-IEEE-NEXT: v_mul_f32_e32 v1, v1, v51593; GFX10-IEEE-NEXT: v_ldexp_f32 v0, v0, v21594; GFX10-IEEE-NEXT: v_ldexp_f32 v1, v1, v31595; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]1596;1597; GFX10-FLUSH-LABEL: v_fdiv_v2f32_ulp25:1598; GFX10-FLUSH: ; %bb.0:1599; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1600; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v2|1601; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s41602; GFX10-FLUSH-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v3|1603; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v41604; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v5, 1.0, 0x2f800000, s41605; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v21606; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v51607; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v31608; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v21609; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v4, v01610; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v31611; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v5, v11612; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]1613;1614; GFX11-IEEE-LABEL: v_fdiv_v2f32_ulp25:1615; GFX11-IEEE: ; %bb.0:1616; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1617; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v21618; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v5, v31619; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v21620; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v6, v01621; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v31622; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v41623; GFX11-IEEE-NEXT: v_rcp_f32_e32 v5, v51624; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v7, v11625; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v0, v01626; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v1, v11627; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v2, v6, v21628; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)1629; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v3, v7, v31630; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1631; GFX11-IEEE-NEXT: v_dual_mul_f32 v0, v0, v4 :: v_dual_mul_f32 v1, v1, v51632; GFX11-IEEE-NEXT: v_ldexp_f32 v0, v0, v21633; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2)1634; GFX11-IEEE-NEXT: v_ldexp_f32 v1, v1, v31635; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]1636;1637; GFX11-FLUSH-LABEL: v_fdiv_v2f32_ulp25:1638; GFX11-FLUSH: ; %bb.0:1639; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1640; GFX11-FLUSH-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v2|1641; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)1642; GFX11-FLUSH-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s01643; GFX11-FLUSH-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v3|1644; GFX11-FLUSH-NEXT: v_cndmask_b32_e64 v5, 1.0, 0x2f800000, s01645; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1646; GFX11-FLUSH-NEXT: v_dual_mul_f32 v2, v2, v4 :: v_dual_mul_f32 v3, v3, v51647; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v21648; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)1649; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v31650; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1651; GFX11-FLUSH-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v31652; GFX11-FLUSH-NEXT: v_dual_mul_f32 v0, v4, v0 :: v_dual_mul_f32 v1, v5, v11653; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]1654 %fdiv = fdiv <2 x float> %a, %b, !fpmath !01655 ret <2 x float> %fdiv1656}1657 1658define <2 x float> @v_rcp_v2f32(<2 x float> %x) {1659; GFX6-IEEE-FASTFMA-LABEL: v_rcp_v2f32:1660; GFX6-IEEE-FASTFMA: ; %bb.0:1661; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1662; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.01663; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v21664; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.01665; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.01666; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v31667; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v31668; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v41669; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v51670; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v41671; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v51672; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.01673; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v4, v31674; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.01675; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.01676; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.01677; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v41678; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v41679; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v21680; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v51681; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v21682; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v51683; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.01684; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]1685;1686; GFX6-FLUSH-FASTFMA-LABEL: v_rcp_v2f32:1687; GFX6-FLUSH-FASTFMA: ; %bb.0:1688; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1689; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.01690; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v21691; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.01692; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31693; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.01694; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v31695; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v31696; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v41697; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v51698; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v41699; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01700; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v51701; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.01702; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v4, v31703; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.01704; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.01705; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31706; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.01707; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v41708; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v41709; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v21710; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v51711; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v21712; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01713; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v51714; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.01715; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]1716;1717; GFX6-IEEE-SLOWFMA-LABEL: v_rcp_v2f32:1718; GFX6-IEEE-SLOWFMA: ; %bb.0:1719; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1720; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.01721; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.01722; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.01723; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.01724; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v6, v21725; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v7, v31726; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, -v2, v6, 1.01727; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, v8, v6, v61728; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, -v3, v7, 1.01729; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v7, v9, v7, v71730; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v8, v4, v61731; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v9, v5, v71732; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, -v2, v8, v41733; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, -v3, v9, v51734; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, v10, v6, v81735; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, v11, v7, v91736; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v8, v41737; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v9, v51738; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v6, v81739; GFX6-IEEE-SLOWFMA-NEXT: s_mov_b64 vcc, s[4:5]1740; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v7, v91741; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.01742; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v1, v3, v1, 1.01743; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]1744;1745; GFX6-FLUSH-SLOWFMA-LABEL: v_rcp_v2f32:1746; GFX6-FLUSH-SLOWFMA: ; %bb.0:1747; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1748; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.01749; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.01750; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v21751; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31752; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.01753; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v41754; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v41755; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v31756; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v51757; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v31758; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01759; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.01760; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v51761; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.01762; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v31763; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.01764; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31765; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, 1.01766; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, v2, v5, v51767; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v4, v21768; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v41769; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v2, v51770; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v5, v41771; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01772; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v3, v2, v51773; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.01774; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]1775;1776; GFX89-IEEE-LABEL: v_rcp_v2f32:1777; GFX89-IEEE: ; %bb.0:1778; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1779; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.01780; GFX89-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.01781; GFX89-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.01782; GFX89-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.01783; GFX89-IEEE-NEXT: v_rcp_f32_e32 v6, v21784; GFX89-IEEE-NEXT: v_rcp_f32_e32 v7, v31785; GFX89-IEEE-NEXT: v_fma_f32 v8, -v2, v6, 1.01786; GFX89-IEEE-NEXT: v_fma_f32 v6, v8, v6, v61787; GFX89-IEEE-NEXT: v_fma_f32 v9, -v3, v7, 1.01788; GFX89-IEEE-NEXT: v_fma_f32 v7, v9, v7, v71789; GFX89-IEEE-NEXT: v_mul_f32_e32 v8, v4, v61790; GFX89-IEEE-NEXT: v_mul_f32_e32 v9, v5, v71791; GFX89-IEEE-NEXT: v_fma_f32 v10, -v2, v8, v41792; GFX89-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v51793; GFX89-IEEE-NEXT: v_fma_f32 v8, v10, v6, v81794; GFX89-IEEE-NEXT: v_fma_f32 v9, v11, v7, v91795; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v8, v41796; GFX89-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v51797; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v6, v81798; GFX89-IEEE-NEXT: s_mov_b64 vcc, s[4:5]1799; GFX89-IEEE-NEXT: v_div_fmas_f32 v3, v3, v7, v91800; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.01801; GFX89-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.01802; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]1803;1804; GFX89-FLUSH-LABEL: v_rcp_v2f32:1805; GFX89-FLUSH: ; %bb.0:1806; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1807; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.01808; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.01809; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v21810; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31811; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.01812; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v41813; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v41814; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v31815; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v51816; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v31817; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01818; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.01819; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v51820; GFX89-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.01821; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v5, v31822; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.01823; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 31824; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, 1.01825; GFX89-FLUSH-NEXT: v_fma_f32 v2, v2, v5, v51826; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v21827; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v41828; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v2, v51829; GFX89-FLUSH-NEXT: v_fma_f32 v3, -v3, v5, v41830; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 01831; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v3, v2, v51832; GFX89-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.01833; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]1834;1835; GFX10-IEEE-LABEL: v_rcp_v2f32:1836; GFX10-IEEE: ; %bb.0:1837; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1838; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.01839; GFX10-IEEE-NEXT: v_div_scale_f32 v3, s4, v1, v1, 1.01840; GFX10-IEEE-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.01841; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v21842; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v31843; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.01844; GFX10-IEEE-NEXT: v_fma_f32 v7, -v3, v5, 1.01845; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v41846; GFX10-IEEE-NEXT: v_div_scale_f32 v6, s4, 1.0, v1, 1.01847; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v7, v51848; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v8, v41849; GFX10-IEEE-NEXT: v_mul_f32_e32 v9, v6, v51850; GFX10-IEEE-NEXT: v_fma_f32 v10, -v2, v7, v81851; GFX10-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v61852; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v41853; GFX10-IEEE-NEXT: v_fmac_f32_e32 v9, v11, v51854; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v81855; GFX10-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v61856; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v71857; GFX10-IEEE-NEXT: s_mov_b32 vcc_lo, s41858; GFX10-IEEE-NEXT: v_div_fmas_f32 v3, v3, v5, v91859; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.01860; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.01861; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]1862;1863; GFX10-FLUSH-LABEL: v_rcp_v2f32:1864; GFX10-FLUSH: ; %bb.0:1865; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1866; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.01867; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.01868; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v21869; GFX10-FLUSH-NEXT: s_denorm_mode 31870; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.01871; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v31872; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v31873; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v41874; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v31875; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v41876; GFX10-FLUSH-NEXT: s_denorm_mode 01877; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, s4, v1, v1, 1.01878; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v51879; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v41880; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.01881; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.01882; GFX10-FLUSH-NEXT: s_denorm_mode 31883; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.01884; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v31885; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v31886; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v21887; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v31888; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v21889; GFX10-FLUSH-NEXT: s_denorm_mode 01890; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v51891; GFX10-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.01892; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]1893;1894; GFX11-IEEE-LABEL: v_rcp_v2f32:1895; GFX11-IEEE: ; %bb.0:1896; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1897; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v0, v0, 1.01898; GFX11-IEEE-NEXT: v_div_scale_f32 v3, null, v1, v1, 1.01899; GFX11-IEEE-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.01900; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1901; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v21902; GFX11-IEEE-NEXT: v_rcp_f32_e32 v5, v31903; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1904; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.01905; GFX11-IEEE-NEXT: v_fma_f32 v7, -v3, v5, 1.01906; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1907; GFX11-IEEE-NEXT: v_dual_fmac_f32 v4, v6, v4 :: v_dual_fmac_f32 v5, v7, v51908; GFX11-IEEE-NEXT: v_div_scale_f32 v6, s0, 1.0, v1, 1.01909; GFX11-IEEE-NEXT: v_mul_f32_e32 v7, v8, v41910; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1911; GFX11-IEEE-NEXT: v_mul_f32_e32 v9, v6, v51912; GFX11-IEEE-NEXT: v_fma_f32 v10, -v2, v7, v81913; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1914; GFX11-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v61915; GFX11-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v41916; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1917; GFX11-IEEE-NEXT: v_fmac_f32_e32 v9, v11, v51918; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v81919; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1920; GFX11-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v61921; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v71922; GFX11-IEEE-NEXT: s_mov_b32 vcc_lo, s01923; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1924; GFX11-IEEE-NEXT: v_div_fmas_f32 v3, v3, v5, v91925; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.01926; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2)1927; GFX11-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.01928; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]1929;1930; GFX11-FLUSH-LABEL: v_rcp_v2f32:1931; GFX11-FLUSH: ; %bb.0:1932; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1933; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v0, v0, 1.01934; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.01935; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)1936; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v21937; GFX11-FLUSH-NEXT: s_denorm_mode 31938; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1939; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.01940; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v31941; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1942; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v31943; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v41944; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1945; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v31946; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v41947; GFX11-FLUSH-NEXT: s_denorm_mode 01948; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.01949; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1950; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v51951; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v41952; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)1953; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.01954; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.01955; GFX11-FLUSH-NEXT: s_denorm_mode 31956; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)1957; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.01958; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v31959; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1960; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v31961; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v21962; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1963; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v31964; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v21965; GFX11-FLUSH-NEXT: s_denorm_mode 01966; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1967; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v51968; GFX11-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.01969; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]1970 %fdiv = fdiv <2 x float> <float 1.0, float 1.0>, %x1971 ret <2 x float> %fdiv1972}1973 1974define <2 x float> @v_rcp_v2f32_arcp(<2 x float> %x) {1975; GFX6-IEEE-FASTFMA-LABEL: v_rcp_v2f32_arcp:1976; GFX6-IEEE-FASTFMA: ; %bb.0:1977; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1978; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.01979; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v21980; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.01981; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.01982; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v31983; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v31984; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v41985; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v51986; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v41987; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v51988; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.01989; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v4, v31990; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.01991; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.01992; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.01993; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v41994; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v41995; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v21996; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v51997; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v21998; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v51999; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.02000; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]2001;2002; GFX6-FLUSH-FASTFMA-LABEL: v_rcp_v2f32_arcp:2003; GFX6-FLUSH-FASTFMA: ; %bb.0:2004; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2005; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.02006; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v22007; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.02008; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32009; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.02010; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v32011; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v32012; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v42013; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v52014; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v42015; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02016; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v52017; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.02018; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v4, v32019; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.02020; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.02021; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32022; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.02023; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v42024; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v42025; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v22026; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v52027; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v22028; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02029; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v52030; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.02031; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]2032;2033; GFX6-IEEE-SLOWFMA-LABEL: v_rcp_v2f32_arcp:2034; GFX6-IEEE-SLOWFMA: ; %bb.0:2035; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2036; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.02037; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.02038; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.02039; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.02040; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v6, v22041; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v7, v32042; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, -v2, v6, 1.02043; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, v8, v6, v62044; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, -v3, v7, 1.02045; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v7, v9, v7, v72046; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v8, v4, v62047; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v9, v5, v72048; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, -v2, v8, v42049; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, -v3, v9, v52050; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, v10, v6, v82051; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, v11, v7, v92052; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v8, v42053; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v9, v52054; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v6, v82055; GFX6-IEEE-SLOWFMA-NEXT: s_mov_b64 vcc, s[4:5]2056; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v7, v92057; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.02058; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v1, v3, v1, 1.02059; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]2060;2061; GFX6-FLUSH-SLOWFMA-LABEL: v_rcp_v2f32_arcp:2062; GFX6-FLUSH-SLOWFMA: ; %bb.0:2063; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2064; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.02065; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.02066; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v22067; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32068; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.02069; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v42070; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v42071; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v32072; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v52073; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v32074; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02075; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.02076; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v52077; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.02078; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v32079; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.02080; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32081; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, 1.02082; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, v2, v5, v52083; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v4, v22084; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v42085; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v2, v52086; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v5, v42087; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02088; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v3, v2, v52089; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.02090; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]2091;2092; GFX89-IEEE-LABEL: v_rcp_v2f32_arcp:2093; GFX89-IEEE: ; %bb.0:2094; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2095; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.02096; GFX89-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.02097; GFX89-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.02098; GFX89-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.02099; GFX89-IEEE-NEXT: v_rcp_f32_e32 v6, v22100; GFX89-IEEE-NEXT: v_rcp_f32_e32 v7, v32101; GFX89-IEEE-NEXT: v_fma_f32 v8, -v2, v6, 1.02102; GFX89-IEEE-NEXT: v_fma_f32 v6, v8, v6, v62103; GFX89-IEEE-NEXT: v_fma_f32 v9, -v3, v7, 1.02104; GFX89-IEEE-NEXT: v_fma_f32 v7, v9, v7, v72105; GFX89-IEEE-NEXT: v_mul_f32_e32 v8, v4, v62106; GFX89-IEEE-NEXT: v_mul_f32_e32 v9, v5, v72107; GFX89-IEEE-NEXT: v_fma_f32 v10, -v2, v8, v42108; GFX89-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v52109; GFX89-IEEE-NEXT: v_fma_f32 v8, v10, v6, v82110; GFX89-IEEE-NEXT: v_fma_f32 v9, v11, v7, v92111; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v8, v42112; GFX89-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v52113; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v6, v82114; GFX89-IEEE-NEXT: s_mov_b64 vcc, s[4:5]2115; GFX89-IEEE-NEXT: v_div_fmas_f32 v3, v3, v7, v92116; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.02117; GFX89-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.02118; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]2119;2120; GFX89-FLUSH-LABEL: v_rcp_v2f32_arcp:2121; GFX89-FLUSH: ; %bb.0:2122; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2123; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.02124; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.02125; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v22126; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32127; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.02128; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v42129; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v42130; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v32131; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v52132; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v32133; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02134; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.02135; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v52136; GFX89-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.02137; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v5, v32138; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.02139; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32140; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, 1.02141; GFX89-FLUSH-NEXT: v_fma_f32 v2, v2, v5, v52142; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v22143; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v42144; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v2, v52145; GFX89-FLUSH-NEXT: v_fma_f32 v3, -v3, v5, v42146; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 02147; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v3, v2, v52148; GFX89-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.02149; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]2150;2151; GFX10-IEEE-LABEL: v_rcp_v2f32_arcp:2152; GFX10-IEEE: ; %bb.0:2153; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2154; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.02155; GFX10-IEEE-NEXT: v_div_scale_f32 v3, s4, v1, v1, 1.02156; GFX10-IEEE-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.02157; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v22158; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v32159; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.02160; GFX10-IEEE-NEXT: v_fma_f32 v7, -v3, v5, 1.02161; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v42162; GFX10-IEEE-NEXT: v_div_scale_f32 v6, s4, 1.0, v1, 1.02163; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v7, v52164; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v8, v42165; GFX10-IEEE-NEXT: v_mul_f32_e32 v9, v6, v52166; GFX10-IEEE-NEXT: v_fma_f32 v10, -v2, v7, v82167; GFX10-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v62168; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v42169; GFX10-IEEE-NEXT: v_fmac_f32_e32 v9, v11, v52170; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v82171; GFX10-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v62172; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v72173; GFX10-IEEE-NEXT: s_mov_b32 vcc_lo, s42174; GFX10-IEEE-NEXT: v_div_fmas_f32 v3, v3, v5, v92175; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.02176; GFX10-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.02177; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]2178;2179; GFX10-FLUSH-LABEL: v_rcp_v2f32_arcp:2180; GFX10-FLUSH: ; %bb.0:2181; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2182; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v0, v0, 1.02183; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.02184; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v22185; GFX10-FLUSH-NEXT: s_denorm_mode 32186; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.02187; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v32188; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v32189; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v42190; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v32191; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v42192; GFX10-FLUSH-NEXT: s_denorm_mode 02193; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, s4, v1, v1, 1.02194; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v52195; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v42196; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.02197; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.02198; GFX10-FLUSH-NEXT: s_denorm_mode 32199; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.02200; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v32201; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v32202; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v22203; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v32204; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v22205; GFX10-FLUSH-NEXT: s_denorm_mode 02206; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v52207; GFX10-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.02208; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]2209;2210; GFX11-IEEE-LABEL: v_rcp_v2f32_arcp:2211; GFX11-IEEE: ; %bb.0:2212; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2213; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v0, v0, 1.02214; GFX11-IEEE-NEXT: v_div_scale_f32 v3, null, v1, v1, 1.02215; GFX11-IEEE-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v0, 1.02216; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)2217; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v22218; GFX11-IEEE-NEXT: v_rcp_f32_e32 v5, v32219; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2220; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.02221; GFX11-IEEE-NEXT: v_fma_f32 v7, -v3, v5, 1.02222; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)2223; GFX11-IEEE-NEXT: v_dual_fmac_f32 v4, v6, v4 :: v_dual_fmac_f32 v5, v7, v52224; GFX11-IEEE-NEXT: v_div_scale_f32 v6, s0, 1.0, v1, 1.02225; GFX11-IEEE-NEXT: v_mul_f32_e32 v7, v8, v42226; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2227; GFX11-IEEE-NEXT: v_mul_f32_e32 v9, v6, v52228; GFX11-IEEE-NEXT: v_fma_f32 v10, -v2, v7, v82229; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2230; GFX11-IEEE-NEXT: v_fma_f32 v11, -v3, v9, v62231; GFX11-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v42232; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2233; GFX11-IEEE-NEXT: v_fmac_f32_e32 v9, v11, v52234; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v82235; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2236; GFX11-IEEE-NEXT: v_fma_f32 v3, -v3, v9, v62237; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v72238; GFX11-IEEE-NEXT: s_mov_b32 vcc_lo, s02239; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2240; GFX11-IEEE-NEXT: v_div_fmas_f32 v3, v3, v5, v92241; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.02242; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2)2243; GFX11-IEEE-NEXT: v_div_fixup_f32 v1, v3, v1, 1.02244; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]2245;2246; GFX11-FLUSH-LABEL: v_rcp_v2f32_arcp:2247; GFX11-FLUSH: ; %bb.0:2248; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2249; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v0, v0, 1.02250; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.02251; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)2252; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v22253; GFX11-FLUSH-NEXT: s_denorm_mode 32254; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2255; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.02256; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v32257; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2258; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v32259; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v42260; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2261; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v32262; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v42263; GFX11-FLUSH-NEXT: s_denorm_mode 02264; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.02265; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2266; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v52267; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v42268; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)2269; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.02270; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.02271; GFX11-FLUSH-NEXT: s_denorm_mode 32272; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2273; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.02274; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v32275; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2276; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v32277; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v22278; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2279; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v32280; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v22281; GFX11-FLUSH-NEXT: s_denorm_mode 02282; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2283; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v52284; GFX11-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.02285; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]2286 %fdiv = fdiv arcp <2 x float> <float 1.0, float 1.0>, %x2287 ret <2 x float> %fdiv2288}2289 2290define <2 x float> @v_rcp_v2f32_arcp_afn(<2 x float> %x) {2291; GCN-LABEL: v_rcp_v2f32_arcp_afn:2292; GCN: ; %bb.0:2293; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2294; GCN-NEXT: v_rcp_f32_e32 v0, v02295; GCN-NEXT: v_rcp_f32_e32 v1, v12296; GCN-NEXT: s_setpc_b64 s[30:31]2297;2298; GFX10-LABEL: v_rcp_v2f32_arcp_afn:2299; GFX10: ; %bb.0:2300; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2301; GFX10-NEXT: v_rcp_f32_e32 v0, v02302; GFX10-NEXT: v_rcp_f32_e32 v1, v12303; GFX10-NEXT: s_setpc_b64 s[30:31]2304;2305; GFX11-LABEL: v_rcp_v2f32_arcp_afn:2306; GFX11: ; %bb.0:2307; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2308; GFX11-NEXT: v_rcp_f32_e32 v0, v02309; GFX11-NEXT: v_rcp_f32_e32 v1, v12310; GFX11-NEXT: s_setpc_b64 s[30:31]2311 %fdiv = fdiv arcp afn <2 x float> <float 1.0, float 1.0>, %x2312 ret <2 x float> %fdiv2313}2314 2315define <2 x float> @v_rcp_v2f32_ulp25(<2 x float> %x) {2316; GFX6-IEEE-LABEL: v_rcp_v2f32_ulp25:2317; GFX6-IEEE: ; %bb.0:2318; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2319; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f8000002320; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v02321; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v32322; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc2323; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v22324; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v02325; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, 0, v02326; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v02327; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v12328; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v32329; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc2330; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v22331; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v12332; GFX6-IEEE-NEXT: v_sub_i32_e32 v1, vcc, 0, v12333; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v1, v2, v12334; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]2335;2336; GCN-FLUSH-LABEL: v_rcp_v2f32_ulp25:2337; GCN-FLUSH: ; %bb.0:2338; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2339; GCN-FLUSH-NEXT: v_rcp_f32_e32 v0, v02340; GCN-FLUSH-NEXT: v_rcp_f32_e32 v1, v12341; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]2342;2343; GFX10-IEEE-LABEL: v_rcp_v2f32_ulp25:2344; GFX10-IEEE: ; %bb.0:2345; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2346; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v02347; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v12348; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v02349; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v12350; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v22351; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v32352; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v0, 0, v02353; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v1, 0, v12354; GFX10-IEEE-NEXT: v_ldexp_f32 v0, v2, v02355; GFX10-IEEE-NEXT: v_ldexp_f32 v1, v3, v12356; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]2357;2358; GFX10-FLUSH-LABEL: v_rcp_v2f32_ulp25:2359; GFX10-FLUSH: ; %bb.0:2360; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2361; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v0, v02362; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v1, v12363; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]2364;2365; GFX11-IEEE-LABEL: v_rcp_v2f32_ulp25:2366; GFX11-IEEE: ; %bb.0:2367; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2368; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v02369; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v12370; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v02371; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v12372; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)2373; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v22374; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v32375; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2376; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v0, 0, v02377; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v1, 0, v12378; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2379; GFX11-IEEE-NEXT: v_ldexp_f32 v0, v2, v02380; GFX11-IEEE-NEXT: v_ldexp_f32 v1, v3, v12381; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]2382;2383; GFX11-FLUSH-LABEL: v_rcp_v2f32_ulp25:2384; GFX11-FLUSH: ; %bb.0:2385; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2386; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v0, v02387; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v1, v12388; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]2389 %fdiv = fdiv <2 x float> <float 1.0, float 1.0>, %x, !fpmath !02390 ret <2 x float> %fdiv2391}2392 2393define <2 x float> @v_fdiv_v2f32_afn_ulp25(<2 x float> %a, <2 x float> %b) {2394; GCN-LABEL: v_fdiv_v2f32_afn_ulp25:2395; GCN: ; %bb.0:2396; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2397; GCN-NEXT: v_rcp_f32_e32 v2, v22398; GCN-NEXT: v_rcp_f32_e32 v3, v32399; GCN-NEXT: v_mul_f32_e32 v0, v0, v22400; GCN-NEXT: v_mul_f32_e32 v1, v1, v32401; GCN-NEXT: s_setpc_b64 s[30:31]2402;2403; GFX10-LABEL: v_fdiv_v2f32_afn_ulp25:2404; GFX10: ; %bb.0:2405; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2406; GFX10-NEXT: v_rcp_f32_e32 v2, v22407; GFX10-NEXT: v_rcp_f32_e32 v3, v32408; GFX10-NEXT: v_mul_f32_e32 v0, v0, v22409; GFX10-NEXT: v_mul_f32_e32 v1, v1, v32410; GFX10-NEXT: s_setpc_b64 s[30:31]2411;2412; GFX11-LABEL: v_fdiv_v2f32_afn_ulp25:2413; GFX11: ; %bb.0:2414; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2415; GFX11-NEXT: v_rcp_f32_e32 v2, v22416; GFX11-NEXT: v_rcp_f32_e32 v3, v32417; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2418; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v32419; GFX11-NEXT: s_setpc_b64 s[30:31]2420 %fdiv = fdiv afn <2 x float> %a, %b, !fpmath !02421 ret <2 x float> %fdiv2422}2423 2424define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) {2425; GFX6-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:2426; GFX6-IEEE: ; %bb.0:2427; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2428; GFX6-IEEE-NEXT: v_mov_b32_e32 v5, 0x7f8000002429; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v22430; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, v52431; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc2432; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v42433; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v22434; GFX6-IEEE-NEXT: v_sub_i32_e32 v2, vcc, 0, v22435; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v2, v4, v22436; GFX6-IEEE-NEXT: v_mul_f32_e32 v0, v0, v22437; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v32438; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v52439; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc2440; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v22441; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v32442; GFX6-IEEE-NEXT: v_sub_i32_e32 v3, vcc, 0, v32443; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v2, v2, v32444; GFX6-IEEE-NEXT: v_mul_f32_e32 v1, v1, v22445; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]2446;2447; GCN-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:2448; GCN-FLUSH: ; %bb.0:2449; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2450; GCN-FLUSH-NEXT: v_rcp_f32_e32 v2, v22451; GCN-FLUSH-NEXT: v_rcp_f32_e32 v3, v32452; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v22453; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v32454; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]2455;2456; GFX10-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:2457; GFX10-IEEE: ; %bb.0:2458; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2459; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v22460; GFX10-IEEE-NEXT: v_frexp_mant_f32_e32 v5, v32461; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v22462; GFX10-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v32463; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v42464; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v52465; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v2, 0, v22466; GFX10-IEEE-NEXT: v_sub_nc_u32_e32 v3, 0, v32467; GFX10-IEEE-NEXT: v_ldexp_f32 v2, v4, v22468; GFX10-IEEE-NEXT: v_ldexp_f32 v3, v5, v32469; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v0, v22470; GFX10-IEEE-NEXT: v_mul_f32_e32 v1, v1, v32471; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]2472;2473; GFX10-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:2474; GFX10-FLUSH: ; %bb.0:2475; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2476; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v22477; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v32478; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v22479; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v32480; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]2481;2482; GFX11-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:2483; GFX11-IEEE: ; %bb.0:2484; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2485; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v22486; GFX11-IEEE-NEXT: v_frexp_mant_f32_e32 v5, v32487; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, v22488; GFX11-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v3, v32489; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)2490; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v42491; GFX11-IEEE-NEXT: v_rcp_f32_e32 v5, v52492; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2493; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v2, 0, v22494; GFX11-IEEE-NEXT: v_sub_nc_u32_e32 v3, 0, v32495; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2496; GFX11-IEEE-NEXT: v_ldexp_f32 v2, v4, v22497; GFX11-IEEE-NEXT: v_ldexp_f32 v3, v5, v32498; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)2499; GFX11-IEEE-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v32500; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]2501;2502; GFX11-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:2503; GFX11-FLUSH: ; %bb.0:2504; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2505; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v22506; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v32507; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2508; GFX11-FLUSH-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v32509; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]2510 %fdiv = fdiv arcp <2 x float> %a, %b, !fpmath !02511 ret <2 x float> %fdiv2512}2513 2514define <2 x float> @v_fdiv_v2f32_arcp_afn_ulp25(<2 x float> %a, <2 x float> %b) {2515; GCN-LABEL: v_fdiv_v2f32_arcp_afn_ulp25:2516; GCN: ; %bb.0:2517; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2518; GCN-NEXT: v_rcp_f32_e32 v2, v22519; GCN-NEXT: v_rcp_f32_e32 v3, v32520; GCN-NEXT: v_mul_f32_e32 v0, v0, v22521; GCN-NEXT: v_mul_f32_e32 v1, v1, v32522; GCN-NEXT: s_setpc_b64 s[30:31]2523;2524; GFX10-LABEL: v_fdiv_v2f32_arcp_afn_ulp25:2525; GFX10: ; %bb.0:2526; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2527; GFX10-NEXT: v_rcp_f32_e32 v2, v22528; GFX10-NEXT: v_rcp_f32_e32 v3, v32529; GFX10-NEXT: v_mul_f32_e32 v0, v0, v22530; GFX10-NEXT: v_mul_f32_e32 v1, v1, v32531; GFX10-NEXT: s_setpc_b64 s[30:31]2532;2533; GFX11-LABEL: v_fdiv_v2f32_arcp_afn_ulp25:2534; GFX11: ; %bb.0:2535; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2536; GFX11-NEXT: v_rcp_f32_e32 v2, v22537; GFX11-NEXT: v_rcp_f32_e32 v3, v32538; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2539; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v32540; GFX11-NEXT: s_setpc_b64 s[30:31]2541 %fdiv = fdiv afn arcp <2 x float> %a, %b, !fpmath !02542 ret <2 x float> %fdiv2543}2544 2545 2546define float @v_fdiv_f32_dynamic__nnan_ninf(float %x, float %y, float %z) #0 {2547; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2548; GFX6-FASTFMA: ; %bb.0:2549; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2550; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v02551; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v22552; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.02553; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v32554; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v02555; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v32556; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v42557; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v52558; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v42559; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v52560; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v02561; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]2562;2563; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2564; GFX6-SLOWFMA: ; %bb.0:2565; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2566; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v02567; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v02568; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v22569; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.02570; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v42571; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v42572; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v32573; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v52574; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v32575; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v52576; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v02577; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]2578;2579; GFX7-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2580; GFX7: ; %bb.0:2581; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2582; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v02583; GFX7-NEXT: v_rcp_f32_e32 v3, v22584; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.02585; GFX7-NEXT: v_fma_f32 v3, v4, v3, v32586; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v02587; GFX7-NEXT: v_mul_f32_e32 v5, v4, v32588; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v42589; GFX7-NEXT: v_fma_f32 v5, v6, v3, v52590; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v42591; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v52592; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v02593; GFX7-NEXT: s_setpc_b64 s[30:31]2594;2595; GFX8-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2596; GFX8: ; %bb.0:2597; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2598; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v02599; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v02600; GFX8-NEXT: v_rcp_f32_e32 v4, v22601; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.02602; GFX8-NEXT: v_fma_f32 v4, v5, v4, v42603; GFX8-NEXT: v_mul_f32_e32 v5, v3, v42604; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v32605; GFX8-NEXT: v_fma_f32 v5, v6, v4, v52606; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v32607; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v52608; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v02609; GFX8-NEXT: s_setpc_b64 s[30:31]2610;2611; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2612; GFX6-IEEE-FASTFMA: ; %bb.0:2613; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2614; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v02615; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v22616; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v02617; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)2618; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32619; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.02620; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v32621; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v32622; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v42623; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v52624; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v42625; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s42626; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v52627; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v02628; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]2629;2630; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2631; GFX6-FLUSH-FASTFMA: ; %bb.0:2632; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2633; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v02634; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v22635; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v02636; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)2637; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32638; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.02639; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v32640; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v32641; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v42642; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v52643; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v42644; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s42645; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v52646; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v02647; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]2648;2649; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2650; GFX6-IEEE-SLOWFMA: ; %bb.0:2651; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2652; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v02653; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v02654; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)2655; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v22656; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32657; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.02658; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v42659; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v42660; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v32661; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v52662; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v32663; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s42664; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v52665; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v02666; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]2667;2668; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2669; GFX6-FLUSH-SLOWFMA: ; %bb.0:2670; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2671; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v02672; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v02673; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)2674; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v22675; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32676; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.02677; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v42678; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v42679; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v32680; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v52681; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v32682; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s42683; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v52684; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v02685; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]2686;2687; GFX89-IEEE-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2688; GFX89-IEEE: ; %bb.0:2689; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2690; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v02691; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v02692; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)2693; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v22694; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32695; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.02696; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v42697; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v42698; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v32699; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v52700; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v32701; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s42702; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v52703; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v02704; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]2705;2706; GFX89-FLUSH-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2707; GFX89-FLUSH: ; %bb.0:2708; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2709; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v02710; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v02711; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)2712; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v22713; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 32714; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.02715; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v42716; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v42717; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v32718; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v52719; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v32720; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s42721; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v52722; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v02723; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]2724;2725; GFX10-IEEE-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2726; GFX10-IEEE: ; %bb.0:2727; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2728; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v02729; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v02730; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)2731; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v22732; GFX10-IEEE-NEXT: s_denorm_mode 152733; GFX10-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.02734; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v32735; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v32736; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v42737; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v32738; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v42739; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s42740; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v52741; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v02742; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]2743;2744; GFX10-FLUSH-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2745; GFX10-FLUSH: ; %bb.0:2746; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2747; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v1, v1, v02748; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v02749; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)2750; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v22751; GFX10-FLUSH-NEXT: s_denorm_mode 32752; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.02753; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v32754; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v32755; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v42756; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v32757; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v42758; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s42759; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v52760; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v02761; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]2762;2763; GFX11-IEEE-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2764; GFX11-IEEE: ; %bb.0:2765; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2766; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v1, v1, v02767; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v02768; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)2769; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v22770; GFX11-IEEE-NEXT: s_denorm_mode 152771; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2772; GFX11-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.02773; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2774; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v32775; GFX11-IEEE-NEXT: v_mul_f32_e32 v5, v4, v32776; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2777; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v42778; GFX11-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v32779; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)2780; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v42781; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s02782; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v52783; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)2784; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v02785; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]2786;2787; GFX11-FLUSH-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2788; GFX11-FLUSH: ; %bb.0:2789; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2790; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v1, v1, v02791; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v02792; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)2793; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v22794; GFX11-FLUSH-NEXT: s_denorm_mode 32795; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2796; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.02797; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2798; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v32799; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v32800; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2801; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v42802; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v32803; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)2804; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v42805; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s02806; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v52807; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1)2808; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v02809; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]2810; EG-LABEL: v_fdiv_f32_dynamic__nnan_ninf:2811; EG: ; %bb.0:2812; EG-NEXT: CF_END2813; EG-NEXT: PAD2814 %div = fdiv nnan ninf float %x, %y2815 ret float %div2816}2817 2818define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf(float %x, float %y, float %z) #0 {2819; GFX6-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:2820; GFX6: ; %bb.0:2821; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2822; GFX6-NEXT: s_mov_b32 s4, 0x7f8000002823; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v12824; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s42825; GFX6-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc2826; GFX6-NEXT: v_rcp_f32_e32 v2, v22827; GFX6-NEXT: v_frexp_mant_f32_e32 v3, v02828; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s42829; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v12830; GFX6-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc2831; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v02832; GFX6-NEXT: v_mul_f32_e32 v2, v3, v22833; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v12834; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v02835; GFX6-NEXT: s_setpc_b64 s[30:31]2836;2837; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:2838; GFX7: ; %bb.0:2839; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2840; GFX7-NEXT: v_frexp_mant_f32_e32 v2, v12841; GFX7-NEXT: v_rcp_f32_e32 v2, v22842; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v12843; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v3, v02844; GFX7-NEXT: v_frexp_mant_f32_e32 v0, v02845; GFX7-NEXT: v_mul_f32_e32 v0, v0, v22846; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v3, v12847; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v12848; GFX7-NEXT: s_setpc_b64 s[30:31]2849;2850; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:2851; GFX8: ; %bb.0:2852; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2853; GFX8-NEXT: v_frexp_mant_f32_e32 v2, v12854; GFX8-NEXT: v_rcp_f32_e32 v2, v22855; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v12856; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v3, v02857; GFX8-NEXT: v_frexp_mant_f32_e32 v0, v02858; GFX8-NEXT: v_mul_f32_e32 v0, v0, v22859; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v3, v12860; GFX8-NEXT: v_ldexp_f32 v0, v0, v12861; GFX8-NEXT: s_setpc_b64 s[30:31]2862;2863; GFX6-IEEE-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:2864; GFX6-IEEE: ; %bb.0:2865; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2866; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f8000002867; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v12868; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v32869; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc2870; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v22871; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v02872; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v32873; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v12874; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc2875; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v02876; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v22877; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v12878; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v02879; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]2880;2881; GFX6-FLUSH-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:2882; GFX6-FLUSH: ; %bb.0:2883; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2884; GFX6-FLUSH-NEXT: v_mov_b32_e32 v3, 0x7f8000002885; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v2, v12886; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v32887; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc2888; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v22889; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v4, v02890; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v32891; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v12892; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc2893; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v02894; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v22895; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v12896; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v2, v02897; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]2898;2899; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:2900; GFX10: ; %bb.0:2901; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2902; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v12903; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v12904; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v02905; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v02906; GFX10-NEXT: v_rcp_f32_e32 v2, v22907; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v12908; GFX10-NEXT: v_mul_f32_e32 v2, v3, v22909; GFX10-NEXT: v_ldexp_f32 v0, v2, v02910; GFX10-NEXT: s_setpc_b64 s[30:31]2911;2912; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:2913; GFX11: ; %bb.0:2914; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2915; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v12916; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v12917; GFX11-NEXT: v_frexp_mant_f32_e32 v3, v02918; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v02919; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)2920; GFX11-NEXT: v_rcp_f32_e32 v2, v22921; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v12922; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)2923; GFX11-NEXT: v_mul_f32_e32 v2, v3, v22924; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2925; GFX11-NEXT: v_ldexp_f32 v0, v2, v02926; GFX11-NEXT: s_setpc_b64 s[30:31]2927; EG-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:2928; EG: ; %bb.0:2929; EG-NEXT: CF_END2930; EG-NEXT: PAD2931 %div = fdiv nnan ninf float %x, %y, !fpmath !02932 ret float %div2933}2934 2935define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user(float %x, float %y, float %z) #0 {2936; GFX6-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:2937; GFX6: ; %bb.0:2938; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2939; GFX6-NEXT: s_mov_b32 s4, 0x7f8000002940; GFX6-NEXT: v_frexp_mant_f32_e32 v3, v12941; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s42942; GFX6-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc2943; GFX6-NEXT: v_rcp_f32_e32 v3, v32944; GFX6-NEXT: v_frexp_mant_f32_e32 v4, v02945; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s42946; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v12947; GFX6-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc2948; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v02949; GFX6-NEXT: v_mul_f32_e32 v3, v4, v32950; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v12951; GFX6-NEXT: v_ldexp_f32_e32 v0, v3, v02952; GFX6-NEXT: v_add_f32_e32 v0, v0, v22953; GFX6-NEXT: s_setpc_b64 s[30:31]2954;2955; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:2956; GFX7: ; %bb.0:2957; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2958; GFX7-NEXT: v_frexp_mant_f32_e32 v3, v12959; GFX7-NEXT: v_rcp_f32_e32 v3, v32960; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v12961; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v4, v02962; GFX7-NEXT: v_frexp_mant_f32_e32 v0, v02963; GFX7-NEXT: v_mul_f32_e32 v0, v0, v32964; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v4, v12965; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v12966; GFX7-NEXT: v_add_f32_e32 v0, v0, v22967; GFX7-NEXT: s_setpc_b64 s[30:31]2968;2969; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:2970; GFX8: ; %bb.0:2971; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2972; GFX8-NEXT: v_frexp_mant_f32_e32 v3, v12973; GFX8-NEXT: v_rcp_f32_e32 v3, v32974; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v12975; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v4, v02976; GFX8-NEXT: v_frexp_mant_f32_e32 v0, v02977; GFX8-NEXT: v_mul_f32_e32 v0, v0, v32978; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v4, v12979; GFX8-NEXT: v_ldexp_f32 v0, v0, v12980; GFX8-NEXT: v_add_f32_e32 v0, v0, v22981; GFX8-NEXT: s_setpc_b64 s[30:31]2982;2983; GFX6-IEEE-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:2984; GFX6-IEEE: ; %bb.0:2985; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2986; GFX6-IEEE-NEXT: v_mov_b32_e32 v4, 0x7f8000002987; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v12988; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v42989; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc2990; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v32991; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v5, v02992; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v42993; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v12994; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v4, v0, v5, vcc2995; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v02996; GFX6-IEEE-NEXT: v_mul_f32_e32 v3, v4, v32997; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v12998; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v3, v02999; GFX6-IEEE-NEXT: v_add_f32_e32 v0, v0, v23000; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]3001;3002; GFX6-FLUSH-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:3003; GFX6-FLUSH: ; %bb.0:3004; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3005; GFX6-FLUSH-NEXT: v_mov_b32_e32 v4, 0x7f8000003006; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v3, v13007; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v43008; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc3009; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v33010; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v5, v03011; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v43012; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v13013; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v4, v0, v5, vcc3014; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v03015; GFX6-FLUSH-NEXT: v_mul_f32_e32 v3, v4, v33016; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v13017; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v3, v03018; GFX6-FLUSH-NEXT: v_add_f32_e32 v0, v0, v23019; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]3020;3021; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:3022; GFX10: ; %bb.0:3023; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3024; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v13025; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v13026; GFX10-NEXT: v_frexp_mant_f32_e32 v4, v03027; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v03028; GFX10-NEXT: v_rcp_f32_e32 v3, v33029; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v13030; GFX10-NEXT: v_mul_f32_e32 v3, v4, v33031; GFX10-NEXT: v_ldexp_f32 v0, v3, v03032; GFX10-NEXT: v_add_f32_e32 v0, v0, v23033; GFX10-NEXT: s_setpc_b64 s[30:31]3034;3035; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:3036; GFX11: ; %bb.0:3037; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3038; GFX11-NEXT: v_frexp_mant_f32_e32 v3, v13039; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v13040; GFX11-NEXT: v_frexp_mant_f32_e32 v4, v03041; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v03042; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)3043; GFX11-NEXT: v_rcp_f32_e32 v3, v33044; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v13045; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3046; GFX11-NEXT: v_mul_f32_e32 v3, v4, v33047; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3048; GFX11-NEXT: v_ldexp_f32 v0, v3, v03049; GFX11-NEXT: v_add_f32_e32 v0, v0, v23050; GFX11-NEXT: s_setpc_b64 s[30:31]3051; EG-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:3052; EG: ; %bb.0:3053; EG-NEXT: CF_END3054; EG-NEXT: PAD3055 %div = fdiv nnan ninf contract float %x, %y, !fpmath !03056 %add = fadd contract float %div, %z3057 ret float %add3058}3059 3060 3061define float @v_fdiv_neglhs_f32_dynamic(float %x, float %y) #0 {3062; GFX6-FASTFMA-LABEL: v_fdiv_neglhs_f32_dynamic:3063; GFX6-FASTFMA: ; %bb.0:3064; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3065; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v03066; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v23067; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.03068; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v33069; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v03070; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v33071; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v43072; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v53073; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v43074; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v53075; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v03076; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]3077;3078; GFX6-SLOWFMA-LABEL: v_fdiv_neglhs_f32_dynamic:3079; GFX6-SLOWFMA: ; %bb.0:3080; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3081; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v03082; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v03083; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v23084; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.03085; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v43086; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v43087; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v33088; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v53089; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v33090; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v53091; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v03092; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]3093;3094; GFX7-LABEL: v_fdiv_neglhs_f32_dynamic:3095; GFX7: ; %bb.0:3096; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3097; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v03098; GFX7-NEXT: v_rcp_f32_e32 v3, v23099; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.03100; GFX7-NEXT: v_fma_f32 v3, v4, v3, v33101; GFX7-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v03102; GFX7-NEXT: v_mul_f32_e32 v5, v4, v33103; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v43104; GFX7-NEXT: v_fma_f32 v5, v6, v3, v53105; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v43106; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v53107; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, -v03108; GFX7-NEXT: s_setpc_b64 s[30:31]3109;3110; GFX8-LABEL: v_fdiv_neglhs_f32_dynamic:3111; GFX8: ; %bb.0:3112; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3113; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v03114; GFX8-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v03115; GFX8-NEXT: v_rcp_f32_e32 v4, v23116; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.03117; GFX8-NEXT: v_fma_f32 v4, v5, v4, v43118; GFX8-NEXT: v_mul_f32_e32 v5, v3, v43119; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v33120; GFX8-NEXT: v_fma_f32 v5, v6, v4, v53121; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v33122; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v53123; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, -v03124; GFX8-NEXT: s_setpc_b64 s[30:31]3125;3126; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_neglhs_f32_dynamic:3127; GFX6-IEEE-FASTFMA: ; %bb.0:3128; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3129; GFX6-IEEE-FASTFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v03130; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v23131; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v4, v33132; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v2, v1, v23133; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3134; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33135; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.03136; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v43137; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v43138; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v23139; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v53140; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v23141; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43142; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v53143; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v03144; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]3145;3146; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_neglhs_f32_dynamic:3147; GFX6-FLUSH-FASTFMA: ; %bb.0:3148; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3149; GFX6-FLUSH-FASTFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v03150; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v23151; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v4, v33152; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v2, v1, v23153; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3154; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33155; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.03156; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v43157; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v43158; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v23159; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v53160; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v23161; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43162; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v53163; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v03164; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]3165;3166; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_neglhs_f32_dynamic:3167; GFX6-IEEE-SLOWFMA: ; %bb.0:3168; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3169; GFX6-IEEE-SLOWFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v03170; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v23171; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v2, v1, v23172; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3173; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v33174; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33175; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.03176; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v43177; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v2, v43178; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v23179; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v53180; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, v23181; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43182; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v53183; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v03184; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]3185;3186; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_neglhs_f32_dynamic:3187; GFX6-FLUSH-SLOWFMA: ; %bb.0:3188; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3189; GFX6-FLUSH-SLOWFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v03190; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v23191; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v2, v1, v23192; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3193; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v33194; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33195; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.03196; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v43197; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v2, v43198; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v23199; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v53200; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, v23201; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43202; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v53203; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v03204; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]3205;3206; GFX89-IEEE-LABEL: v_fdiv_neglhs_f32_dynamic:3207; GFX89-IEEE: ; %bb.0:3208; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3209; GFX89-IEEE-NEXT: v_xor_b32_e32 v2, 0x80000000, v03210; GFX89-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v23211; GFX89-IEEE-NEXT: v_div_scale_f32 v2, vcc, v2, v1, v23212; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3213; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v33214; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33215; GFX89-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.03216; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v43217; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v2, v43218; GFX89-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v23219; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v53220; GFX89-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v23221; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43222; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v53223; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, -v03224; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]3225;3226; GFX89-FLUSH-LABEL: v_fdiv_neglhs_f32_dynamic:3227; GFX89-FLUSH: ; %bb.0:3228; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3229; GFX89-FLUSH-NEXT: v_xor_b32_e32 v2, 0x80000000, v03230; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v23231; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, vcc, v2, v1, v23232; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3233; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v33234; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33235; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.03236; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v43237; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v43238; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v23239; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v53240; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v23241; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43242; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v53243; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, -v03244; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]3245;3246; GFX10-IEEE-LABEL: v_fdiv_neglhs_f32_dynamic:3247; GFX10-IEEE: ; %bb.0:3248; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3249; GFX10-IEEE-NEXT: v_xor_b32_e32 v2, 0x80000000, v03250; GFX10-IEEE-NEXT: v_div_scale_f32 v3, s4, v1, v1, v23251; GFX10-IEEE-NEXT: v_div_scale_f32 v2, vcc_lo, v2, v1, v23252; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3253; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v33254; GFX10-IEEE-NEXT: s_denorm_mode 153255; GFX10-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.03256; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v43257; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v2, v43258; GFX10-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v23259; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v43260; GFX10-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v23261; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43262; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v53263; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, -v03264; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]3265;3266; GFX10-FLUSH-LABEL: v_fdiv_neglhs_f32_dynamic:3267; GFX10-FLUSH: ; %bb.0:3268; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3269; GFX10-FLUSH-NEXT: v_xor_b32_e32 v2, 0x80000000, v03270; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, s4, v1, v1, v23271; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v2, v1, v23272; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3273; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v4, v33274; GFX10-FLUSH-NEXT: s_denorm_mode 33275; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.03276; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v43277; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v43278; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v23279; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v43280; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v23281; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43282; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v53283; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, -v03284; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]3285;3286; GFX11-IEEE-LABEL: v_fdiv_neglhs_f32_dynamic:3287; GFX11-IEEE: ; %bb.0:3288; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3289; GFX11-IEEE-NEXT: v_xor_b32_e32 v2, 0x80000000, v03290; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)3291; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3292; GFX11-IEEE-NEXT: v_div_scale_f32 v3, null, v1, v1, v23293; GFX11-IEEE-NEXT: v_div_scale_f32 v2, vcc_lo, v2, v1, v23294; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v33295; GFX11-IEEE-NEXT: s_denorm_mode 153296; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3297; GFX11-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.03298; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3299; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v43300; GFX11-IEEE-NEXT: v_mul_f32_e32 v5, v2, v43301; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3302; GFX11-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v23303; GFX11-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v43304; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)3305; GFX11-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v23306; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s03307; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v53308; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)3309; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, -v03310; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]3311;3312; GFX11-FLUSH-LABEL: v_fdiv_neglhs_f32_dynamic:3313; GFX11-FLUSH: ; %bb.0:3314; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3315; GFX11-FLUSH-NEXT: v_xor_b32_e32 v2, 0x80000000, v03316; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)3317; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3318; GFX11-FLUSH-NEXT: v_div_scale_f32 v3, null, v1, v1, v23319; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v2, v1, v23320; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v4, v33321; GFX11-FLUSH-NEXT: s_denorm_mode 33322; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3323; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.03324; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3325; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v43326; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v43327; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3328; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v23329; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v43330; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)3331; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v23332; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s03333; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v53334; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1)3335; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, -v03336; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]3337; EG-LABEL: v_fdiv_neglhs_f32_dynamic:3338; EG: ; %bb.0:3339; EG-NEXT: CF_END3340; EG-NEXT: PAD3341 %neg.x = fneg float %x3342 %div = fdiv float %neg.x, %y3343 ret float %div3344}3345 3346define float @v_fdiv_neglhs_f32_dynamic_25ulp(float %x, float %y) #0 {3347; GFX6-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:3348; GFX6: ; %bb.0:3349; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3350; GFX6-NEXT: s_mov_b32 s4, 0x7f8000003351; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v13352; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s43353; GFX6-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc3354; GFX6-NEXT: v_rcp_f32_e32 v2, v23355; GFX6-NEXT: v_frexp_mant_f32_e64 v3, -v03356; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s43357; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v13358; GFX6-NEXT: v_cndmask_b32_e64 v3, -v0, v3, s[4:5]3359; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v03360; GFX6-NEXT: v_mul_f32_e32 v2, v3, v23361; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v13362; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v03363; GFX6-NEXT: s_setpc_b64 s[30:31]3364;3365; GFX7-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:3366; GFX7: ; %bb.0:3367; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3368; GFX7-NEXT: v_frexp_mant_f32_e32 v2, v13369; GFX7-NEXT: v_rcp_f32_e32 v2, v23370; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v13371; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v3, v03372; GFX7-NEXT: v_frexp_mant_f32_e64 v0, -v03373; GFX7-NEXT: v_mul_f32_e32 v0, v0, v23374; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v3, v13375; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v13376; GFX7-NEXT: s_setpc_b64 s[30:31]3377;3378; GFX8-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:3379; GFX8: ; %bb.0:3380; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3381; GFX8-NEXT: v_frexp_mant_f32_e32 v2, v13382; GFX8-NEXT: v_rcp_f32_e32 v2, v23383; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v13384; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v3, v03385; GFX8-NEXT: v_frexp_mant_f32_e64 v0, -v03386; GFX8-NEXT: v_mul_f32_e32 v0, v0, v23387; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v3, v13388; GFX8-NEXT: v_ldexp_f32 v0, v0, v13389; GFX8-NEXT: s_setpc_b64 s[30:31]3390;3391; GFX6-IEEE-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:3392; GFX6-IEEE: ; %bb.0:3393; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3394; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f8000003395; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v13396; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v33397; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc3398; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v23399; GFX6-IEEE-NEXT: v_frexp_mant_f32_e64 v4, -v03400; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v33401; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v13402; GFX6-IEEE-NEXT: v_cndmask_b32_e64 v3, -v0, v4, s[4:5]3403; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e64 v0, -v03404; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v23405; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v13406; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v03407; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]3408;3409; GFX6-FLUSH-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:3410; GFX6-FLUSH: ; %bb.0:3411; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3412; GFX6-FLUSH-NEXT: v_mov_b32_e32 v3, 0x7f8000003413; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v2, v13414; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v33415; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc3416; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v23417; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e64 v4, -v03418; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v33419; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v13420; GFX6-FLUSH-NEXT: v_cndmask_b32_e64 v3, -v0, v4, s[4:5]3421; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e64 v0, -v03422; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v23423; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v13424; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v2, v03425; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]3426;3427; GFX10-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:3428; GFX10: ; %bb.0:3429; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3430; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v13431; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v13432; GFX10-NEXT: v_frexp_mant_f32_e64 v3, -v03433; GFX10-NEXT: v_frexp_exp_i32_f32_e64 v0, -v03434; GFX10-NEXT: v_rcp_f32_e32 v2, v23435; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v13436; GFX10-NEXT: v_mul_f32_e32 v2, v3, v23437; GFX10-NEXT: v_ldexp_f32 v0, v2, v03438; GFX10-NEXT: s_setpc_b64 s[30:31]3439;3440; GFX11-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:3441; GFX11: ; %bb.0:3442; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3443; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v13444; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v13445; GFX11-NEXT: v_frexp_mant_f32_e64 v3, -v03446; GFX11-NEXT: v_frexp_exp_i32_f32_e64 v0, -v03447; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)3448; GFX11-NEXT: v_rcp_f32_e32 v2, v23449; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v13450; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3451; GFX11-NEXT: v_mul_f32_e32 v2, v3, v23452; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)3453; GFX11-NEXT: v_ldexp_f32 v0, v2, v03454; GFX11-NEXT: s_setpc_b64 s[30:31]3455; EG-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:3456; EG: ; %bb.0:3457; EG-NEXT: CF_END3458; EG-NEXT: PAD3459 %neg.x = fneg float %x3460 %div = fdiv float %neg.x, %y, !fpmath !03461 ret float %div3462}3463 3464 3465define float @v_fdiv_negrhs_f32_dynamic(float %x, float %y) #0 {3466; GFX6-FASTFMA-LABEL: v_fdiv_negrhs_f32_dynamic:3467; GFX6-FASTFMA: ; %bb.0:3468; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3469; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v03470; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v23471; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.03472; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v33473; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v03474; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v33475; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v43476; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v53477; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v43478; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v53479; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v03480; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]3481;3482; GFX6-SLOWFMA-LABEL: v_fdiv_negrhs_f32_dynamic:3483; GFX6-SLOWFMA: ; %bb.0:3484; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3485; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v03486; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v03487; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v23488; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.03489; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v43490; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v43491; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v33492; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v53493; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v33494; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v53495; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v03496; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]3497;3498; GFX7-LABEL: v_fdiv_negrhs_f32_dynamic:3499; GFX7: ; %bb.0:3500; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3501; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v03502; GFX7-NEXT: v_rcp_f32_e32 v3, v23503; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.03504; GFX7-NEXT: v_fma_f32 v3, v4, v3, v33505; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v03506; GFX7-NEXT: v_mul_f32_e32 v5, v4, v33507; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v43508; GFX7-NEXT: v_fma_f32 v5, v6, v3, v53509; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v43510; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v53511; GFX7-NEXT: v_div_fixup_f32 v0, v2, -v1, v03512; GFX7-NEXT: s_setpc_b64 s[30:31]3513;3514; GFX8-LABEL: v_fdiv_negrhs_f32_dynamic:3515; GFX8: ; %bb.0:3516; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3517; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v03518; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v03519; GFX8-NEXT: v_rcp_f32_e32 v4, v23520; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.03521; GFX8-NEXT: v_fma_f32 v4, v5, v4, v43522; GFX8-NEXT: v_mul_f32_e32 v5, v3, v43523; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v33524; GFX8-NEXT: v_fma_f32 v5, v6, v4, v53525; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v33526; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v53527; GFX8-NEXT: v_div_fixup_f32 v0, v2, -v1, v03528; GFX8-NEXT: s_setpc_b64 s[30:31]3529;3530; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_negrhs_f32_dynamic:3531; GFX6-IEEE-FASTFMA: ; %bb.0:3532; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3533; GFX6-IEEE-FASTFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v13534; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v03535; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v4, v33536; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v0, v2, v03537; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3538; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33539; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.03540; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v43541; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v43542; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v23543; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v53544; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v23545; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43546; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v53547; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v03548; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]3549;3550; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_negrhs_f32_dynamic:3551; GFX6-FLUSH-FASTFMA: ; %bb.0:3552; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3553; GFX6-FLUSH-FASTFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v13554; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v03555; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v4, v33556; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v0, v2, v03557; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3558; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33559; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.03560; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v43561; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v43562; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v23563; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v53564; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v23565; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43566; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v53567; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v03568; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]3569;3570; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_negrhs_f32_dynamic:3571; GFX6-IEEE-SLOWFMA: ; %bb.0:3572; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3573; GFX6-IEEE-SLOWFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v13574; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v03575; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v0, v2, v03576; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3577; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v33578; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33579; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.03580; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v43581; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v2, v43582; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v23583; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v53584; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, v23585; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43586; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v53587; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v03588; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]3589;3590; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_negrhs_f32_dynamic:3591; GFX6-FLUSH-SLOWFMA: ; %bb.0:3592; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3593; GFX6-FLUSH-SLOWFMA-NEXT: v_xor_b32_e32 v2, 0x80000000, v13594; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v03595; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v0, v2, v03596; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3597; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v33598; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33599; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.03600; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v43601; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v2, v43602; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v23603; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v53604; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, v23605; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43606; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v53607; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v03608; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]3609;3610; GFX89-IEEE-LABEL: v_fdiv_negrhs_f32_dynamic:3611; GFX89-IEEE: ; %bb.0:3612; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3613; GFX89-IEEE-NEXT: v_xor_b32_e32 v2, 0x80000000, v13614; GFX89-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v03615; GFX89-IEEE-NEXT: v_div_scale_f32 v2, vcc, v0, v2, v03616; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3617; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v33618; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33619; GFX89-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.03620; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v43621; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v2, v43622; GFX89-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v23623; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v53624; GFX89-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v23625; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43626; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v53627; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, -v1, v03628; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]3629;3630; GFX89-FLUSH-LABEL: v_fdiv_negrhs_f32_dynamic:3631; GFX89-FLUSH: ; %bb.0:3632; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3633; GFX89-FLUSH-NEXT: v_xor_b32_e32 v2, 0x80000000, v13634; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v03635; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, vcc, v0, v2, v03636; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3637; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v33638; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33639; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.03640; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v43641; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v43642; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v23643; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v53644; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v23645; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43646; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v53647; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, -v1, v03648; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]3649;3650; GFX10-IEEE-LABEL: v_fdiv_negrhs_f32_dynamic:3651; GFX10-IEEE: ; %bb.0:3652; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3653; GFX10-IEEE-NEXT: v_xor_b32_e32 v2, 0x80000000, v13654; GFX10-IEEE-NEXT: v_div_scale_f32 v3, s4, v2, v2, v03655; GFX10-IEEE-NEXT: v_div_scale_f32 v2, vcc_lo, v0, v2, v03656; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3657; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v33658; GFX10-IEEE-NEXT: s_denorm_mode 153659; GFX10-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.03660; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v43661; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v2, v43662; GFX10-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v23663; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v43664; GFX10-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v23665; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43666; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v53667; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, -v1, v03668; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]3669;3670; GFX10-FLUSH-LABEL: v_fdiv_negrhs_f32_dynamic:3671; GFX10-FLUSH: ; %bb.0:3672; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3673; GFX10-FLUSH-NEXT: v_xor_b32_e32 v2, 0x80000000, v13674; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, s4, v2, v2, v03675; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v0, v2, v03676; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3677; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v4, v33678; GFX10-FLUSH-NEXT: s_denorm_mode 33679; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.03680; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v43681; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v43682; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v23683; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v43684; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v23685; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43686; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v53687; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, -v1, v03688; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]3689;3690; GFX11-IEEE-LABEL: v_fdiv_negrhs_f32_dynamic:3691; GFX11-IEEE: ; %bb.0:3692; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3693; GFX11-IEEE-NEXT: v_xor_b32_e32 v2, 0x80000000, v13694; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)3695; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3696; GFX11-IEEE-NEXT: v_div_scale_f32 v3, null, v2, v2, v03697; GFX11-IEEE-NEXT: v_div_scale_f32 v2, vcc_lo, v0, v2, v03698; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v33699; GFX11-IEEE-NEXT: s_denorm_mode 153700; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3701; GFX11-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.03702; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3703; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v43704; GFX11-IEEE-NEXT: v_mul_f32_e32 v5, v2, v43705; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3706; GFX11-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v23707; GFX11-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v43708; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)3709; GFX11-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v23710; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s03711; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v53712; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)3713; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, -v1, v03714; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]3715;3716; GFX11-FLUSH-LABEL: v_fdiv_negrhs_f32_dynamic:3717; GFX11-FLUSH: ; %bb.0:3718; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3719; GFX11-FLUSH-NEXT: v_xor_b32_e32 v2, 0x80000000, v13720; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)3721; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3722; GFX11-FLUSH-NEXT: v_div_scale_f32 v3, null, v2, v2, v03723; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, vcc_lo, v0, v2, v03724; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v4, v33725; GFX11-FLUSH-NEXT: s_denorm_mode 33726; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3727; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.03728; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3729; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v43730; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v43731; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3732; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v23733; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v43734; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)3735; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v23736; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s03737; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v53738; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1)3739; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, -v1, v03740; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]3741; EG-LABEL: v_fdiv_negrhs_f32_dynamic:3742; EG: ; %bb.0:3743; EG-NEXT: CF_END3744; EG-NEXT: PAD3745 %neg.y = fneg float %y3746 %div = fdiv float %x, %neg.y3747 ret float %div3748}3749 3750 3751define float @v_fdiv_f32_constrhs0_dynamic(float %x) #0 {3752; GFX6-FASTFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:3753; GFX6-FASTFMA: ; %bb.0:3754; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3755; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e4003756; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v03757; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v13758; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v1, v2, 1.03759; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v3, v2, v23760; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v03761; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v23762; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v33763; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v43764; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v33765; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v43766; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v03767; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]3768;3769; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:3770; GFX6-SLOWFMA: ; %bb.0:3771; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3772; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e4003773; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v03774; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v03775; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v13776; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.03777; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v33778; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v33779; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v23780; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v43781; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v23782; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v43783; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v03784; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]3785;3786; GFX7-LABEL: v_fdiv_f32_constrhs0_dynamic:3787; GFX7: ; %bb.0:3788; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3789; GFX7-NEXT: s_mov_b32 s6, 0x4640e4003790; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v03791; GFX7-NEXT: v_rcp_f32_e32 v2, v13792; GFX7-NEXT: v_fma_f32 v3, -v1, v2, 1.03793; GFX7-NEXT: v_fma_f32 v2, v3, v2, v23794; GFX7-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v03795; GFX7-NEXT: v_mul_f32_e32 v4, v3, v23796; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v33797; GFX7-NEXT: v_fma_f32 v4, v5, v2, v43798; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v33799; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v43800; GFX7-NEXT: v_div_fixup_f32 v0, v1, s6, v03801; GFX7-NEXT: s_setpc_b64 s[30:31]3802;3803; GFX8-LABEL: v_fdiv_f32_constrhs0_dynamic:3804; GFX8: ; %bb.0:3805; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3806; GFX8-NEXT: s_mov_b32 s6, 0x4640e4003807; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v03808; GFX8-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v03809; GFX8-NEXT: v_rcp_f32_e32 v3, v13810; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.03811; GFX8-NEXT: v_fma_f32 v3, v4, v3, v33812; GFX8-NEXT: v_mul_f32_e32 v4, v2, v33813; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v23814; GFX8-NEXT: v_fma_f32 v4, v5, v3, v43815; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v23816; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v43817; GFX8-NEXT: v_div_fixup_f32 v0, v1, s6, v03818; GFX8-NEXT: s_setpc_b64 s[30:31]3819;3820; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:3821; GFX6-IEEE-FASTFMA: ; %bb.0:3822; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3823; GFX6-IEEE-FASTFMA-NEXT: v_mov_b32_e32 v1, 0x4640e4003824; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v03825; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v23826; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v03827; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3828; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33829; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.03830; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v33831; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v33832; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v43833; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v53834; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v43835; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43836; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v53837; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v03838; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]3839;3840; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:3841; GFX6-FLUSH-FASTFMA: ; %bb.0:3842; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3843; GFX6-FLUSH-FASTFMA-NEXT: v_mov_b32_e32 v1, 0x4640e4003844; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v03845; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v23846; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v03847; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3848; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33849; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.03850; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v33851; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v33852; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v43853; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v53854; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v43855; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43856; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v53857; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v03858; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]3859;3860; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:3861; GFX6-IEEE-SLOWFMA: ; %bb.0:3862; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3863; GFX6-IEEE-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0x4640e4003864; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v03865; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v03866; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3867; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v23868; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33869; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.03870; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v43871; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v43872; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v33873; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v53874; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v33875; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43876; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v53877; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v03878; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]3879;3880; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:3881; GFX6-FLUSH-SLOWFMA: ; %bb.0:3882; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3883; GFX6-FLUSH-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0x4640e4003884; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v03885; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v03886; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3887; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v23888; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33889; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.03890; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v43891; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v43892; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v33893; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v53894; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v33895; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43896; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v53897; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v03898; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]3899;3900; GFX89-IEEE-LABEL: v_fdiv_f32_constrhs0_dynamic:3901; GFX89-IEEE: ; %bb.0:3902; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3903; GFX89-IEEE-NEXT: v_mov_b32_e32 v1, 0x4640e4003904; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v03905; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v03906; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3907; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v23908; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33909; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.03910; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v43911; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v43912; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v33913; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v53914; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v33915; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43916; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v53917; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v03918; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]3919;3920; GFX89-FLUSH-LABEL: v_fdiv_f32_constrhs0_dynamic:3921; GFX89-FLUSH: ; %bb.0:3922; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3923; GFX89-FLUSH-NEXT: v_mov_b32_e32 v1, 0x4640e4003924; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v03925; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v03926; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3927; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v23928; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 33929; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.03930; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v43931; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v43932; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v33933; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v53934; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v33935; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43936; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v53937; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v03938; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]3939;3940; GFX10-IEEE-LABEL: v_fdiv_f32_constrhs0_dynamic:3941; GFX10-IEEE: ; %bb.0:3942; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3943; GFX10-IEEE-NEXT: v_div_scale_f32 v1, s4, 0x4640e400, 0x4640e400, v03944; GFX10-IEEE-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v03945; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3946; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v13947; GFX10-IEEE-NEXT: s_denorm_mode 153948; GFX10-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.03949; GFX10-IEEE-NEXT: v_fmac_f32_e32 v2, v4, v23950; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v3, v23951; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v33952; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v23953; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v33954; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43955; GFX10-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v43956; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v03957; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]3958;3959; GFX10-FLUSH-LABEL: v_fdiv_f32_constrhs0_dynamic:3960; GFX10-FLUSH: ; %bb.0:3961; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3962; GFX10-FLUSH-NEXT: v_div_scale_f32 v1, s4, 0x4640e400, 0x4640e400, v03963; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v03964; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)3965; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v13966; GFX10-FLUSH-NEXT: s_denorm_mode 33967; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.03968; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v23969; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v23970; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v33971; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v23972; GFX10-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v33973; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s43974; GFX10-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v43975; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v03976; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]3977;3978; GFX11-IEEE-LABEL: v_fdiv_f32_constrhs0_dynamic:3979; GFX11-IEEE: ; %bb.0:3980; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3981; GFX11-IEEE-NEXT: v_div_scale_f32 v1, null, 0x4640e400, 0x4640e400, v03982; GFX11-IEEE-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v03983; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)3984; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v13985; GFX11-IEEE-NEXT: s_denorm_mode 153986; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)3987; GFX11-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.03988; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3989; GFX11-IEEE-NEXT: v_fmac_f32_e32 v2, v4, v23990; GFX11-IEEE-NEXT: v_mul_f32_e32 v4, v3, v23991; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3992; GFX11-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v33993; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v23994; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)3995; GFX11-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v33996; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s03997; GFX11-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v43998; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)3999; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v04000; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]4001;4002; GFX11-FLUSH-LABEL: v_fdiv_f32_constrhs0_dynamic:4003; GFX11-FLUSH: ; %bb.0:4004; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4005; GFX11-FLUSH-NEXT: v_div_scale_f32 v1, null, 0x4640e400, 0x4640e400, v04006; GFX11-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v04007; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)4008; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v14009; GFX11-FLUSH-NEXT: s_denorm_mode 34010; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4011; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.04012; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4013; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v24014; GFX11-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v24015; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4016; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v34017; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v24018; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4019; GFX11-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v34020; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s04021; GFX11-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v44022; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1)4023; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v04024; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]4025; EG-LABEL: v_fdiv_f32_constrhs0_dynamic:4026; EG: ; %bb.0:4027; EG-NEXT: CF_END4028; EG-NEXT: PAD4029 %div = fdiv float %x, 12345.04030 ret float %div4031}4032 4033define float @v_fdiv_f32_constrhs0_dynamic_25ulp(float %x) #0 {4034; GFX6-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:4035; GFX6: ; %bb.0:4036; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4037; GFX6-NEXT: s_mov_b32 s4, 0x7f8000004038; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v04039; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s44040; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, 0x4640e4004041; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc4042; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v04043; GFX6-NEXT: v_mul_f32_e32 v2, 0x3fa9e0f0, v24044; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v14045; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v04046; GFX6-NEXT: s_setpc_b64 s[30:31]4047;4048; GFX7-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:4049; GFX7: ; %bb.0:4050; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4051; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v04052; GFX7-NEXT: v_frexp_mant_f32_e32 v0, v04053; GFX7-NEXT: v_mul_f32_e32 v0, 0x3fa9e0f0, v04054; GFX7-NEXT: v_add_i32_e32 v1, vcc, -14, v14055; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v14056; GFX7-NEXT: s_setpc_b64 s[30:31]4057;4058; GFX8-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:4059; GFX8: ; %bb.0:4060; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4061; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v04062; GFX8-NEXT: v_frexp_mant_f32_e32 v0, v04063; GFX8-NEXT: v_mul_f32_e32 v0, 0x3fa9e0f0, v04064; GFX8-NEXT: v_add_u32_e32 v1, vcc, -14, v14065; GFX8-NEXT: v_ldexp_f32 v0, v0, v14066; GFX8-NEXT: s_setpc_b64 s[30:31]4067;4068; GFX6-IEEE-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:4069; GFX6-IEEE: ; %bb.0:4070; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4071; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, 0x3f40e4004072; GFX6-IEEE-NEXT: v_mov_b32_e32 v4, 0x7f8000004073; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v3, v04074; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v44075; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, 0x4640e4004076; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc4077; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v04078; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v24079; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v14080; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v04081; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]4082;4083; GFX6-FLUSH-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:4084; GFX6-FLUSH: ; %bb.0:4085; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4086; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, 0x3f40e4004087; GFX6-FLUSH-NEXT: v_mov_b32_e32 v4, 0x7f8000004088; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v3, v04089; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v44090; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, 0x4640e4004091; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc4092; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v04093; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v24094; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v14095; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v2, v04096; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]4097;4098; GFX10-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:4099; GFX10: ; %bb.0:4100; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4101; GFX10-NEXT: v_rcp_f32_e32 v1, 0x3f40e4004102; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v04103; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v04104; GFX10-NEXT: v_add_nc_u32_e32 v0, -14, v04105; GFX10-NEXT: v_mul_f32_e32 v1, v2, v14106; GFX10-NEXT: v_ldexp_f32 v0, v1, v04107; GFX10-NEXT: s_setpc_b64 s[30:31]4108;4109; GFX11-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:4110; GFX11: ; %bb.0:4111; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4112; GFX11-NEXT: v_rcp_f32_e32 v1, 0x3f40e4004113; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v04114; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v04115; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4116; GFX11-NEXT: v_dual_mul_f32 v1, v2, v1 :: v_dual_add_nc_u32 v0, -14, v04117; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)4118; GFX11-NEXT: v_ldexp_f32 v0, v1, v04119; GFX11-NEXT: s_setpc_b64 s[30:31]4120; EG-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:4121; EG: ; %bb.0:4122; EG-NEXT: CF_END4123; EG-NEXT: PAD4124 %div = fdiv float %x, 12345.0, !fpmath !04125 ret float %div4126}4127 4128 4129define float @v_fdiv_f32_constlhs0_dynamic(float %x) #0 {4130; GFX6-FASTFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:4131; GFX6-FASTFMA: ; %bb.0:4132; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4133; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e4004134; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s64135; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v14136; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v1, v2, 1.04137; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v3, v2, v24138; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s64139; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v24140; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v34141; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v44142; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v34143; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v44144; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s64145; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]4146;4147; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:4148; GFX6-SLOWFMA: ; %bb.0:4149; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4150; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e4004151; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s64152; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s64153; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v14154; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.04155; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v34156; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v34157; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v24158; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v44159; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v24160; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v44161; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s64162; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]4163;4164; GFX7-LABEL: v_fdiv_f32_constlhs0_dynamic:4165; GFX7: ; %bb.0:4166; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4167; GFX7-NEXT: s_mov_b32 s6, 0x4640e4004168; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s64169; GFX7-NEXT: v_rcp_f32_e32 v2, v14170; GFX7-NEXT: v_fma_f32 v3, -v1, v2, 1.04171; GFX7-NEXT: v_fma_f32 v2, v3, v2, v24172; GFX7-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s64173; GFX7-NEXT: v_mul_f32_e32 v4, v3, v24174; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v34175; GFX7-NEXT: v_fma_f32 v4, v5, v2, v44176; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v34177; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v44178; GFX7-NEXT: v_div_fixup_f32 v0, v1, v0, s64179; GFX7-NEXT: s_setpc_b64 s[30:31]4180;4181; GFX8-LABEL: v_fdiv_f32_constlhs0_dynamic:4182; GFX8: ; %bb.0:4183; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4184; GFX8-NEXT: s_mov_b32 s6, 0x4640e4004185; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s64186; GFX8-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s64187; GFX8-NEXT: v_rcp_f32_e32 v3, v14188; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.04189; GFX8-NEXT: v_fma_f32 v3, v4, v3, v34190; GFX8-NEXT: v_mul_f32_e32 v4, v2, v34191; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v24192; GFX8-NEXT: v_fma_f32 v4, v5, v3, v44193; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v24194; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v44195; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, s64196; GFX8-NEXT: s_setpc_b64 s[30:31]4197;4198; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:4199; GFX6-IEEE-FASTFMA: ; %bb.0:4200; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4201; GFX6-IEEE-FASTFMA-NEXT: v_mov_b32_e32 v1, 0x4640e4004202; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v14203; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v24204; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v14205; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4206; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34207; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.04208; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v34209; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v34210; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v44211; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v54212; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v44213; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44214; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v54215; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, v14216; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]4217;4218; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:4219; GFX6-FLUSH-FASTFMA: ; %bb.0:4220; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4221; GFX6-FLUSH-FASTFMA-NEXT: v_mov_b32_e32 v1, 0x4640e4004222; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v14223; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v24224; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v1, v0, v14225; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4226; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34227; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.04228; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v34229; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v34230; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v44231; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v54232; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v44233; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44234; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v54235; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, v14236; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]4237;4238; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:4239; GFX6-IEEE-SLOWFMA: ; %bb.0:4240; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4241; GFX6-IEEE-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0x4640e4004242; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v14243; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v1, v0, v14244; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4245; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v24246; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34247; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.04248; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v44249; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v44250; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v34251; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v54252; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v34253; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44254; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v54255; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, v14256; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]4257;4258; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:4259; GFX6-FLUSH-SLOWFMA: ; %bb.0:4260; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4261; GFX6-FLUSH-SLOWFMA-NEXT: v_mov_b32_e32 v1, 0x4640e4004262; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v14263; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v1, v0, v14264; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4265; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v24266; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34267; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.04268; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v44269; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v44270; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v34271; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v54272; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v34273; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44274; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v54275; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, v14276; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]4277;4278; GFX89-IEEE-LABEL: v_fdiv_f32_constlhs0_dynamic:4279; GFX89-IEEE: ; %bb.0:4280; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4281; GFX89-IEEE-NEXT: v_mov_b32_e32 v1, 0x4640e4004282; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v14283; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v1, v0, v14284; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4285; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v24286; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34287; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.04288; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v44289; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v44290; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v34291; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v54292; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v34293; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44294; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v54295; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, v14296; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]4297;4298; GFX89-FLUSH-LABEL: v_fdiv_f32_constlhs0_dynamic:4299; GFX89-FLUSH: ; %bb.0:4300; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4301; GFX89-FLUSH-NEXT: v_mov_b32_e32 v1, 0x4640e4004302; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, v14303; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v1, v0, v14304; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4305; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v24306; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34307; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.04308; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v44309; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v44310; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v34311; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v54312; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v34313; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44314; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v54315; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, v14316; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]4317;4318; GFX10-IEEE-LABEL: v_fdiv_f32_constlhs0_dynamic:4319; GFX10-IEEE: ; %bb.0:4320; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4321; GFX10-IEEE-NEXT: v_div_scale_f32 v1, s4, v0, v0, 0x4640e4004322; GFX10-IEEE-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e4004323; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4324; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v14325; GFX10-IEEE-NEXT: s_denorm_mode 154326; GFX10-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.04327; GFX10-IEEE-NEXT: v_fmac_f32_e32 v2, v4, v24328; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v3, v24329; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v34330; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v24331; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v34332; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44333; GFX10-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v44334; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e4004335; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]4336;4337; GFX10-FLUSH-LABEL: v_fdiv_f32_constlhs0_dynamic:4338; GFX10-FLUSH: ; %bb.0:4339; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4340; GFX10-FLUSH-NEXT: v_div_scale_f32 v1, s4, v0, v0, 0x4640e4004341; GFX10-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e4004342; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4343; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v14344; GFX10-FLUSH-NEXT: s_denorm_mode 34345; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.04346; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v24347; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v24348; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v34349; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v24350; GFX10-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v34351; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44352; GFX10-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v44353; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e4004354; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]4355;4356; GFX11-IEEE-LABEL: v_fdiv_f32_constlhs0_dynamic:4357; GFX11-IEEE: ; %bb.0:4358; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4359; GFX11-IEEE-NEXT: v_div_scale_f32 v1, null, v0, v0, 0x4640e4004360; GFX11-IEEE-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e4004361; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)4362; GFX11-IEEE-NEXT: v_rcp_f32_e32 v2, v14363; GFX11-IEEE-NEXT: s_denorm_mode 154364; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4365; GFX11-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.04366; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4367; GFX11-IEEE-NEXT: v_fmac_f32_e32 v2, v4, v24368; GFX11-IEEE-NEXT: v_mul_f32_e32 v4, v3, v24369; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4370; GFX11-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v34371; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v5, v24372; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4373; GFX11-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v34374; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s04375; GFX11-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v44376; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)4377; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e4004378; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]4379;4380; GFX11-FLUSH-LABEL: v_fdiv_f32_constlhs0_dynamic:4381; GFX11-FLUSH: ; %bb.0:4382; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4383; GFX11-FLUSH-NEXT: v_div_scale_f32 v1, null, v0, v0, 0x4640e4004384; GFX11-FLUSH-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e4004385; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)4386; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v2, v14387; GFX11-FLUSH-NEXT: s_denorm_mode 34388; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4389; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.04390; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4391; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v24392; GFX11-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v24393; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4394; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v34395; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v24396; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4397; GFX11-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v34398; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s04399; GFX11-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v44400; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1)4401; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e4004402; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]4403; EG-LABEL: v_fdiv_f32_constlhs0_dynamic:4404; EG: ; %bb.0:4405; EG-NEXT: CF_END4406; EG-NEXT: PAD4407 %div = fdiv float 12345.0, %x4408 ret float %div4409}4410 4411define float @v_fdiv_f32_constlhs0_dynamic_25ulp(float %x) #0 {4412; GFX6-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:4413; GFX6: ; %bb.0:4414; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4415; GFX6-NEXT: s_mov_b32 s4, 0x7f8000004416; GFX6-NEXT: v_frexp_mant_f32_e32 v1, v04417; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s44418; GFX6-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc4419; GFX6-NEXT: v_rcp_f32_e32 v1, v14420; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v04421; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v2, 0x4640e4004422; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v2, v04423; GFX6-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v14424; GFX6-NEXT: v_ldexp_f32_e32 v0, v1, v04425; GFX6-NEXT: s_setpc_b64 s[30:31]4426;4427; GFX7-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:4428; GFX7: ; %bb.0:4429; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4430; GFX7-NEXT: v_frexp_mant_f32_e32 v1, v04431; GFX7-NEXT: v_rcp_f32_e32 v1, v14432; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v0, v04433; GFX7-NEXT: v_sub_i32_e32 v0, vcc, 14, v04434; GFX7-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v14435; GFX7-NEXT: v_ldexp_f32_e32 v0, v1, v04436; GFX7-NEXT: s_setpc_b64 s[30:31]4437;4438; GFX8-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:4439; GFX8: ; %bb.0:4440; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4441; GFX8-NEXT: v_frexp_mant_f32_e32 v1, v04442; GFX8-NEXT: v_rcp_f32_e32 v1, v14443; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v0, v04444; GFX8-NEXT: v_sub_u32_e32 v0, vcc, 14, v04445; GFX8-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v14446; GFX8-NEXT: v_ldexp_f32 v0, v1, v04447; GFX8-NEXT: s_setpc_b64 s[30:31]4448;4449; GFX6-IEEE-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:4450; GFX6-IEEE: ; %bb.0:4451; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4452; GFX6-IEEE-NEXT: v_mov_b32_e32 v2, 0x7f8000004453; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v1, v04454; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v24455; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc4456; GFX6-IEEE-NEXT: v_rcp_f32_e32 v1, v14457; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v04458; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v2, 0x4640e4004459; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v2, v04460; GFX6-IEEE-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v14461; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v1, v04462; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]4463;4464; GFX6-FLUSH-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:4465; GFX6-FLUSH: ; %bb.0:4466; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4467; GFX6-FLUSH-NEXT: v_mov_b32_e32 v2, 0x7f8000004468; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v1, v04469; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v24470; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc4471; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v1, v14472; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v04473; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v2, 0x4640e4004474; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v2, v04475; GFX6-FLUSH-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v14476; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v1, v04477; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]4478;4479; GFX10-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:4480; GFX10: ; %bb.0:4481; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4482; GFX10-NEXT: v_frexp_mant_f32_e32 v1, v04483; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v04484; GFX10-NEXT: v_rcp_f32_e32 v1, v14485; GFX10-NEXT: v_sub_nc_u32_e32 v0, 14, v04486; GFX10-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v14487; GFX10-NEXT: v_ldexp_f32 v0, v1, v04488; GFX10-NEXT: s_setpc_b64 s[30:31]4489;4490; GFX11-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:4491; GFX11: ; %bb.0:4492; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4493; GFX11-NEXT: v_frexp_mant_f32_e32 v1, v04494; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v04495; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)4496; GFX11-NEXT: v_rcp_f32_e32 v1, v14497; GFX11-NEXT: v_sub_nc_u32_e32 v0, 14, v04498; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4499; GFX11-NEXT: v_mul_f32_e32 v1, 0x3f40e400, v14500; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)4501; GFX11-NEXT: v_ldexp_f32 v0, v1, v04502; GFX11-NEXT: s_setpc_b64 s[30:31]4503; EG-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:4504; EG: ; %bb.0:4505; EG-NEXT: CF_END4506; EG-NEXT: PAD4507 %div = fdiv float 12345.0, %x, !fpmath !04508 ret float %div4509}4510 4511 4512define float @v_fdiv_f32_dynamic_nodenorm_x(float nofpclass(sub) %x, float %y) #0 {4513; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4514; GFX6-FASTFMA: ; %bb.0:4515; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4516; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04517; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v24518; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.04519; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v34520; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v04521; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v34522; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v44523; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v54524; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v44525; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v54526; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v04527; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]4528;4529; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4530; GFX6-SLOWFMA: ; %bb.0:4531; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4532; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04533; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v04534; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v24535; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.04536; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v44537; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v44538; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v34539; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v54540; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v34541; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v54542; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v04543; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]4544;4545; GFX7-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4546; GFX7: ; %bb.0:4547; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4548; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04549; GFX7-NEXT: v_rcp_f32_e32 v3, v24550; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.04551; GFX7-NEXT: v_fma_f32 v3, v4, v3, v34552; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v04553; GFX7-NEXT: v_mul_f32_e32 v5, v4, v34554; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v44555; GFX7-NEXT: v_fma_f32 v5, v6, v3, v54556; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v44557; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v54558; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v04559; GFX7-NEXT: s_setpc_b64 s[30:31]4560;4561; GFX8-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4562; GFX8: ; %bb.0:4563; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4564; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04565; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v04566; GFX8-NEXT: v_rcp_f32_e32 v4, v24567; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.04568; GFX8-NEXT: v_fma_f32 v4, v5, v4, v44569; GFX8-NEXT: v_mul_f32_e32 v5, v3, v44570; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v34571; GFX8-NEXT: v_fma_f32 v5, v6, v4, v54572; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v34573; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v54574; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v04575; GFX8-NEXT: s_setpc_b64 s[30:31]4576;4577; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4578; GFX6-IEEE-FASTFMA: ; %bb.0:4579; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4580; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04581; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v24582; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v04583; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4584; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34585; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.04586; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v34587; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v34588; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v44589; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v54590; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v44591; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44592; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v54593; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v04594; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]4595;4596; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4597; GFX6-FLUSH-FASTFMA: ; %bb.0:4598; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4599; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04600; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v24601; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v04602; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4603; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34604; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.04605; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v34606; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v34607; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v44608; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v54609; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v44610; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44611; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v54612; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v04613; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]4614;4615; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4616; GFX6-IEEE-SLOWFMA: ; %bb.0:4617; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4618; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04619; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v04620; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4621; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v24622; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34623; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.04624; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v44625; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v44626; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v34627; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v54628; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v34629; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44630; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v54631; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v04632; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]4633;4634; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4635; GFX6-FLUSH-SLOWFMA: ; %bb.0:4636; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4637; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04638; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v04639; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4640; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v24641; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34642; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.04643; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v44644; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v44645; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v34646; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v54647; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v34648; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44649; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v54650; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v04651; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]4652;4653; GFX89-IEEE-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4654; GFX89-IEEE: ; %bb.0:4655; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4656; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04657; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v04658; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4659; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v24660; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34661; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.04662; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v44663; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v44664; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v34665; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v54666; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v34667; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44668; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v54669; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v04670; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]4671;4672; GFX89-FLUSH-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4673; GFX89-FLUSH: ; %bb.0:4674; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4675; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04676; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v04677; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4678; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v24679; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34680; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.04681; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v44682; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v44683; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v34684; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v54685; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v34686; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44687; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v54688; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v04689; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]4690;4691; GFX10-IEEE-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4692; GFX10-IEEE: ; %bb.0:4693; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4694; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v04695; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v04696; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4697; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v24698; GFX10-IEEE-NEXT: s_denorm_mode 154699; GFX10-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.04700; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v34701; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v34702; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v44703; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v34704; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v44705; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44706; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v54707; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v04708; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]4709;4710; GFX10-FLUSH-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4711; GFX10-FLUSH: ; %bb.0:4712; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4713; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v1, v1, v04714; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v04715; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4716; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v24717; GFX10-FLUSH-NEXT: s_denorm_mode 34718; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.04719; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v34720; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v34721; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v44722; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v34723; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v44724; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44725; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v54726; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v04727; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]4728;4729; GFX11-IEEE-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4730; GFX11-IEEE: ; %bb.0:4731; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4732; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v1, v1, v04733; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v04734; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)4735; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v24736; GFX11-IEEE-NEXT: s_denorm_mode 154737; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4738; GFX11-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.04739; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4740; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v34741; GFX11-IEEE-NEXT: v_mul_f32_e32 v5, v4, v34742; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4743; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v44744; GFX11-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v34745; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4746; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v44747; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s04748; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v54749; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)4750; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v04751; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]4752;4753; GFX11-FLUSH-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4754; GFX11-FLUSH: ; %bb.0:4755; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4756; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v1, v1, v04757; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v04758; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)4759; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v24760; GFX11-FLUSH-NEXT: s_denorm_mode 34761; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4762; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.04763; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4764; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v34765; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v34766; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4767; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v44768; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v34769; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4770; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v44771; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s04772; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v54773; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1)4774; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v04775; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]4776; EG-LABEL: v_fdiv_f32_dynamic_nodenorm_x:4777; EG: ; %bb.0:4778; EG-NEXT: CF_END4779; EG-NEXT: PAD4780 %div = fdiv float %x, %y4781 ret float %div4782}4783 4784define float @v_fdiv_f32_dynamic_25ulp_nodenorm_x(float nofpclass(sub) %x, float %y) #0 {4785; GFX6-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:4786; GFX6: ; %bb.0:4787; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4788; GFX6-NEXT: s_mov_b32 s4, 0x7f8000004789; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v14790; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s44791; GFX6-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc4792; GFX6-NEXT: v_rcp_f32_e32 v2, v24793; GFX6-NEXT: v_frexp_mant_f32_e32 v3, v04794; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s44795; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v14796; GFX6-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc4797; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v04798; GFX6-NEXT: v_mul_f32_e32 v2, v3, v24799; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v14800; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v04801; GFX6-NEXT: s_setpc_b64 s[30:31]4802;4803; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:4804; GFX7: ; %bb.0:4805; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4806; GFX7-NEXT: v_frexp_mant_f32_e32 v2, v14807; GFX7-NEXT: v_rcp_f32_e32 v2, v24808; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v14809; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v3, v04810; GFX7-NEXT: v_frexp_mant_f32_e32 v0, v04811; GFX7-NEXT: v_mul_f32_e32 v0, v0, v24812; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v3, v14813; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v14814; GFX7-NEXT: s_setpc_b64 s[30:31]4815;4816; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:4817; GFX8: ; %bb.0:4818; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4819; GFX8-NEXT: v_frexp_mant_f32_e32 v2, v14820; GFX8-NEXT: v_rcp_f32_e32 v2, v24821; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v14822; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v3, v04823; GFX8-NEXT: v_frexp_mant_f32_e32 v0, v04824; GFX8-NEXT: v_mul_f32_e32 v0, v0, v24825; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v3, v14826; GFX8-NEXT: v_ldexp_f32 v0, v0, v14827; GFX8-NEXT: s_setpc_b64 s[30:31]4828;4829; GFX6-IEEE-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:4830; GFX6-IEEE: ; %bb.0:4831; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4832; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f8000004833; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v14834; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v34835; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc4836; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v24837; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v04838; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v34839; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v14840; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc4841; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v04842; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v24843; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v14844; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v04845; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]4846;4847; GFX6-FLUSH-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:4848; GFX6-FLUSH: ; %bb.0:4849; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4850; GFX6-FLUSH-NEXT: v_mov_b32_e32 v3, 0x7f8000004851; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v2, v14852; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v34853; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc4854; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v24855; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v4, v04856; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v34857; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v14858; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc4859; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v04860; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v24861; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v14862; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v2, v04863; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]4864;4865; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:4866; GFX10: ; %bb.0:4867; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4868; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v14869; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v14870; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v04871; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v04872; GFX10-NEXT: v_rcp_f32_e32 v2, v24873; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v14874; GFX10-NEXT: v_mul_f32_e32 v2, v3, v24875; GFX10-NEXT: v_ldexp_f32 v0, v2, v04876; GFX10-NEXT: s_setpc_b64 s[30:31]4877;4878; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:4879; GFX11: ; %bb.0:4880; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4881; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v14882; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v14883; GFX11-NEXT: v_frexp_mant_f32_e32 v3, v04884; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v04885; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)4886; GFX11-NEXT: v_rcp_f32_e32 v2, v24887; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v14888; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)4889; GFX11-NEXT: v_mul_f32_e32 v2, v3, v24890; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)4891; GFX11-NEXT: v_ldexp_f32 v0, v2, v04892; GFX11-NEXT: s_setpc_b64 s[30:31]4893; EG-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:4894; EG: ; %bb.0:4895; EG-NEXT: CF_END4896; EG-NEXT: PAD4897 %div = fdiv float %x, %y, !fpmath !04898 ret float %div4899}4900 4901define float @v_fdiv_f32_dynamic_nodenorm_y(float %x, float nofpclass(sub) %y) #0 {4902; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:4903; GFX6-FASTFMA: ; %bb.0:4904; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4905; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04906; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v24907; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.04908; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v34909; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v04910; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v34911; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v44912; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v54913; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v44914; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v54915; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v04916; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]4917;4918; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:4919; GFX6-SLOWFMA: ; %bb.0:4920; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4921; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04922; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v04923; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v24924; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.04925; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v44926; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v44927; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v34928; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v54929; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v34930; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v54931; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v04932; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]4933;4934; GFX7-LABEL: v_fdiv_f32_dynamic_nodenorm_y:4935; GFX7: ; %bb.0:4936; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4937; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04938; GFX7-NEXT: v_rcp_f32_e32 v3, v24939; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.04940; GFX7-NEXT: v_fma_f32 v3, v4, v3, v34941; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v04942; GFX7-NEXT: v_mul_f32_e32 v5, v4, v34943; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v44944; GFX7-NEXT: v_fma_f32 v5, v6, v3, v54945; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v44946; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v54947; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v04948; GFX7-NEXT: s_setpc_b64 s[30:31]4949;4950; GFX8-LABEL: v_fdiv_f32_dynamic_nodenorm_y:4951; GFX8: ; %bb.0:4952; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4953; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04954; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v04955; GFX8-NEXT: v_rcp_f32_e32 v4, v24956; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.04957; GFX8-NEXT: v_fma_f32 v4, v5, v4, v44958; GFX8-NEXT: v_mul_f32_e32 v5, v3, v44959; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v34960; GFX8-NEXT: v_fma_f32 v5, v6, v4, v54961; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v34962; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v54963; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v04964; GFX8-NEXT: s_setpc_b64 s[30:31]4965;4966; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:4967; GFX6-IEEE-FASTFMA: ; %bb.0:4968; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4969; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04970; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v24971; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v04972; GFX6-IEEE-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4973; GFX6-IEEE-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34974; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.04975; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v34976; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v34977; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v44978; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v54979; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v44980; GFX6-IEEE-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s44981; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v54982; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v04983; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]4984;4985; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:4986; GFX6-FLUSH-FASTFMA: ; %bb.0:4987; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4988; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v04989; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v24990; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v04991; GFX6-FLUSH-FASTFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)4992; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 34993; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.04994; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v34995; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v34996; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v44997; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v54998; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v44999; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s45000; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v55001; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v05002; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]5003;5004; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:5005; GFX6-IEEE-SLOWFMA: ; %bb.0:5006; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5007; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v05008; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v05009; GFX6-IEEE-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)5010; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v25011; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 35012; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.05013; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v45014; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v45015; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v35016; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v55017; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v35018; GFX6-IEEE-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s45019; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v55020; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v05021; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]5022;5023; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:5024; GFX6-FLUSH-SLOWFMA: ; %bb.0:5025; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5026; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v05027; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v05028; GFX6-FLUSH-SLOWFMA-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)5029; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v25030; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 35031; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.05032; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v45033; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v45034; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v35035; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v55036; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v35037; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s45038; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v55039; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v05040; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]5041;5042; GFX89-IEEE-LABEL: v_fdiv_f32_dynamic_nodenorm_y:5043; GFX89-IEEE: ; %bb.0:5044; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5045; GFX89-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v05046; GFX89-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v05047; GFX89-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)5048; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v25049; GFX89-IEEE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 35050; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.05051; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v45052; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v45053; GFX89-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v35054; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v55055; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v35056; GFX89-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s45057; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v55058; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v05059; GFX89-IEEE-NEXT: s_setpc_b64 s[30:31]5060;5061; GFX89-FLUSH-LABEL: v_fdiv_f32_dynamic_nodenorm_y:5062; GFX89-FLUSH: ; %bb.0:5063; GFX89-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5064; GFX89-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v05065; GFX89-FLUSH-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v05066; GFX89-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)5067; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v25068; GFX89-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 35069; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.05070; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v45071; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v45072; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v35073; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v55074; GFX89-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v35075; GFX89-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s45076; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v55077; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v05078; GFX89-FLUSH-NEXT: s_setpc_b64 s[30:31]5079;5080; GFX10-IEEE-LABEL: v_fdiv_f32_dynamic_nodenorm_y:5081; GFX10-IEEE: ; %bb.0:5082; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5083; GFX10-IEEE-NEXT: v_div_scale_f32 v2, s4, v1, v1, v05084; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v05085; GFX10-IEEE-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)5086; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v25087; GFX10-IEEE-NEXT: s_denorm_mode 155088; GFX10-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.05089; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v35090; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v35091; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v45092; GFX10-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v35093; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v45094; GFX10-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s45095; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v55096; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v05097; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31]5098;5099; GFX10-FLUSH-LABEL: v_fdiv_f32_dynamic_nodenorm_y:5100; GFX10-FLUSH: ; %bb.0:5101; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5102; GFX10-FLUSH-NEXT: v_div_scale_f32 v2, s4, v1, v1, v05103; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v05104; GFX10-FLUSH-NEXT: s_getreg_b32 s4, hwreg(HW_REG_MODE, 4, 2)5105; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v25106; GFX10-FLUSH-NEXT: s_denorm_mode 35107; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.05108; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v35109; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v35110; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v45111; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v35112; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v45113; GFX10-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s45114; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v55115; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v05116; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31]5117;5118; GFX11-IEEE-LABEL: v_fdiv_f32_dynamic_nodenorm_y:5119; GFX11-IEEE: ; %bb.0:5120; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5121; GFX11-IEEE-NEXT: v_div_scale_f32 v2, null, v1, v1, v05122; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v05123; GFX11-IEEE-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)5124; GFX11-IEEE-NEXT: v_rcp_f32_e32 v3, v25125; GFX11-IEEE-NEXT: s_denorm_mode 155126; GFX11-IEEE-NEXT: s_waitcnt_depctr depctr_va_vdst(0)5127; GFX11-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.05128; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)5129; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v5, v35130; GFX11-IEEE-NEXT: v_mul_f32_e32 v5, v4, v35131; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)5132; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v45133; GFX11-IEEE-NEXT: v_fmac_f32_e32 v5, v6, v35134; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)5135; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v45136; GFX11-IEEE-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s05137; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v55138; GFX11-IEEE-NEXT: s_delay_alu instid0(VALU_DEP_1)5139; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v05140; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31]5141;5142; GFX11-FLUSH-LABEL: v_fdiv_f32_dynamic_nodenorm_y:5143; GFX11-FLUSH: ; %bb.0:5144; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5145; GFX11-FLUSH-NEXT: v_div_scale_f32 v2, null, v1, v1, v05146; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v05147; GFX11-FLUSH-NEXT: s_getreg_b32 s0, hwreg(HW_REG_MODE, 4, 2)5148; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v25149; GFX11-FLUSH-NEXT: s_denorm_mode 35150; GFX11-FLUSH-NEXT: s_waitcnt_depctr depctr_va_vdst(0)5151; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.05152; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)5153; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v3, v5, v35154; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v35155; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)5156; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v45157; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v6, v35158; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)5159; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v45160; GFX11-FLUSH-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s05161; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v55162; GFX11-FLUSH-NEXT: s_delay_alu instid0(VALU_DEP_1)5163; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v05164; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31]5165; EG-LABEL: v_fdiv_f32_dynamic_nodenorm_y:5166; EG: ; %bb.0:5167; EG-NEXT: CF_END5168; EG-NEXT: PAD5169 %div = fdiv float %x, %y5170 ret float %div5171}5172 5173define float @v_fdiv_f32_dynamic_25ulp_nodenorm_y(float %x, float nofpclass(sub) %y) #0 {5174; GFX6-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:5175; GFX6: ; %bb.0:5176; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5177; GFX6-NEXT: s_mov_b32 s4, 0x7f8000005178; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v15179; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s45180; GFX6-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc5181; GFX6-NEXT: v_rcp_f32_e32 v2, v25182; GFX6-NEXT: v_frexp_mant_f32_e32 v3, v05183; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s45184; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v15185; GFX6-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc5186; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v05187; GFX6-NEXT: v_mul_f32_e32 v2, v3, v25188; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v15189; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v05190; GFX6-NEXT: s_setpc_b64 s[30:31]5191;5192; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:5193; GFX7: ; %bb.0:5194; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5195; GFX7-NEXT: v_frexp_mant_f32_e32 v2, v15196; GFX7-NEXT: v_rcp_f32_e32 v2, v25197; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v1, v15198; GFX7-NEXT: v_frexp_exp_i32_f32_e32 v3, v05199; GFX7-NEXT: v_frexp_mant_f32_e32 v0, v05200; GFX7-NEXT: v_mul_f32_e32 v0, v0, v25201; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v3, v15202; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v15203; GFX7-NEXT: s_setpc_b64 s[30:31]5204;5205; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:5206; GFX8: ; %bb.0:5207; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5208; GFX8-NEXT: v_frexp_mant_f32_e32 v2, v15209; GFX8-NEXT: v_rcp_f32_e32 v2, v25210; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v1, v15211; GFX8-NEXT: v_frexp_exp_i32_f32_e32 v3, v05212; GFX8-NEXT: v_frexp_mant_f32_e32 v0, v05213; GFX8-NEXT: v_mul_f32_e32 v0, v0, v25214; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v3, v15215; GFX8-NEXT: v_ldexp_f32 v0, v0, v15216; GFX8-NEXT: s_setpc_b64 s[30:31]5217;5218; GFX6-IEEE-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:5219; GFX6-IEEE: ; %bb.0:5220; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5221; GFX6-IEEE-NEXT: v_mov_b32_e32 v3, 0x7f8000005222; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v2, v15223; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v35224; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc5225; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v25226; GFX6-IEEE-NEXT: v_frexp_mant_f32_e32 v4, v05227; GFX6-IEEE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v35228; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v1, v15229; GFX6-IEEE-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc5230; GFX6-IEEE-NEXT: v_frexp_exp_i32_f32_e32 v0, v05231; GFX6-IEEE-NEXT: v_mul_f32_e32 v2, v3, v25232; GFX6-IEEE-NEXT: v_sub_i32_e32 v0, vcc, v0, v15233; GFX6-IEEE-NEXT: v_ldexp_f32_e32 v0, v2, v05234; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]5235;5236; GFX6-FLUSH-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:5237; GFX6-FLUSH: ; %bb.0:5238; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5239; GFX6-FLUSH-NEXT: v_mov_b32_e32 v3, 0x7f8000005240; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v2, v15241; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v35242; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc5243; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v25244; GFX6-FLUSH-NEXT: v_frexp_mant_f32_e32 v4, v05245; GFX6-FLUSH-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v35246; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v1, v15247; GFX6-FLUSH-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc5248; GFX6-FLUSH-NEXT: v_frexp_exp_i32_f32_e32 v0, v05249; GFX6-FLUSH-NEXT: v_mul_f32_e32 v2, v3, v25250; GFX6-FLUSH-NEXT: v_sub_i32_e32 v0, vcc, v0, v15251; GFX6-FLUSH-NEXT: v_ldexp_f32_e32 v0, v2, v05252; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]5253;5254; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:5255; GFX10: ; %bb.0:5256; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5257; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v15258; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v15259; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v05260; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v05261; GFX10-NEXT: v_rcp_f32_e32 v2, v25262; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v15263; GFX10-NEXT: v_mul_f32_e32 v2, v3, v25264; GFX10-NEXT: v_ldexp_f32 v0, v2, v05265; GFX10-NEXT: s_setpc_b64 s[30:31]5266;5267; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:5268; GFX11: ; %bb.0:5269; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5270; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v15271; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v15272; GFX11-NEXT: v_frexp_mant_f32_e32 v3, v05273; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v05274; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)5275; GFX11-NEXT: v_rcp_f32_e32 v2, v25276; GFX11-NEXT: v_sub_nc_u32_e32 v0, v0, v15277; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)5278; GFX11-NEXT: v_mul_f32_e32 v2, v3, v25279; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)5280; GFX11-NEXT: v_ldexp_f32 v0, v2, v05281; GFX11-NEXT: s_setpc_b64 s[30:31]5282; EG-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:5283; EG: ; %bb.0:5284; EG-NEXT: CF_END5285; EG-NEXT: PAD5286 %div = fdiv float %x, %y, !fpmath !05287 ret float %div5288}5289 5290!0 = !{float 2.500000e+00}5291 5292attributes #0 = { "denormal-fp-math-f32"="dynamic,dynamic" }5293 5294;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:5295; GCN-IEEE: {{.*}}5296