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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX942 %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX11 %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX11 %s5 6define amdgpu_ps void @flat_atomic_fadd_f32_no_rtn_intrinsic(ptr %ptr, float %data) {7 ; GFX942-LABEL: name: flat_atomic_fadd_f32_no_rtn_intrinsic8 ; GFX942: bb.1 (%ir-block.0):9 ; GFX942-NEXT: liveins: $vgpr0, $vgpr1, $vgpr210 ; GFX942-NEXT: {{ $}}11 ; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr012 ; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr113 ; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub114 ; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr215 ; GFX942-NEXT: FLAT_ATOMIC_ADD_F32 [[REG_SEQUENCE]], [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (s32) on %ir.ptr, !noalias.addrspace !0)16 ; GFX942-NEXT: S_ENDPGM 017 ;18 ; GFX11-LABEL: name: flat_atomic_fadd_f32_no_rtn_intrinsic19 ; GFX11: bb.1 (%ir-block.0):20 ; GFX11-NEXT: liveins: $vgpr0, $vgpr1, $vgpr221 ; GFX11-NEXT: {{ $}}22 ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr023 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr124 ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub125 ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr226 ; GFX11-NEXT: FLAT_ATOMIC_ADD_F32 [[REG_SEQUENCE]], [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (s32) on %ir.ptr, !noalias.addrspace !0)27 ; GFX11-NEXT: S_ENDPGM 028 %ret = call float @llvm.amdgcn.flat.atomic.fadd.f32.p1.f32(ptr %ptr, float %data)29 ret void30}31 32define amdgpu_ps float @flat_atomic_fadd_f32_rtn_intrinsic(ptr %ptr, float %data) {33 ; GFX942-LABEL: name: flat_atomic_fadd_f32_rtn_intrinsic34 ; GFX942: bb.1 (%ir-block.0):35 ; GFX942-NEXT: liveins: $vgpr0, $vgpr1, $vgpr236 ; GFX942-NEXT: {{ $}}37 ; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr038 ; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr139 ; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub140 ; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr241 ; GFX942-NEXT: [[FLAT_ATOMIC_ADD_F32_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_ADD_F32_RTN [[REG_SEQUENCE]], [[COPY2]], 0, 1, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (s32) on %ir.ptr, !noalias.addrspace !0)42 ; GFX942-NEXT: $vgpr0 = COPY [[FLAT_ATOMIC_ADD_F32_RTN]]43 ; GFX942-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr044 ;45 ; GFX11-LABEL: name: flat_atomic_fadd_f32_rtn_intrinsic46 ; GFX11: bb.1 (%ir-block.0):47 ; GFX11-NEXT: liveins: $vgpr0, $vgpr1, $vgpr248 ; GFX11-NEXT: {{ $}}49 ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr050 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr151 ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub152 ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr253 ; GFX11-NEXT: [[FLAT_ATOMIC_ADD_F32_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_ADD_F32_RTN [[REG_SEQUENCE]], [[COPY2]], 0, 1, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (s32) on %ir.ptr, !noalias.addrspace !0)54 ; GFX11-NEXT: $vgpr0 = COPY [[FLAT_ATOMIC_ADD_F32_RTN]]55 ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr056 %ret = call float @llvm.amdgcn.flat.atomic.fadd.f32.p1.f32(ptr %ptr, float %data)57 ret float %ret58}59 60define amdgpu_ps void @flat_atomic_fadd_f32_no_rtn_atomicrmw(ptr %ptr, float %data) {61 ; GFX942-LABEL: name: flat_atomic_fadd_f32_no_rtn_atomicrmw62 ; GFX942: bb.1 (%ir-block.0):63 ; GFX942-NEXT: liveins: $vgpr0, $vgpr1, $vgpr264 ; GFX942-NEXT: {{ $}}65 ; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr066 ; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr167 ; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub168 ; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr269 ; GFX942-NEXT: FLAT_ATOMIC_ADD_F32 [[REG_SEQUENCE]], [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr)70 ; GFX942-NEXT: S_ENDPGM 071 ;72 ; GFX11-LABEL: name: flat_atomic_fadd_f32_no_rtn_atomicrmw73 ; GFX11: bb.1 (%ir-block.0):74 ; GFX11-NEXT: liveins: $vgpr0, $vgpr1, $vgpr275 ; GFX11-NEXT: {{ $}}76 ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr077 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr178 ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub179 ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr280 ; GFX11-NEXT: FLAT_ATOMIC_ADD_F32 [[REG_SEQUENCE]], [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr)81 ; GFX11-NEXT: S_ENDPGM 082 %ret = atomicrmw fadd ptr %ptr, float %data syncscope("wavefront") monotonic, !amdgpu.no.fine.grained.memory !083 ret void84}85 86define amdgpu_ps float @flat_atomic_fadd_f32_rtn_atomicrmw(ptr %ptr, float %data) {87 ; GFX942-LABEL: name: flat_atomic_fadd_f32_rtn_atomicrmw88 ; GFX942: bb.1 (%ir-block.0):89 ; GFX942-NEXT: liveins: $vgpr0, $vgpr1, $vgpr290 ; GFX942-NEXT: {{ $}}91 ; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr092 ; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr193 ; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub194 ; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr295 ; GFX942-NEXT: [[FLAT_ATOMIC_ADD_F32_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_ADD_F32_RTN [[REG_SEQUENCE]], [[COPY2]], 0, 1, implicit $exec, implicit $flat_scr :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr)96 ; GFX942-NEXT: $vgpr0 = COPY [[FLAT_ATOMIC_ADD_F32_RTN]]97 ; GFX942-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr098 ;99 ; GFX11-LABEL: name: flat_atomic_fadd_f32_rtn_atomicrmw100 ; GFX11: bb.1 (%ir-block.0):101 ; GFX11-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2102 ; GFX11-NEXT: {{ $}}103 ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0104 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1105 ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1106 ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2107 ; GFX11-NEXT: [[FLAT_ATOMIC_ADD_F32_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_ADD_F32_RTN [[REG_SEQUENCE]], [[COPY2]], 0, 1, implicit $exec, implicit $flat_scr :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr)108 ; GFX11-NEXT: $vgpr0 = COPY [[FLAT_ATOMIC_ADD_F32_RTN]]109 ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0110 %ret = atomicrmw fadd ptr %ptr, float %data syncscope("wavefront") monotonic, !amdgpu.no.fine.grained.memory !0111 ret float %ret112}113 114declare float @llvm.amdgcn.flat.atomic.fadd.f32.p1.f32(ptr, float)115 116!0 = !{}117