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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 -stop-after=instruction-select < %s | FileCheck -check-prefix=GFX942 %s3 4define amdgpu_ps <2 x half> @flat_atomic_fadd_v2f16_rtn(ptr %ptr, <2 x half> %data) {5 ; GFX942-LABEL: name: flat_atomic_fadd_v2f16_rtn6 ; GFX942: bb.1 (%ir-block.0):7 ; GFX942-NEXT: liveins: $vgpr0, $vgpr1, $vgpr28 ; GFX942-NEXT: {{ $}}9 ; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr010 ; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr111 ; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub112 ; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr213 ; GFX942-NEXT: [[FLAT_ATOMIC_PK_ADD_F16_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_PK_ADD_F16_RTN [[REG_SEQUENCE]], [[COPY2]], 0, 1, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (<2 x s16>) on %ir.ptr)14 ; GFX942-NEXT: $vgpr0 = COPY [[FLAT_ATOMIC_PK_ADD_F16_RTN]]15 ; GFX942-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr016 %ret = atomicrmw fadd ptr %ptr, <2 x half> %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !017 ret <2 x half> %ret18}19 20define amdgpu_ps <2 x half> @flat_atomic_fadd_v2f16_saddr_rtn(ptr inreg %ptr, <2 x half> %data) {21 ; GFX942-LABEL: name: flat_atomic_fadd_v2f16_saddr_rtn22 ; GFX942: bb.1 (%ir-block.0):23 ; GFX942-NEXT: liveins: $sgpr0, $sgpr1, $vgpr024 ; GFX942-NEXT: {{ $}}25 ; GFX942-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr026 ; GFX942-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr127 ; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub128 ; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr029 ; GFX942-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]]30 ; GFX942-NEXT: [[FLAT_ATOMIC_PK_ADD_F16_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_PK_ADD_F16_RTN [[COPY3]], [[COPY2]], 0, 1, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (<2 x s16>) on %ir.ptr)31 ; GFX942-NEXT: $vgpr0 = COPY [[FLAT_ATOMIC_PK_ADD_F16_RTN]]32 ; GFX942-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr033 %ret = atomicrmw fadd ptr %ptr, <2 x half> %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !034 ret <2 x half> %ret35}36 37define amdgpu_ps void @flat_atomic_fadd_v2f16_no_rtn(ptr %ptr, <2 x half> %data) {38 ; GFX942-LABEL: name: flat_atomic_fadd_v2f16_no_rtn39 ; GFX942: bb.1 (%ir-block.0):40 ; GFX942-NEXT: liveins: $vgpr0, $vgpr1, $vgpr241 ; GFX942-NEXT: {{ $}}42 ; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr043 ; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr144 ; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub145 ; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr246 ; GFX942-NEXT: FLAT_ATOMIC_PK_ADD_F16 [[REG_SEQUENCE]], [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (<2 x s16>) on %ir.ptr)47 ; GFX942-NEXT: S_ENDPGM 048 %ret = atomicrmw fadd ptr %ptr, <2 x half> %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !049 ret void50}51 52define amdgpu_ps void @flat_atomic_fadd_v2f16_saddr_no_rtn(ptr inreg %ptr, <2 x half> %data) {53 ; GFX942-LABEL: name: flat_atomic_fadd_v2f16_saddr_no_rtn54 ; GFX942: bb.1 (%ir-block.0):55 ; GFX942-NEXT: liveins: $sgpr0, $sgpr1, $vgpr056 ; GFX942-NEXT: {{ $}}57 ; GFX942-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr058 ; GFX942-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr159 ; GFX942-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub160 ; GFX942-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr061 ; GFX942-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]]62 ; GFX942-NEXT: FLAT_ATOMIC_PK_ADD_F16 [[COPY3]], [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr :: (load store syncscope("agent") seq_cst (<2 x s16>) on %ir.ptr)63 ; GFX942-NEXT: S_ENDPGM 064 %ret = atomicrmw fadd ptr %ptr, <2 x half> %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !065 ret void66}67 68!0 = !{}69